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91. 发明申请

US20080248621A1 Integrated Non-Volatile Memory And Peripheral Circuitry Fabrication 有权
标题翻译：集成非易失性存储器和外围电路制造
公开(公告)号：US20080248621A1
公开(公告)日：2008-10-09
申请号：US12058512
申请日：2008-03-28
申请人： James Kai , Tuan Pham , Masaaki Higashitani , George Matamis , Takashi Orimoto
发明人： James Kai , Tuan Pham , Masaaki Higashitani , George Matamis , Takashi Orimoto
IPC分类号： H01L21/336
CPC分类号： H01L27/11529 , H01L27/105 , H01L27/115 , H01L27/11526 , H01L27/11536 , H01L27/11539
摘要： Non-volatile memory and integrated memory and peripheral circuitry fabrication processes are provided. Sets of charge storage regions, such as NAND strings including multiple non-volatile storage elements, are formed over a semiconductor substrate using a layer of charge storage material such as a first layer of polysilicon. An intermediate dielectric layer is provided over the charge storage regions. A layer of conductive material such as a second layer of polysilicon is deposited over the substrate and etched to form the control gates for the charge storage regions and the gate regions of the select transistors for the sets of storage elements. The first layer of polysilicon is removed from a portion of the substrate, facilitating fabrication of the select transistor gate regions from only the second layer of polysilicon. Peripheral circuitry formation is also incorporated into the fabrication process to form the gate regions for devices such as high voltage and logic transistors. The gate regions of these devices can be formed from the layer forming the control gates of the memory array.
摘要翻译：提供非易失性存储器和集成存储器和外围电路制造工艺。使用诸如第一多晶硅层的电荷存储材料层在半导体衬底上形成诸如包括多个非易失性存储元件的NAND串的电荷存储区的集合。中间电介质层设置在电荷存储区域的上方。将诸如第二多晶硅层的导电材料层沉积在衬底上并被蚀刻以形成用于存储元件组的选择晶体管的电荷存储区域和栅极区域的控制栅极。从衬底的一部分去除第一层多晶硅，便于仅从第二层多晶硅制造选择晶体管栅极区。外围电路形成也被并入到制造过程中以形成诸如高电压和逻辑晶体管的器件的栅极区域。这些器件的栅极区域可以由形成存储器阵列的控制栅极的层形成。

92. 发明申请

US20080050875A1 Methods of fabricating embedded flash memory devices 审中-公开
标题翻译：制造嵌入式闪存设备的方法
公开(公告)号：US20080050875A1
公开(公告)日：2008-02-28
申请号：US11645576
申请日：2006-12-27
申请人： Jung-Ho Moon , Chul-Soon Kwon , Jae-Min Yu , Young-Cheon Jeong , In-Gu Yoon , Byeong-Cheol Lim
发明人： Jung-Ho Moon , Chul-Soon Kwon , Jae-Min Yu , Young-Cheon Jeong , In-Gu Yoon , Byeong-Cheol Lim
IPC分类号： H01L21/336
CPC分类号： H01L27/105 , H01L27/11526 , H01L27/11539
摘要： A method of fabricating a compound device includes forming a first gate insulating pattern on a semiconductor substrate including a first region and a second region, forming a second gate insulating layer on the first gate insulating pattern, and after forming the second gate insulating layer, forming a well in the second region of the semiconductor substrate.
摘要翻译：一种复合器件的制造方法包括在包括第一区域和第二区域的半导体衬底上形成第一栅极绝缘图案，在第一栅极绝缘图案上形成第二栅极绝缘层，在形成第二栅极绝缘层之后，形成在半导体衬底的第二区域中的阱。

93. 发明申请

US20080029806A1 SEMICONDUCTOR DEVICE INCLUDING NONVOLATILE MEMORY AND METHOD FOR FABRICATING THE SAME 有权
标题翻译：包含非易失性存储器的半导体器件及其制造方法
公开(公告)号：US20080029806A1
公开(公告)日：2008-02-07
申请号：US11865894
申请日：2007-10-02
申请人： Masataka TAKEBUCHI , Fumitaka Arai
发明人： Masataka TAKEBUCHI , Fumitaka Arai
IPC分类号： H01L29/78
CPC分类号： H01L21/823857 , H01L27/112 , H01L27/1122 , H01L27/11529 , H01L27/11536 , H01L27/11539 , H01L27/11546
摘要： A semiconductor device including a nonvolatile memory and the fabrication method of the same is described formed on a semiconductor substrate. According to the semiconductor device, a second gate electrode film is used for a gate electrode film of a logic circuit, and for a control gate electrode film of a nonvolatile memory. As the second gate electrode film is formed at a relatively later step in fabrication, subsequent thermal process may be avoided. The gate structure is suitable for miniaturization of the transistor in the logic circuit.
摘要翻译：描述了在半导体衬底上形成包括非易失性存储器的半导体器件及其制造方法。根据半导体器件，第二栅电极膜用于逻辑电路的栅电极膜和非易失性存储器的控制栅电极膜。由于第二栅极电极膜在相对较后的制造步骤中形成，所以可以避免随后的热处理。栅极结构适合于逻辑电路中的晶体管的小型化。

94. 发明授权

US07211486B2 Method of manufacturing a semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US07211486B2
公开(公告)日：2007-05-01
申请号：US11175050
申请日：2005-07-06
申请人： Kazuyuki Ozeki , Yuji Goto
发明人： Kazuyuki Ozeki , Yuji Goto
IPC分类号： H01L21/336
CPC分类号： H01L27/11534 , H01L21/28273 , H01L27/0629 , H01L27/105 , H01L27/11521 , H01L27/11526 , H01L27/11531 , H01L27/11539 , H01L29/66825 , H01L29/7881
摘要： When memory cells of EEPROM and a capacitor element are formed on a same semiconductor substrate, the number of processes is prevented from increasing and a manufacturing cost is reduced. Furthermore, reliability of the capacitor element is improved, and characteristics of the memory cells, a MOS transistor, and so on are prevented from changing. A pair of left and right memory cells is formed in a memory cell formation region of a P-type silicon substrate, being symmetrical to each other with respect to a source region, and a capacitor element formed of a lower electrode, a capacitor insulation film, and an upper electrode is formed in a capacitor element formation region of the same P-type silicon substrate. The lower electrode of the capacitor element is formed by patterning a polysilicon film provided for forming control gates of the pair of memory cells.
摘要翻译：当EEPROM和电容器元件的存储单元形成在相同的半导体衬底上时，防止了工艺数量的增加并且降低了制造成本。此外，电容器元件的可靠性得到改善，并且防止存储单元，MOS晶体管等的特性改变。一对左右存储单元形成在P型硅衬底的存储单元形成区域中，相对于源极区域彼此对称，并且电容器元件由下电极，电容器绝缘膜并且在相同P型硅衬底的电容器元件形成区域中形成上电极。电容器元件的下电极通过图案化用于形成该对存储单元的控制栅极的多晶硅膜而形成。

95. 发明授权

US07029968B2 Method of forming a PIP capacitor 失效
标题翻译：形成PIP电容器的方法
公开(公告)号：US07029968B2
公开(公告)日：2006-04-18
申请号：US10729084
申请日：2003-12-05
申请人： Kuo-Chi Tu
发明人： Kuo-Chi Tu
IPC分类号： H01L21/8242
CPC分类号： H01L27/11526 , H01L27/0629 , H01L27/105 , H01L27/11539 , H01L27/11543 , H01L28/40
摘要： A method of forming a polysilicon-insulator-polysilicon (PIP) capacitor in a mixed mode semiconductor device. A floating gate of a split gate transistor and a bottom electrode of a PIP capacitor are formed from a first polysilicon layer using a single lithography mask. Poly-oxide regions are formed over the floating gate and the bottom electrode, and an oxide layer is formed over the poly-oxide regions and other exposed material layers. A nitride layer is deposited over the oxide layer. The nitride layer is patterned to expose at least a portion of the poly-oxide region over the bottom electrode. The exposed oxide layer and poly-oxide region are removed from over the bottom electrode. A second polysilicon layer is deposited over the structure, and a control gate of the split gate transistor and a top electrode of the PIP capacitor are formed from the second polysilicon layer using a single lithography mask.
摘要翻译：一种在混合模式半导体器件中形成多晶硅 - 绝缘体 - 多晶硅（PIP）电容器的方法。分离栅极晶体管的浮置栅极和PIP电容器的底部电极由使用单个光刻掩模的第一多晶硅层形成。多晶氧化物区域形成在浮置栅极和底部电极上，并且在多晶氧化物区域和其它暴露的材料层上形成氧化物层。在氧化物层上沉积氮化物层。图案化氮化物层以暴露底部电极上的多晶氧化物区域的至少一部分。暴露的氧化物层和多晶氧化物区域从底部电极上去除。在结构上沉积第二多晶硅层，并且使用单个光刻掩模由第二多晶硅层形成分离栅极晶体管的控制栅极和PIP电容器的顶部电极。

96. 发明申请

US20060008986A1 Method of manufacturing a semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US20060008986A1
公开(公告)日：2006-01-12
申请号：US11175050
申请日：2005-07-06
申请人： Kazuyuki Ozeki , Yuji Goto
发明人： Kazuyuki Ozeki , Yuji Goto
IPC分类号： H01L21/336
CPC分类号： H01L27/11534 , H01L21/28273 , H01L27/0629 , H01L27/105 , H01L27/11521 , H01L27/11526 , H01L27/11531 , H01L27/11539 , H01L29/66825 , H01L29/7881
摘要： When memory cells of EEPROM and a capacitor element are formed on a same semiconductor substrate, the number of processes is prevented from increasing and a manufacturing cost is reduced. Furthermore, reliability of the capacitor element is improved, and characteristics of the memory cells, a MOS transistor, and so on are prevented from changing. A pair of left and right memory cells is formed in a memory cell formation region of a P-type silicon substrate, being symmetrical to each other with respect to a source region, and a capacitor element formed of a lower electrode, a capacitor insulation film, and an upper electrode is formed in a capacitor element formation region of the same P-type silicon substrate. The lower electrode of the capacitor element is formed by patterning a polysilicon film provided for forming control gates of the pair of memory cells.
摘要翻译：当EEPROM和电容器元件的存储单元形成在相同的半导体衬底上时，防止了工艺数量的增加并且降低了制造成本。此外，电容器元件的可靠性得到改善，并且防止存储单元，MOS晶体管等的特性改变。一对左右存储单元形成在P型硅衬底的存储单元形成区域中，相对于源极区域彼此对称，并且电容器元件由下电极，电容器绝缘膜并且在相同P型硅衬底的电容器元件形成区域中形成上电极。电容器元件的下电极通过图案化用于形成该对存储单元的控制栅极的多晶硅膜而形成。

97. 发明申请

US20050085041A1 Method for fabricating semiconductor memory device 有权
标题翻译：半导体存储器件的制造方法
公开(公告)号：US20050085041A1
公开(公告)日：2005-04-21
申请号：US10959984
申请日：2004-10-08
申请人： Masatoshi Arai
发明人： Masatoshi Arai
IPC分类号： H01L21/336 , H01L21/822 , H01L21/8234 , H01L21/8239 , H01L21/8246 , H01L21/8247 , H01L27/088 , H01L27/105 , H01L29/78
CPC分类号： H01L27/11568 , H01L27/105 , H01L27/11526 , H01L27/11539 , Y10S438/961
摘要： A method for fabricating a semiconductor memory device in which a logic circuit and a nonvolatile memory are provided on a semiconductor substrate includes the steps of: forming an isolation region; forming a protective film made of an insulating material over the semiconductor substrate in a logic circuit region and a nonvolatile memory region; selectively introducing impurity ions in part of the semiconductor substrate in the logic circuit region; and removing the protective film formed over the logic circuit region. The step of introducing the impurity ions is performed before the step of removing the protective film is performed.
摘要翻译：一种用于制造半导体存储器件的方法，其中在半导体衬底上设置有逻辑电路和非易失性存储器包括以下步骤：形成隔离区; 在逻辑电路区域和非易失性存储区域中在半导体衬底上形成由绝缘材料制成的保护膜; 在半导体衬底的一部分中选择性地将杂质离子引入到逻辑电路区域中; 以及去除在逻辑电路区域上形成的保护膜。引入杂质离子的步骤是在除去保护膜的步骤之前进行的。

98. 发明申请

US20050042828A1 Semiconductor device with split gate electrode structure and method for manufacturing the semiconductor device 失效
标题翻译：具有分裂栅电极结构的半导体器件和用于制造半导体器件的方法
公开(公告)号：US20050042828A1
公开(公告)日：2005-02-24
申请号：US10920158
申请日：2004-08-18
申请人： Jung-Ho Moon , Jae-Min Yu , Don-Woo Lee , Chul-Soon Kwon , In-Gu Yoon , Yong-Sun Lee , Jae-Hyun Park
发明人： Jung-Ho Moon , Jae-Min Yu , Don-Woo Lee , Chul-Soon Kwon , In-Gu Yoon , Yong-Sun Lee , Jae-Hyun Park
IPC分类号： H01L27/10 , H01L21/336 , H01L21/8247 , H01L27/105 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： H01L27/11526 , H01L27/105 , H01L27/11539
摘要： A semiconductor device includes a substrate divided into a memory cell region and a logic region. A split gate electrode structure is formed in a memory cell region of a substrate. A silicon oxide layer is formed on a sidewall of the split gate electrode structure and a surface of the substrate. A word line is formed on the silicon oxide layer that is positioned on the sidewall of the split gate electrode structure. The word line has an upper width and a lower width. The lower width is greater than the upper width. A logic gate pattern is formed on a logic region of the substrate. The logic gate pattern has a thickness thinner than the lower width of the word line.
摘要翻译：半导体器件包括分为存储单元区域和逻辑区域的衬底。在基板的存储单元区域中形成分割栅电极结构。在分离栅电极结构的侧壁和基板的表面上形成氧化硅层。在位于分离栅电极结构的侧壁上的氧化硅层上形成字线。字线具有上宽度和下宽度。较低的宽度大于上部宽度。在基板的逻辑区域上形成逻辑门图案。逻辑门图案具有比字线的较低宽度更薄的厚度。

99. 发明申请

US20040212007A1 Method of forming different oxide thickness for high voltage transistor and memory cell tunnel dieletric 有权
标题翻译：形成高压晶体管和存储单元隧道消失的不同氧化物厚度的方法
公开(公告)号：US20040212007A1
公开(公告)日：2004-10-28
申请号：US10850300
申请日：2004-05-19
发明人： Geeng-Chuan Chern , Amitay Levi , Dana Lee
IPC分类号： H01L029/788 , H01L021/8238
CPC分类号： H01L27/11526 , H01L21/823462 , H01L27/105 , H01L27/11539 , Y10S438/981
摘要： A semiconductor memory device and method for making the same, where a memory cell and high voltage MOS transistor are formed on the same substrate. An insulating layer is formed having a first portion that insulates the control and floating gates of the memory cell from each other, and a second portion that insulates the poly gate from the substrate in the MOS transistor. The insulating layer is formed so that its first portion has a smaller thickness than that of its second portion.
摘要翻译：一种半导体存储器件及其制造方法，其中存储单元和高电压MOS晶体管形成在同一衬底上。形成绝缘层，其具有将存储单元的控制和浮置栅极彼此绝缘的第一部分和将MOS晶体管中的多晶硅栅极与衬底绝缘的第二部分。绝缘层形成为使得其第一部分的厚度小于其第二部分的厚度。

100. 发明授权

US06589843B1 Methods of forming FLASH field effect transistor gates and non-FLASH field effect transistor gates 有权
标题翻译：形成FLASH场效应晶体管栅极和非FLASH场效应晶体管栅极的方法
公开(公告)号：US06589843B1
公开(公告)日：2003-07-08
申请号：US10043430
申请日：2002-01-09
申请人： Kevin L. Beaman
发明人： Kevin L. Beaman
IPC分类号： H01L21336
CPC分类号： H01L27/11526 , H01L27/115 , H01L27/11539
摘要： Methods of forming FLASH field effect transistor gates and a non-FLASH field effect transistor gates are described. In one implementation, a substrate comprising first and second semiconductive material portions is provided. A FLASH transistor gate is partially formed to include at least a first gate dielectric material received over the first semiconductive material portion, a floating gate material overlying the first gate dielectric material, and a second gate dielectric material received over the floating gate material. The second gate dielectric material comprises silicon nitride. In a common oxidizing step, the silicon nitride of the second gate dielectric material and the second semiconductive material portion are oxidized effective to form both a) a gate oxide layer of a non-FLASH transistor gate overlying the second semiconductive material portion, and b) silicon dioxide as part of the second gate dielectric material of the FLASH transistor gate. Additional implementations are contemplated.
摘要翻译：描述形成FLASH场效应晶体管栅极和非FLASH场效应晶体管栅极的方法。在一个实施方案中，提供了包括第一和第二半导体材料部分的基板。闪存晶体管栅极部分地形成为包括容纳在第一半导体材料部分上的至少第一栅极电介质材料，覆盖第一栅极电介质材料的浮置栅极材料和在浮置栅极材料上接收的第二栅极电介质材料。第二栅极电介质材料包括氮化硅。在通常的氧化步骤中，第二栅极电介质材料和第二半导体材料部分的氮化硅被有效氧化以形成a）覆盖第二半导体材料部分的非FLASH晶体管栅极的栅极氧化物层，以及b）二氧化硅作为FLASH晶体管栅极的第二栅极电介质材料的一部分。考虑附加实现。

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