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91. 发明申请

US20060030087A1 Compliant substrate for a heteroepitaxial structure and method for making same 审中-公开
标题翻译：用于异质外延结构的合适衬底及其制造方法
公开(公告)号：US20060030087A1
公开(公告)日：2006-02-09
申请号：US11224078
申请日：2005-09-13
申请人： Takeshi Akatsu
发明人： Takeshi Akatsu
IPC分类号： H01L21/84
CPC分类号： H01L21/2654 , C30B29/60 , H01L21/76254 , H01L21/76259
摘要： The present invention relates to a compliant substrate having a top surface for receiving a heteroepitaxial structure or heteroepitaxial layer. This substrate comprises a carrier substrate, a top single-crystalline layer, a buried layer located between the carrier substrate and the top layer, and a weakened region located in the top layer or between the top layer and the buried layer such that the compliant substrate facilitates relaxed growth of a heteroepitaxial layer or structure upon the top surface. The invention also relates to the combination of the compliant substrate and a heteroepitaxial layer provided thereon, as well as to a method of making the compliant substrate and combination.
摘要翻译：本发明涉及具有用于接收异质外延结构或异质外延层的顶表面的顺应性衬底。该衬底包括载体衬底，顶部单晶层，位于载体衬底和顶层之间的掩埋层以及位于顶层中或顶层和掩埋层之间的弱化区域，使得柔性衬底促进顶表面上异质外延层或结构的松弛生长。本发明还涉及顺应性衬底和其上提供的异质外延层的组合，以及制造柔顺衬底和组合的方法。

92. 发明申请

US20040140479A1 Compliant substrate for a heteroepitaxial structure and method for making same 审中-公开
标题翻译：用于异质外延结构的合适衬底及其制造方法
公开(公告)号：US20040140479A1
公开(公告)日：2004-07-22
申请号：US10753171
申请日：2004-01-06
发明人： Takeshi Akatsu
IPC分类号： H01L031/0328
CPC分类号： H01L21/2654 , C30B29/60 , H01L21/76254 , H01L21/76259
摘要： The present invention relates to a compliant substrate having a top surface for receiving a heteroepitaxial structure or heteroepitaxial layer. This substrate comprises a carrier substrate, a top single-crystalline layer, a buried layer located between the carrier substrate and the top layer, and a weakened region located in the top layer or between the top layer and the buried layer such that the compliant substrate facilitates relaxed growth of a heteroepitaxial layer or structure upon the top surface. The invention also relates to the combination of the compliant substrate and a heteroepitaxial layer provided thereon, as well as to a method of making the compliant substrate and combination.
摘要翻译：本发明涉及具有用于接收异质外延结构或异质外延层的顶表面的顺应性衬底。该衬底包括载体衬底，顶部单晶层，位于载体衬底和顶层之间的掩埋层以及位于顶层中或顶层和掩埋层之间的弱化区域，使得柔性衬底促进顶表面上异质外延层或结构的松弛生长。本发明还涉及顺应性衬底和其上提供的异质外延层的组合，以及制造柔顺衬底和组合的方法。

93. 发明授权

US5399900A Isolation region in a group III-V semiconductor device and method of making the same 失效
标题翻译： III-V族半导体器件中的隔离区及其制造方法
公开(公告)号：US5399900A
公开(公告)日：1995-03-21
申请号：US133552
申请日：1993-10-08
申请人： Kei-Yu Ko , Samuel Chen , Shuit-Tong Lee
发明人： Kei-Yu Ko , Samuel Chen , Shuit-Tong Lee
IPC分类号： H01L21/265 , H01L21/76 , H01L27/02 , H01L27/12
CPC分类号： H01L21/2654 , H01L21/7605
摘要： A semiconductor device having in a body of a group III-V semiconductor material at least one isolation region which is stable at temperatures up to about 900.degree. C. The isolation region is formed of ions of a group III or V element which are implanted into the body and then thermally annealed at a temperature of between 650.degree. C. and 900.degree. C. This provides the regions with voids which remove free carriers and makes the region highly resistive.
摘要翻译：一种半导体器件，其具有III-V族半导体材料的主体，该至少一个隔离区在高达约900℃的温度下是稳定的。隔离区由III或V族元素的离子形成，然后在650℃至900℃的温度下进行热退火。这为这些区域提供了去除游离载体并使该区域具有高电阻性的空隙。

94. 发明授权

US5396089A Method of generating active semiconductor structures by means of starting structures which have a 2D charge carrier layer parallel to the surface 失效
标题翻译：通过具有平行于表面的2D电荷载体层的起始结构产生有源半导体结构的方法
公开(公告)号：US5396089A
公开(公告)日：1995-03-07
申请号：US34315
申请日：1993-03-22
申请人： Andreas D. Wieck , Klaus Ploog
发明人： Andreas D. Wieck , Klaus Ploog
IPC分类号： H01L21/265 , H01L21/28 , H01L21/335 , H01L29/06 , H01L29/32 , H01L29/423 , H01L29/51 , H01L29/775 , H01L29/86 , H01L29/20 , H01L29/78 , H01L29/161 , H01L29/205
CPC分类号： H01L21/2654 , B82Y10/00 , H01L21/28158 , H01L29/0653 , H01L29/32 , H01L29/4238 , H01L29/51 , H01L29/513 , H01L29/66469 , H01L29/775 , H01L29/86
摘要： A unipolar electronic component is proposed with a quasi one dimensional carrier channel which has all the characteristics of an FET. This component can be very simply produced, has "self-alignment" and linear gates with a low capacity in place of planar gates. In this way a very high operating frequency of the component is possible. The structure comprises an initially homogenous 2D-layer with a high carrier mobility which is formed by epitaxy of for example GaAs. The implantation of focussed ions (for example Ga.sup.+ with 100 keV) locally destroys the conductivity of the electron layer. The irradiated regions remain insulating at low temperature or room temperature even after illuminating the cristal with bandgap radiation. The writing in of the insulating layer is carried out along two paths on the chip so that the 2D-carrier layer is subdivided into three regions insulated from one another. The source and drain are only connected by a narrow channel 44 the width of which is continuously tunable by a gate potential which is simultaneously applied to the two gate regions relative to the source, so that a pronounced change of the carrier concentration and thus of the channel resistance arises. The specification also describes integrated circuits made using the same methods.
摘要翻译：提出了具有FET的所有特性的准一维载流子通道的单极电子元件。该部件可以非常简单地制造，具有“自对准”和具有低容量的线性门来代替平面栅极。以这种方式，组件的非常高的工作频率是可能的。该结构包括通过例如GaAs的外延形成的具有高载流子迁移率的初始均匀的2D层。聚焦离子（例如Ga +与100keV）的注入会局部地破坏电子层的导电性。即使在用带隙辐射照射碎片之后，照射区域在低温或室温下保持绝缘。绝缘层的写入沿着芯片上的两条路径进行，使得2D载体层被细分成彼此绝缘的三个区域。源极和漏极仅由窄通道44连接，窄通道44的宽度可通过栅极电位连续可调，该栅极电位同时施加到相对于源极的两个栅极区域，使得载流子浓度明显变化通道电阻出现。本说明书还描述了使用相同方法制造的集成电路。

95. 发明授权

US4960718A MESFET device having a semiconductor surface barrier layer 失效
标题翻译： MESFET器件具有半导体表面阻挡层
公开(公告)号：US4960718A
公开(公告)日：1990-10-02
申请号：US218506
申请日：1988-07-05
申请人： Olaleye A. Aina
发明人： Olaleye A. Aina
IPC分类号： H01L21/265 , H01L21/306 , H01L21/76 , H01L29/47 , H01L29/812
CPC分类号： H01L29/812 , H01L21/2654 , H01L21/26546 , H01L21/2656 , H01L21/30612 , H01L21/7605 , H01L29/475
摘要： An InP MESFET having a semiconductor surface barrier layer formed of GaInP or AlInP. The semiconductor surface barrier layer is formed between an active layer and a gate electrode and the barrier height of the gate for the semiconductor surface barrier layer is higher than the barrier height of the gate for InP. In a method of forming an InP MESFET according to the present invention, the semiconductor surface barrier layer is formed by high dose implantation of Ga or Al into the active region. Surface barrier layers formed of other compounds, for example GaInAsP or AlInAsP, which have a lattice match with InP can be formed by other methods such as epitaxial growth.
摘要翻译：具有由GaInP或AlInP形成的半导体表面阻挡层的InP MESFET。半导体表面阻挡层形成在有源层和栅极之间，并且用于半导体表面阻挡层的栅极的势垒高度高于InP栅极的势垒高度。在根据本发明的形成InP MESFET的方法中，半导体表面势垒层通过Ga或Al的高剂量注入形成到有源区中。与InP具有晶格匹配的其它化合物（例如GaInAsP或AlInAsP）形成的表面阻挡层可以通过其它方法如外延生长形成。

96. 发明授权

US4708883A Annealing process 失效
标题翻译：退火过程
公开(公告)号：US4708883A
公开(公告)日：1987-11-24
申请号：US821139
申请日：1986-01-23
申请人： Harold J. Hovel , Thomas F. Kuech
发明人： Harold J. Hovel , Thomas F. Kuech
IPC分类号： C23C14/06 , C23C14/58 , H01L21/265 , H01L21/324 , B05D3/06
CPC分类号： C23C14/0617 , C23C14/58 , C23C14/5806 , C23C14/5893 , H01L21/2654 , H01L21/3245
摘要： An ion implantation annealing source for a controlled excess of the most volatile element of a multielement compound semiconductor whereby the source is provided with interstices and contains the most volatile element of the multielement semiconductor; and process of ion implantation employing the annealing source.
摘要翻译：一种离子注入退火源，用于多元素化合物半导体中最易挥发的元素受控过量，其中源极具有间隙并且包含多元素半导体中最易挥发的元素; 以及使用退火源的离子注入工艺。

97. 发明授权

US4646116A Semiconductor device having an electroluminescent diode 失效
标题翻译：具有电致发光二极管的半导体器件
公开(公告)号：US4646116A
公开(公告)日：1987-02-24
申请号：US675483
申请日：1984-11-28
申请人： Jacques J. Varon , Marie-Josephe Martin , Marc Mahieu
发明人： Jacques J. Varon , Marie-Josephe Martin , Marc Mahieu
IPC分类号： H01L21/20 , H01L21/265 , H01L33/00 , H01L33/02
CPC分类号： H01L33/025 , H01L21/2654 , H01L33/0062
摘要： A semiconductor device includes an electroluminescent diode, which is obtained from at least one epitaxial layer of a III-V compound vapor-deposited on a substrate which is also of a III-V compound. The invention is characterized in that, preferably before the epitaxial layer is vapor deposited, a layer having a disturbed crystal structure is provided at the surface of the substrate, as a result of which the substrate does not generate radiation.
摘要翻译：一种半导体器件包括电致发光二极管，该电致发光二极管是由气相沉积在也是III-V族化合物的衬底上的III-V族化合物的至少一个外延层获得的。本发明的特征在于，优选在外延层被气相沉积之前，在衬底的表面上设置具有干扰的晶体结构的层，结果衬底不产生辐射。

98. 发明授权

US4642879A Method of making self-aligned FET using GaAs substrate and spatially controlled implanted channel region 失效
标题翻译：使用GaAs衬底和空间控制的注入沟道区域制作自对准FET的方法
公开(公告)号：US4642879A
公开(公告)日：1987-02-17
申请号：US555547
申请日：1983-11-28
申请人： Haruo Kawata , Hidetoshi Nishi
发明人： Haruo Kawata , Hidetoshi Nishi
IPC分类号： H01L21/265 , H01L21/318 , H01L21/324 , H01L21/338 , H01L29/10 , H01L29/47 , H01L29/812 , H01L21/263
CPC分类号： H01L21/265 , H01L21/2654 , H01L21/318 , H01L21/3245 , H01L29/1029 , H01L29/475 , H01L29/812 , Y10S148/084 , Y10S148/14
摘要： High transconductance is obtained in GaAs FET's by forming a channel layer having a carrier concentration monotonously decreasing from the interface of the channel layer and a control gate toward the interface of the channel layer and the substrate it is formed in. This is established by ion implantation of the channel layer through an insulating layer, preferably an AlN layer, on a GaAs substrate. An AlN layer is preferable since it has no adverse effects on the GaAs substrate during ion implantation and the following heat treatment, allowing higher uniformity of the threshold voltages of the FET's.
摘要翻译：在GaAs FET中通过形成从沟道层的界面和控制栅极向沟道层的界面和其形成的衬底的界面单调递减的沟道层获得高跨导。这是通过离子注入建立的通过GaAs衬底上的绝缘层，优选AlN层。 AlN层是优选的，因为它在离子注入和随后的热处理期间对GaAs衬底没有不利影响，从而允许FET的阈值电压更高的均匀性。

99. 发明授权

US4602965A Method of making FETs in GaAs by dual species implantation of silicon and boron 失效
标题翻译：通过硅和硼的双物种注入在GaAs中制造FET的方法
公开(公告)号：US4602965A
公开(公告)日：1986-07-29
申请号：US589267
申请日：1984-03-13
申请人： Philip J. McNally
发明人： Philip J. McNally
IPC分类号： H01L21/265 , H01L29/812 , H01L21/20
CPC分类号： H01L29/812 , H01L21/2654 , H01L21/26546 , Y10S148/084
摘要： A method of preparing an active surface layer on a semi-insulating GaAs substrate comprising the steps of ion implanting a surface layer with silicon to form an n-type active layer and ion implanting a buried diffusion layer beneath the active layer with boron to prevent defects in the substrate from influencing the active region. The method is particularly useful for GaAs MESFETs.
摘要翻译：一种在半绝缘GaAs衬底上制备活性表面层的方法，包括以下步骤：用硅离子注入表面层以形成n型有源层，并用硼离子注入有源层下方的掩埋扩散层以防止缺陷在底物中影响活性区。该方法对于GaAs MESFET尤其有用。

100. 发明授权

US4545824A Process for producing a GaAs or InP semiconductor by pre-implantation followed by transition metal diffusion 失效
标题翻译：用于通过预注入然后过渡金属扩散来生产GaAs或InP半导体的工艺
公开(公告)号：US4545824A
公开(公告)日：1985-10-08
申请号：US444429
申请日：1982-11-24
申请人： Michel Salvi , Pierre N. Favennec , Marcel Gauneau
发明人： Michel Salvi , Pierre N. Favennec , Marcel Gauneau
IPC分类号： H01L21/22 , H01L21/223 , H01L21/265 , H01L29/207 , H01L21/263 , H01L21/24
CPC分类号： H01L21/2233 , H01L21/22 , H01L21/2654 , H01L29/207
摘要： Process for producing a semiconductor component by diffusion with prior ion implantation. According to the invention, an impurity of oxygen, fluorine, chlorine or bromine having chemical affinity with the diffusion impurity is implanted in the semiconductor substrate of GaAs or InP before thermally diffusing Zn, Cd or Fe in the substrate. The diffusion is thus limited in depth.
摘要翻译：用先前的离子注入通过扩散制造半导体组件的方法。根据本发明，在GaAs或InP的半导体衬底中，在衬底内热扩散Zn，Cd或Fe之前，将与扩散杂质具有化学亲和性的氧，氟，氯或溴的杂质注入。因此扩散深度受到限制。

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