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91. 发明授权

US09299443B1 Modifying program pulses based on inter-pulse period to reduce program noise 有权
标题翻译：基于脉冲间周期修改程序脉冲以减少程序噪声
公开(公告)号：US09299443B1
公开(公告)日：2016-03-29
申请号：US14500655
申请日：2014-09-29
申请人： SanDisk Technologies Inc.
发明人： Yingda Dong , Liang Pang , Jiahui Yuan
IPC分类号： G11C11/34 , G11C16/10 , G11C16/34 , G11C16/04
CPC分类号： G11C16/10 , G11C11/5628 , G11C16/0466 , G11C16/3454 , G11C16/3459 , G11C2211/5621
摘要： Techniques are provided for more accurately programming memory cells by reducing program noise caused by charge loss in a programming pass in which the number of verify tests varies in different program loops. In an nth program loop, at least one programming characteristic is modified based on the number (N) of data states which were subject to verify tests in the n-1st program loop. For example, a reduced step size or pulse duration, or an elevated bit line voltage (Vbl) can be used. The reduction in the step size or pulse duration, or the increase in Vbl, is proportional to N. The modification of the at least one programming characteristic results in a slowdown of the programming of the memory cells so that program noise is reduced.
摘要翻译：提供了通过减少在不同程序循环中验证测试数量变化的编程遍历中的电荷损失引起的程序噪声来更准确地编程存储器单元的技术。在第n个程序循环中，基于在第n-1程序循环中进行验证测试的数据状态数（N）来修改至少一个编程特性。例如，可以使用减小的步长或脉冲持续时间，或升高的位线电压（Vbl）。步长或脉冲持续时间的减小或Vbl的增加与N成比例。至少一个编程特性的修改导致存储器单元的编程减慢，从而减少编程噪声。

92. 发明申请

US20160071595A1 Controlling Pass Voltages To Minimize Program Disturb In Charge-Trapping Memory 有权
标题翻译：控制通过电压以最大限度地减少电荷陷阱存储器中的程序干扰
公开(公告)号：US20160071595A1
公开(公告)日：2016-03-10
申请号：US14481304
申请日：2014-09-09
申请人： SanDisk Technologies Inc.
发明人： Yingda Dong , Hong-Yan Chen
IPC分类号： G11C16/10 , G11C16/34 , G11C16/04
CPC分类号： G11C16/10 , G11C11/5628 , G11C16/0466 , G11C16/0483 , G11C16/3427 , G11C16/3459
摘要： Techniques are provided for preventing program disturb of unselected memory cells during programming of a selected memory cell in a NAND string which includes a continuous charge-trapping layer, either in a two-dimensional or three-dimensional configuration. In such a NAND string, regions between the memory cells can be inadvertently programmed as parasitic cells due to the program voltage and pass voltages on the word lines. For programmed cells, an upshift in threshold voltage due to a parasitic cell can be avoided by providing a higher pass voltage on an adjacent later-programmed word line than on an adjacent previously-programmed word line. For erased cells, an upshift in threshold voltage due to the parasitic cells can be reduced by progressively lowering the pass voltage on the adjacent later-programmed word line. The lowering can occur when memory cells of a lowest target data state complete programming.
摘要翻译：提供技术用于防止在包括二维或三维配置的连续电荷俘获层的NAND串中的所选存储单元的编程期间防止未选择存储单元的程序干扰。在这种NAND串中，由于程序电压和字线上的通过电压，存储单元之间的区域可能被无意地编程为寄生单元。对于编程单元，通过在相邻的后面编程的字线上提供比在相邻的预先编程的字线上更高的通过电压，可以避免由寄生电池引起的阈值电压升档。对于已擦除的单元，可以通过逐渐降低相邻的后编程字线上的通过电压来降低由寄生电池引起的阈值电压升档。当最低目标数据状态的存储单元完成编程时，可能会发生降低。

93. 发明申请

US20160042792A1 NONVOLATILE MEMORY DEVICES AND DRIVING METHODS THEREOF 审中-公开
公开(公告)号：US20160042792A1
公开(公告)日：2016-02-11
申请号：US14887595
申请日：2015-10-20
申请人： Kyung-Hwa Kang , Sang-Wan Nam , Donghyuk Chae , ChiWeon Yoon
发明人： Kyung-Hwa Kang , Sang-Wan Nam , Donghyuk Chae , ChiWeon Yoon
IPC分类号： G11C16/04 , G11C16/08
CPC分类号： G11C16/0483 , G11C16/0466 , G11C16/08 , G11C16/24 , H01L23/528 , H01L27/11565 , H01L27/1157 , H01L27/11582
摘要： Nonvolatile memory devices including memory cell arrays with a plurality of cell strings connected between a substrate and a plurality of bit lines and selected by selection lines, and a gating circuit configured to drive the selection lines in at least two directions.

94. 发明申请

US20160020220A1 NON-VOLATILE ONE-TIME PROGRAMMABLE MEMORY DEVICE 有权
标题翻译：非易失性一次可编程存储器件
公开(公告)号：US20160020220A1
公开(公告)日：2016-01-21
申请号：US14495507
申请日：2014-09-24
申请人： QUALCOMM Incorporated
发明人： Xia Li , Jeffrey Junhao Xu , Xiao Lu , Bin Yang , Jun Yuan , Xiaonan Chen , Zhongze Wang
IPC分类号： H01L27/115 , G11C16/10 , G11C16/26 , H01L29/792
CPC分类号： H01L29/792 , G11C16/0466 , G11C16/10 , G11C16/26 , G11C17/18 , H01L27/11206 , H01L29/4234 , H01L29/513 , H01L29/517
摘要： An apparatus includes a metal gate, a substrate material, and an oxide layer between the metal gate and the substrate material. The oxide layer includes a hafnium oxide layer contacting the metal gate and a silicon dioxide layer contacting the substrate material and contacting the hafnium oxide layer. The metal gate, the substrate material, and the oxide layer are included in a one-time programmable (OTP) memory device. The OTP memory device includes a transistor. A non-volatile state of the OTP memory device is based on a threshold voltage shift of the OTP memory device.
摘要翻译：一种装置包括金属栅极，衬底材料和金属栅极和衬底材料之间的氧化物层。氧化物层包括与金属栅极接触的氧化铪层和与衬底材料接触并与氧化铪层接触的二氧化硅层。金属栅极，衬底材料和氧化物层包括在一次性可编程（OTP）存储器件中。 OTP存储器件包括晶体管。 OTP存储器件的非易失性状态基于OTP存储器件的阈值电压偏移。

95. 发明申请

US20160012871A1 INTEGRATED CIRCUIT FOR STORING INFORMATION 审中-公开
标题翻译：集成电路存储信息
公开(公告)号：US20160012871A1
公开(公告)日：2016-01-14
申请号：US14858631
申请日：2015-09-18
申请人： SK hynix Inc.
发明人： Kyung-Hoon KIM
IPC分类号： G11C7/22 , G11C5/14
CPC分类号： G11C7/22 , G11C5/147 , G11C7/062 , G11C7/067 , G11C7/106 , G11C7/1072 , G11C11/4091 , G11C16/0466 , G11C16/26
摘要： An integrated circuit includes a variable resistance unit including at least one transistor that receives a control signal and changes a resistance through the transistor in response to the control signal in a programming operation mode and an information detection unit configured to detect programming information in response to an output voltage of the variable resistance unit in a normal operation mode.
摘要翻译：集成电路包括：可变电阻单元，包括至少一个晶体管，其接收控制信号并响应于编程操作模式中的控制信号改变通过晶体管的电阻;以及信息检测单元，其被配置为响应于控制信号检测编程信息可变电阻单元的输出电压处于正常工作模式。

96. 发明授权

US09230981B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US09230981B2
公开(公告)日：2016-01-05
申请号：US14448832
申请日：2014-07-31
申请人： SK hynix Inc.
发明人： Sung Lae Oh , Go Hyun Lee , Chang Man Son , Soo Nam Jung
IPC分类号： G11C16/04 , H01L27/115 , H01L29/792 , G11C5/06 , G11C16/08 , G11C16/24
CPC分类号： H01L27/11582 , G11C5/063 , G11C16/0466 , G11C16/0483 , G11C16/08 , G11C16/24 , H01L27/11573 , H01L29/7926
摘要： Provided are a semiconductor device. The semiconductor device includes a memory block including a drain select line, word lines, and a source select line, which are spaced apart from one another and stacked in a direction perpendicular to a semiconductor substrate; and a peripheral circuit including a switching device connected to a bit line, which is disposed under a vertical channel layer vertically passing through the drain select line, the word lines, and the source select line.
摘要翻译：提供半导体器件。该半导体器件包括一个包括漏极选择线，字线和源极选择线的存储块，它们彼此间隔开并沿垂直于半导体衬底的方向堆叠; 以及包括连接到位线的开关装置的外围电路，其位于垂直通过漏极选择线，字线和源选择线的垂直沟道层下方。

97. 发明授权

US09224477B2 Apparatuses and methods for coupling load current to a common source 有权
标题翻译：将负载电流耦合到公共源的装置和方法
公开(公告)号：US09224477B2
公开(公告)日：2015-12-29
申请号：US14725619
申请日：2015-05-29
申请人： Micron Technology, Inc.
发明人： Toru Tanzawa
IPC分类号： G11C5/14 , G11C16/04 , G11C16/06 , G11C11/56
CPC分类号： G11C16/0483 , G11C7/065 , G11C7/067 , G11C7/08 , G11C11/5621 , G11C11/5671 , G11C16/0408 , G11C16/0466 , G11C16/06 , G11C16/26
摘要： Apparatuses and methods are disclosed, including an apparatus with a string of charge storage devices coupled to a common source, a first switch coupled between the string of charge storage devices and a load current source, and a second switch coupled between the load current source and the common source. Additional apparatuses and methods are described.
摘要翻译：公开了装置和方法，包括具有耦合到公共源的电荷存储装置串的装置，耦合在电荷存储装置串和负载电流源之间的第一开关和耦合在负载电流源和共同的来源。描述附加的装置和方法。

98. 发明申请

US20150371707A1 Semiconductor Memory Having Both Volatile and Non-Volatile Functionality and Method of Operating 有权
标题翻译：具有挥发性和非挥发性功能的半导体存储器和操作方法
公开(公告)号：US20150371707A1
公开(公告)日：2015-12-24
申请号：US14839682
申请日：2015-08-28
申请人： Zeno Semiconductor, Inc.
发明人： Yuniarto Widjaja
IPC分类号： G11C14/00
CPC分类号： G11C14/0018 , G11C11/404 , G11C16/0408 , G11C16/0466 , G11C16/0483 , G11C16/225 , G11C2211/4016 , H01L21/28273 , H01L21/28282 , H01L21/84 , H01L27/105 , H01L27/108 , H01L27/10802 , H01L27/10826 , H01L27/10879 , H01L27/10897 , H01L27/11521 , H01L27/11526 , H01L27/11531 , H01L27/11568 , H01L27/11573 , H01L27/1203 , H01L29/0649 , H01L29/42324 , H01L29/4234 , H01L29/66825 , H01L29/66833 , H01L29/7841 , H01L29/785 , H01L29/7885 , H01L29/7887 , H01L29/792 , H01L29/7923
摘要： Semiconductor memory having both volatile and non-volatile modes and methods of operation. A semiconductor storage device includes a plurality of memory cells each having a floating body for storing, reading and writing data as volatile memory. The device includes a floating gate or trapping layer for storing data as non-volatile memory, the device operating as volatile memory when power is applied to the device, and the device storing data from the volatile memory as non-volatile memory when power to the device is interrupted.
摘要翻译：具有易失性和非易失性模式和操作方法的半导体存储器。半导体存储装置包括多个存储单元，每个存储单元具有用于存储，读取和写入数据作为易失性存储器的浮动体。该装置包括用于将数据存储为非易失性存储器的浮动栅极或捕获层，该装置在向该装置施加电力时作为易失性存储器工作，并且该装置将来自易失性存储器的数据作为非易失性存储器，设备中断

99. 发明授权

US09203018B2 Memory element and memory device 有权
标题翻译：存储器元件和存储器件
公开(公告)号：US09203018B2
公开(公告)日：2015-12-01
申请号：US14196240
申请日：2014-03-04
申请人： Sony Corporation
发明人： Kazuhiro Ohba , Takeyuki Sone , Masayuki Shimuta , Shuichiro Yasuda
IPC分类号： G11C11/00 , H01L45/00 , H01L27/24 , G11C13/00 , G11C16/04 , G11C16/34
CPC分类号： H01L45/08 , G11C13/0069 , G11C16/0466 , G11C16/3418 , H01L27/2436 , H01L27/2472 , H01L45/085 , H01L45/1233 , H01L45/1266 , H01L45/141 , H01L45/142 , H01L45/143 , H01L45/144 , H01L45/146
摘要： A memory element with a first electrode, a memory layer, and a second electrode in this order. The memory layer includes a resistance change layer provided on the first electrode side, an ion source layer provided on the second electrode side, an intermediate layer provided between the resistance change layer and the ion source layer, and a barrier layer provided at least either between the ion source layer and the intermediate layer, or between the intermediate layer and the resistance change layer.
摘要翻译：具有第一电极，存储层和第二电极的存储元件。存储层包括设置在第一电极侧的电阻变化层，设置在第二电极侧的离子源层，设置在电阻变化层和离子源层之间的中间层，以及设置在第一电极侧之间的至少一个离子源层和中间层，或中间层和电阻变化层之间。

100. 发明授权

US09202571B2 Vertically-integrated nonvolatile memory devices having laterally-integrated ground select transistors 有权
标题翻译：具有横向集成的地选择晶体管的垂直集成的非易失性存储器件
公开(公告)号：US09202571B2
公开(公告)日：2015-12-01
申请号：US14272765
申请日：2014-05-08
申请人： Samsung Electronics Co., Ltd.
发明人： Sunil Shim , Jaehun Jeong , Jaehoon Jang , Kihyun Kim
IPC分类号： G11C11/34 , G11C16/04 , H01L27/115
CPC分类号： H01L27/11582 , G11C16/0408 , G11C16/0466 , G11C16/0483 , H01L27/11519 , H01L27/11551 , H01L27/11556 , H01L27/1157
摘要： Nonvolatile memory devices utilize vertically-stacked strings of nonvolatile memory cells (e.g., NAND-type strings) that can be selectively coupled to common source lines within a substrate. This selective coupling may be provided by lateral ground select transistors having different threshold voltages that account for different lateral spacings between the vertically-stacked strings of nonvolatile memory cells and the common source lines.
摘要翻译：非易失性存储器件利用垂直堆叠的非易失性存储器单元串（例如，NAND型串），其可选择性地耦合到衬底内的公共源极线。该选择耦合可以由具有不同阈值电压的横向接地选择晶体管提供，这些阈值电压考虑了非垂直堆叠的非易失性存储单元串与公共源极线之间的不同横向间隔。

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