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91. 发明授权

US09489320B2 System and method for transferring an active state between a powerful processor and a less powerful processor 有权
公开(公告)号：US09489320B2
公开(公告)日：2016-11-08
申请号：US15169267
申请日：2016-05-31
申请人： DELL PRODUCTS, LP
发明人： Chitrak Gupta , Sushma Basavarajaiah
IPC分类号： G06F1/16 , G06F9/44 , G06F13/12 , G06F9/48
CPC分类号： G06F13/126 , G06F1/1626 , G06F1/1632 , G06F9/4403 , G06F9/441 , G06F9/4856
摘要： An information handling system includes a tablet with a processor, and a dock with a second processor that determines that the tablet is coupled to the dock, boots the dock, receives a request for the tablet to be uncoupled from the dock, creates a migration image with state information of the dock and that identifies a process running on the dock, and sends the migration image to the tablet. The first processor receives the request, boots the tablet, receives the migration image from the second processor, loads the state information to the tablet, and launches the first process.

92. 发明申请

US20160291984A1 RESOURCE PROCESSING METHOD, OPERATING SYSTEM, AND DEVICE 审中-公开
标题翻译：资源处理方法，操作系统和设备
公开(公告)号：US20160291984A1
公开(公告)日：2016-10-06
申请号：US15175742
申请日：2016-06-07
申请人： HUAWEI TECHNOLOGIES CO.,LTD.
发明人： Gang Lu , Jianfeng Zhan , Yunwei Gao , Chongkang Tan , Dongliang Xue
IPC分类号： G06F9/44 , G06F13/24
CPC分类号： G06F9/4406 , G06F9/4403 , G06F9/4405 , G06F9/4408 , G06F9/45533 , G06F9/5083 , G06F13/24
摘要： A resource processing method, an operating system, and a device are provided. The method is applied to a multi-core operating system, where the multi-core operating system includes a management operating system and multiple load operating systems that run on a host machine and includes a physical resource pool. According to the method, after selecting, in processor cores allocated to a first load operating system, a startup processor core that starts up the first load operating system, the management operating system instructs the startup processor core to read a mapping relationship that is from a virtual memory address to a physical memory address and that is required for executing a startup mirror of the first load operating system. Then, the management operating system instructs the startup processor core to execute the startup mirror pre-constructed for the first load operating system to start up the first load operating system.
摘要翻译：提供资源处理方法，操作系统和设备。该方法应用于多核操作系统，其中多核操作系统包括管理操作系统和在主机上运行并包括物理资源池的多个加载操作系统。根据该方法，在分配给第一负载操作系统的处理器核心中选择启动第一负载操作系统的启动处理器核心之后，管理操作系统指示启动处理器核心读取来自虚拟内存地址到物理内存地址，这是执行第一个加载操作系统的启动镜像所必需的。然后，管理操作系统指示启动处理器内核执行为第一加载操作系统预先构建的启动镜，以启动第一加载操作系统。

93. 发明申请

US20160266631A1 SINGLE WIRE SERIAL INTERFACE 审中-公开
公开(公告)号：US20160266631A1
公开(公告)日：2016-09-15
申请号：US15041979
申请日：2016-02-11
申请人： Skyworks Solutions, Inc.
发明人： Kevin P. d'Angelo , David Alan Brown , John Sung K. So , Jan Nilsson , Richard K. Williams
IPC分类号： G06F1/28 , G06F9/44 , G06F1/12
CPC分类号： G06F1/28 , G06F1/04 , G06F1/06 , G06F1/12 , G06F1/22 , G06F9/4403 , G06F13/4291 , G09G3/3406 , G09G5/10 , G09G2320/0233 , H05B33/0803 , H05B33/0815 , H05B33/0851
摘要： A single wire serial interface for power ICs and other devices is provided. To use the interface, a device is configured to include an EN/SET input pin. A counter within the device counts clock pulses sent to the EN/SET input pin. The output of the counter is passed to a ROM or other decoder circuit. The ROM selects an operational state for the device that corresponds to the value of the counter. In this way, control states may be selected for the device by sending corresponding clock pulses to the EN/SET pin. Holding the EN/SET pin high causes the device to maintain its operational state. Holding the EN/SET pin low for a predetermined timeout period resets the counter and causes the device to adopt a predetermined configuration (such as off) until new clock pulses are received at the EN/SET pin.

94. 发明申请

US20160231935A1 Memory Configuration Operations for a Computing Device 有权
标题翻译：计算设备的内存配置操作
公开(公告)号：US20160231935A1
公开(公告)日：2016-08-11
申请号：US14618187
申请日：2015-02-10
申请人： ADVANCED MICRO DEVICES, INC.
发明人： Hsiu-Ming Chu
IPC分类号： G06F3/06
CPC分类号： G06F9/4406 , G06F9/4403
摘要： In the described embodiments, a computing device executes firmware to perform a startup initialization operation, wherein performing the startup initialization operation comprises setting an operating state of a memory in the computing device to a default low performance memory operating state. After completing the startup initialization operation, the computing device executes an operating system, wherein executing the operating system comprises performing a memory test to determine a high performance memory operating state. The computing device then sets one or more memory configuration values based on the high performance memory operating state, the one or more memory configuration values controlling the operation of the memory.
摘要翻译：在所描述的实施例中，计算设备执行固件以执行启动初始化操作，其中执行启动初始化操作包括将计算设备中的存储器的操作状态设置为默认的低性能存储器操作状态。在完成启动初始化操作之后，计算设备执行操作系统，其中执行操作系统包括执行存储器测试以确定高性能存储器操作状态。然后，计算设备基于高性能存储器操作状态来设置一个或多个存储器配置值，所述一个或多个存储器配置值控制存储器的操作。

95. 发明授权

US09412443B2 Processor system having variable capacity memory 有权
标题翻译：具有可变容量存储器的处理器系统
公开(公告)号：US09412443B2
公开(公告)日：2016-08-09
申请号：US14205817
申请日：2014-03-12
申请人： KABUSHIKI KAISHA TOSHIBA
发明人： Hiroki Noguchi , Shinobu Fujita , Keiko Abe
IPC分类号： G06F13/00 , G11C13/00 , G06F9/44 , G11C14/00 , G11C11/00
CPC分类号： G11C13/004 , G06F9/4403 , G11C11/1673 , G11C11/1693 , G11C13/0002 , G11C13/0023 , G11C13/0069 , G11C14/0081
摘要： According to one embodiment, a processor system includes a variable capacity memory. The memory includes a memory cell array including basic units, each of the basic units including one cell transistor and one variable resistance element, a mode selector switching between first and second modes, a read/write of one bit executed in 2n basic units (n is an integer) among the basic units in the first mode, the read/write of the one bit executed in 2m basic units (m is an integer, m≠n) among the basic units in the second mode, and a control circuit which controls the switching between the first and second modes.
摘要翻译：根据一个实施例，处理器系统包括可变容量存储器。该存储器包括一个包括基本单元的存储单元阵列，每个基本单元包括一个单元晶体管和一个可变电阻元件，在第一和第二模式之间切换的模式选择器，以2n个基本单位执行的一个位的读/写是第一模式中的基本单元之间的整数），在第二模式中的基本单元中以2m个基本单位（m为整数，m≠n）执行的一位的读/写，以及控制电路控制第一和第二模式之间的切换。

96. 发明申请

US20160202997A1 PORTABLE DEVICE OPERATING SYSTEM 审中-公开
标题翻译：便携式设备操作系统
公开(公告)号：US20160202997A1
公开(公告)日：2016-07-14
申请号：US14593880
申请日：2015-01-09
申请人： SHENG-CHIA OPTICAL CO., LTD.
发明人： Jinn-Yuan LAY
IPC分类号： G06F9/44 , G06F1/32
CPC分类号： G06F1/3243 , G06F1/3206 , G06F1/3287 , G06F9/4403 , Y02D10/152 , Y02D10/171
摘要： A portable device booting system consists of a booting firmware and a circuit system which includes a microprocessor, a sensor and a power control circuit. The booting is performed by a booting gesture. When the booting gesture is applied, the position of the portable device is changed accordingly that causes sensor physical values changed and also triggers the microprocessor from sleep mode to working state. Then the microprocessor reads the sensor physical value to verify if it is compliant with the defined boot up orientation as well as the sequential. If negative, the microprocessor will set the sensor and itself getting back to the sleep mode. Once the applied booting gesture meets the defined orientation and sequential, the microprocessor will release the turning ON signal to the utility circuit and power control circuit to turn the device ON.
摘要翻译：便携式设备启动系统由引导固件和包括微处理器，传感器和功率控制电路的电路系统组成。引导通过启动手势执行。当应用启动手势时，相应地改变便携式设备的位置，导致传感器物理值改变，并且还将微处理器从睡眠模式触发到工作状态。然后微处理器读取传感器物理值，以验证其是否符合定义的启动方向以及顺序。如果为负值，则微处理器将设置传感器和本身恢复到睡眠模式。一旦应用启动手势满足定义的方向和顺序，微处理器将释放打开信号到公用电路和电源控制电路以打开设备。

97. 发明申请

US20160188534A1 COMPUTING SYSTEM WITH PARALLEL MECHANISM AND METHOD OF OPERATION THEREOF 审中-公开
标题翻译：具有并行机制的计算系统及其操作方法
公开(公告)号：US20160188534A1
公开(公告)日：2016-06-30
申请号：US14674399
申请日：2015-03-31
申请人： Samsung Electronics Co., Ltd.
发明人： Tameesh Suri , Manu Awasthi , Mrinmoy Ghosh
IPC分类号： G06F15/82 , G06F9/44 , G06F9/50
CPC分类号： G06F9/4403 , G06F9/4411 , G06F9/5016 , G06F12/0646
摘要： A computing system includes: an identification block configured to determine a structural profile for representing a parallel structure of architectural components; and an arrangement block, coupled to the identification block, configured to generate memory sets based on the structural profile for representing the parallel structure.
摘要翻译：计算系统包括：识别块，被配置为确定用于表示架构组件的并行结构的结构简档; 以及耦合到所述识别块的配置块，被配置为基于用于表示所述并行结构的所述结构轮廓来生成存储器组。

98. 发明授权

US09378133B2 Autonomous initialization of non-volatile random access memory in a computer system 有权
标题翻译：计算机系统中非易失性随机存取存储器的自动初始化
公开(公告)号：US09378133B2
公开(公告)日：2016-06-28
申请号：US13997945
申请日：2011-09-30
申请人： Murugasamy K. Nachimuthu , Mohan Kumar , Dimitrios Ziakas
发明人： Murugasamy K. Nachimuthu , Mohan Kumar , Dimitrios Ziakas
IPC分类号： G06F12/02 , G06F9/44
CPC分类号： G06F12/0246 , G06F9/4403
摘要： A non-volatile random access memory (NVRAM) is used in a computer system to store information that allows the NVRAM to autonomously initialize itself at power-on. The computer system includes a processor, an NVRAM controller coupled to the processor, and an NVRAM that comprises the NVRAM controller. The NVRAM is byte-rewritable and byte-erasable by the processor. The NVRAM stores a memory interface table containing information for the NVRAM controller to autonomously initialize the NVRAM upon power-on of the computer system without interacting with the processor and firmware outside of the NVRAM. The information is provided by the NVRAM controller to the processor to allow the processor to access the NVRAM.
摘要翻译：在计算机系统中使用非易失性随机存取存储器（NVRAM）来存储允许NVRAM在上电时自动初始化的信息。计算机系统包括处理器，耦合到处理器的NVRAM控制器和包括NVRAM控制器的NVRAM。 NVRAM是字节可重写的，可由处理器字节擦除。 NVRAM存储包含NVRAM控制器的信息的存储器接口表，用于在计算机系统上电时自动初始化NVRAM，而不与NVRAM之外的处理器和固件交互。该信息由NVRAM控制器提供给处理器，以允许处理器访问NVRAM。

99. 发明授权

US09377829B2 Information processing system includes an operating unit and main element and reboot unit that reboots only operating unit in asynchronization with main element 有权
标题翻译：信息处理系统包括操作单元和主要元件以及重新启动单元，其仅与主要元件异步地重新启动操作单元
公开(公告)号：US09377829B2
公开(公告)日：2016-06-28
申请号：US14283348
申请日：2014-05-21
申请人： Yoh Masuyama , Tadashi Nagata , Keisuke Iwasa
发明人： Yoh Masuyama , Tadashi Nagata , Keisuke Iwasa
IPC分类号： G06F9/00 , G06F1/24 , G06F9/44
CPC分类号： G06F9/4406 , G06F1/24 , G06F9/4401 , G06F9/4403 , G06F9/4416 , G06F9/451 , H04N1/00928 , H04N1/32667 , H04N2201/0094
摘要： An information processing system includes an operating unit that receives an input in response to a user operation and that runs under a first operating system; and a main body that runs under a second operating system and operates in response to the input received by the operating unit. The main body includes a generation unit that generates a command to direct rendering of a screen corresponding to an application being executed, and a command transmission control unit that provides control to transmit the command to the operating unit. The operating unit includes a receiving unit that receives the command from the main body, a screen rendering unit that renders the screen in accordance with the command received by the receiving unit, a display unit that displays the screen rendered by the screen rendering unit, and a reboot unit that reboots the operating unit in asynchronization with the main body.
摘要翻译：信息处理系统包括：操作单元，其接收响应于用户操作并在第一操作系统下运行的输入; 以及在第二操作系统下运行并且响应于由操作单元接收的输入而操作的主体。主体包括：生成单元，生成用于指示与正在执行的应用程序相对应的画面的呈现命令;以及命令发送控制单元，其提供向操作单元发送命令的控制。操作单元包括从主体接收命令的接收单元，根据接收单元接收到的命令显示画面的画面呈现单元，显示画面呈现单元呈现的画面的显示单元，以及重新启动单元，重新启动操作单元与主体异步。

100. 发明申请

US20160180094A1 METHOD FOR OPTIMIZING BOOT TIME OF AN INFORMATION HANDLING SYSTEM 有权
标题翻译：优化信息处理系统引导时间的方法
公开(公告)号：US20160180094A1
公开(公告)日：2016-06-23
申请号：US14580389
申请日：2014-12-23
申请人： DELL PRODUCTS, L.P.
发明人： SUNDAR DASAR , YOGESH P. KULKARNI , SUMANTH VIDYADHARA , BILL MUNGER , RAGHAVENDRA VENKATARAMUDU
IPC分类号： G06F21/57 , G06F9/44 , G06F11/14
CPC分类号： G06F21/575 , G06F9/4403 , G06F9/4406 , G06F11/1417 , G06F11/1438
摘要： A method and information handling system (IHS) that optimizes boot time. The method includes a basic input output system (BIOS) performing an authentication check of drivers during an initial boot process. The results of the authentication check are stored along with an unified extensible firmware interface (UEFI) image for each driver in an authentication results data structure (ARDS). In response to receipt of a subsequent request to enable a secure boot of the IHS, when the initial boot process was performed with the secure boot disabled, the ARDS is accessed to determine if any of the drivers failed the authentication check. When none of the drivers have failed the authentication check, the boot process is continued using the UEFI images of the drivers. When at least one of the drivers has failed its authentication check, a notification is output indicating a failure of the authentication check.
摘要翻译：一种优化引导时间的方法和信息处理系统（IHS）。该方法包括在初始引导过程中执行驱动程序的认证检查的基本输入输出系统（BIOS）。认证检查的结果与认证结果数据结构（ARDS）中的每个驱动程序的统一的可扩展固件接口（UEFI）映像一起存储。响应于接收到启用IHS的安全引导的后续请求，当在禁用安全启动时执行初始启动过程时，访问ARDS以确定是否有任何驱动程序认证检查失败。当没有一个驱动程序出现验证检查失败时，使用驱动程序的UEFI映像继续启动进程。当至少其中一个驱动程序的认证检查失败时，会输出指示认证检查失败的通知。

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