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91. 发明授权

US07916812B2 Determining modulo count in sleep capable system 有权
标题翻译：确定睡眠能力系统中的模数
公开(公告)号：US07916812B2
公开(公告)日：2011-03-29
申请号：US11370521
申请日：2006-03-07
申请人： Kevin Stuart Cousineau
发明人： Kevin Stuart Cousineau
IPC分类号： H04L27/00
CPC分类号： H04L27/2602 , G06F7/72 , H04L27/2655 , H04L27/2656
摘要： Apparatus and methods of determining a modulo count of a synchronization number in a sleep capable system. The synchronization number is stored in a comparison register, and a comparison number equal to the largest power of two multiple of the modulus within a predetermined range is subtracted from the synchronization number. If the difference is zero, the difference is stored in the comparison register, replacing the previous number stored in the register. If the difference is less than zero, the number stored in the register remains unchanged. The comparison number is right shifted, resulting in division by two. The process is repeated for a number of loops equal to the power of two, or until the difference is less than the modulus.
摘要翻译：在睡眠能力系统中确定同步数的模数的装置和方法。同步数存储在比较寄存器中，并且从同步数中减去等于预定范围内的模数的两倍的最大功率的比较数。如果差值为零，则差值存储在比较寄存器中，代替存储在寄存器中的上一个数字。如果差值小于零，则寄存器中存储的数字保持不变。比较数字是右移，导致二分。对于等于2的幂的多个回路重复该过程，或直到该差小于该模数。

92. 发明申请

US20110061105A1 PROTECTION OF A PRIME NUMBER GENERATION AGAINST SIDE-CHANNEL ATTACKS 有权
标题翻译：保护一个针对边界通道攻击的主机号码生成
公开(公告)号：US20110061105A1
公开(公告)日：2011-03-10
申请号：US12877330
申请日：2010-09-08
申请人： Frank Cuypers
发明人： Frank Cuypers
IPC分类号： G06F21/00
CPC分类号： H04L63/1441 , G06F7/72 , G06F2207/7204 , G09C1/00 , H04L9/003 , H04L9/302
摘要： A method for protecting the generation, by an electronic circuit, of at least one prime number by testing the primality of successive candidate numbers, including for each candidate number tests of primality with respect to prime numbers of at least one set of consecutive prime numbers, wherein the order of application of the tests is modified at least from one prime number generation to another.
摘要翻译：一种用于通过测试连续的候选号码的原语来保护由电子电路产生至少一个素数的方法，包括针对至少一组连续素数的素数的每个候选数量测试的原语，其中测试的应用顺序至少从一个素数代到另一个修改。

93. 发明申请

US20100138467A1 METHODS OF CALCULATING NEGATIVE INVERSE OF MODULUS 有权
标题翻译：计算模态反演的方法
公开(公告)号：US20100138467A1
公开(公告)日：2010-06-03
申请号：US12618283
申请日：2009-11-13
申请人： Young-sik Kim , Mi-jung Noh , Kyoung-moon Ahn , Sun-soo Shin
发明人： Young-sik Kim , Mi-jung Noh , Kyoung-moon Ahn , Sun-soo Shin
IPC分类号： G06F7/72
CPC分类号： G06F7/72 , G06F7/721 , G06F7/728
摘要： Provided is a method of calculating a negative inverse of a modulus, wherein the negative inverse, which is an essential element in Montgomery multiplication, is quickly obtained. The method includes setting a modulus, defining P obtained by converting the modulus to a negative number, and defining S obtained by subtracting 1 from P, and calculating a negative inverse of the modulus by using P and S.
摘要翻译：提供了一种计算模数的负逆的方法，其中快速获得作为蒙哥马利乘法中的基本要素的负逆。该方法包括设定模量，通过将模数转换为负数来定义P，并定义通过从P中减去1获得的S，并且通过使用P和S计算模量的负逆。

94. 发明授权

US07607165B2 Method and apparatus for multiplication and/or modular reduction processing 有权
公开(公告)号：US07607165B2
公开(公告)日：2009-10-20
申请号：US10096038
申请日：2002-03-11
申请人： Jonathon D. Mellott , Patrick Dennis Rugg
发明人： Jonathon D. Mellott , Patrick Dennis Rugg
IPC分类号： H04L9/00
CPC分类号： G06F7/722 , G06F7/72
摘要： The subject invention relates to a method and apparatus for multiplication of numbers. In a specific embodiment, the subject invention can be used to perform sequential multiplication. The subject invention also pertains to a method and apparatus for modular reduction processing of a number or product of two numbers. In a specific embodiment, sequential multiplication can be incorporated to perform modular reduction processing. The subject method and apparatus can also be utilized for modular exponentiation of large numbers. In a specific embodiment, numbers larger than or equal to 2128 or even higher can be exponentiated. For example, the subject invention can be used for exponentiation of number as large as 21024, 22048, 24096, or even larger.

95. 发明申请

US20090245507A1 DATA PROCESSING SYSTEM AND DATA PROCESSING METHOD 有权
标题翻译：数据处理系统和数据处理方法
公开(公告)号：US20090245507A1
公开(公告)日：2009-10-01
申请号：US12366679
申请日：2009-02-06
申请人： Camille VUILLAUME , Katsuyuki Okeya , Masayuki Yoshino
发明人： Camille VUILLAUME , Katsuyuki Okeya , Masayuki Yoshino
IPC分类号： H04L9/28
CPC分类号： G06F7/72 , G06F2207/7204 , H04L9/3033 , H04L2209/20 , H04L2209/56
摘要： A technique which contributes to materialization of efficient encryption even with devices such as smartcards restricted in memory resource is provided. The system for generating cryptographic keys includes: a calculation unit for reconstructing a large number of small primes, a sieving unit for checking the divisibility of an integer by small primes, a recoding unit for changing the representation of an integer, a primality testing unit. First, the sieving unit eliminates “bad” candidates by checking their divisibility by small primes reconstructed by the calculation unit. After that, the primality of the remaining candidates is tested using the primality testing unit. The primality testing unit uses the recoding unit to change the representation of prime candidates. The primality testing unit performs a primality test using the representation after change. Thus, the number of operations for the primality test can be decreased without further memory requirements.
摘要翻译：提供了即使在存储器资源中限制的诸如智能卡之类的设备的情况下有助于实现有效加密的技术。用于生成加密密钥的系统包括：用于重建大量小素数的计算单元，用于通过小素数检查整数的可分性的筛选单元，用于改变整数表示的记录单元，原始检测单元。首先，筛选单位通过由计算单元重建的小素数来检查其可分性，从而消除“不良”候选者。之后，使用原始性测试单元测试剩余候选人的原始性。原始测试单元使用记录单元来改变主要候选者的表示。原始测试单元使用改变后的表示执行原始测试。因此，可以在没有进一步的存储器要求的情况下减少用于原色测试的操作的数量。

96. 发明申请

US20090185681A1 CIRCUIT ARRANGEMENT AND METHOD FOR RSA KEY GENERATION 有权
标题翻译： RSA密钥生成的电路布置和方法
公开(公告)号：US20090185681A1
公开(公告)日：2009-07-23
申请号：US12063865
申请日：2006-08-09
申请人： Sander Matthijs Van Rijnswou
发明人： Sander Matthijs Van Rijnswou
IPC分类号： H04L9/06 , H04L9/30
CPC分类号： G06F7/72 , G06F2207/7204 , H04L9/302 , H04L9/3249
摘要： In order to further develop a circuit arrangement for as well as a method of performing at least one operation, in particular at least one cryptographic calculation, wherein the problem of creating at least one key, in particular the R[ivest-]S[hamir-] A[dleman] key, satisfying at least one defined digital signature laws, in particular satisfying the German Digital Signature Law, is solved it is proposed that at least one, preferably two, prime numbers (p; q) for key generation, in particular for R[ivest-]S[hamir-]A[dleman] key generation, are searched in compliance with at least one defined digital signature law, in particular with the German Digital Signature Law.
摘要翻译：为了进一步开发电路装置以及执行至少一个操作的方法，特别是至少一个密码计算，其中创建至少一个密钥的问题，特别是R [ivest-] S [hamir - ] A [dleman]键，满足至少一个定义的数字签名规则，特别是满足德国数字签名法，解决了提出至少一个，优选两个用于密钥生成的素数（p; q）特别是对于R [ivest-] S [hamir-] A [dleman]密钥生成，根据至少一个定义的数字签名法搜索，特别是与德国数字签名法。

97. 发明申请

US20090180609A1 Modular Reduction Using a Special Form of the Modulus 有权
标题翻译：使用特殊形式的模量进行模块化减少
公开(公告)号：US20090180609A1
公开(公告)日：2009-07-16
申请号：US12033512
申请日：2008-02-19
申请人： Michel Douguet , Vincent Dupaquis
发明人： Michel Douguet , Vincent Dupaquis
IPC分类号： H04L9/28 , G06F7/72 , H04L9/30
CPC分类号： G06F7/72
摘要： A special form of a modulus and a modified Barrett reduction method are used to perform modular arithmetic in a cryptographic system. The modified Barrett reduction is a method of reducing a number modulo another number without the use of any division. By pre-computing static values used in the Barrett reduction method and by using a special form of the modulus, the calculation of reducing a number modulo another number can be reduced. This can result in a decrease in computation time, speeding up the overall cryptographic process.
摘要翻译：在密码系统中使用模数特殊形式和修改后的Barrett简化方法进行模数运算。修改后的巴雷特简化是一种在不使用任何划分的情况下减少数字模数的方法。通过预先计算Barrett还原法中使用的静态值，并通过使用特殊形式的模数，可以减少模数减少数的计算。这可能导致计算时间的减少，加快了整体加密过程。

98. 发明授权

US07552164B1 Accelerated prime sieving using architecture-optimized partial prime product table 失效
标题翻译：使用架构优化的部分主要产品表加速优质筛选
公开(公告)号：US07552164B1
公开(公告)日：2009-06-23
申请号：US12108513
申请日：2008-04-24
申请人： Tamas Visegrady , Nicholas Wu , Joseph Harfouch
发明人： Tamas Visegrady , Nicholas Wu , Joseph Harfouch
IPC分类号： G06F7/00
CPC分类号： G06F7/72 , G06F7/38 , G06F2207/7204 , H04L9/3033 , H04L2209/125 , H04L2209/127
摘要： This embodiment teaches a variation of GCD-based sieving, building tables of prime products, but intentionally restricting the size of table entries to fit within a single machine word. This combination allows one to mix advantages of the two most popular sieves, while retaining the simple and straightforward structure of the simpler one. Divisor length restriction can provide significant savings in the number of long divisions, but may be implemented with only two very specific primitives. The two primitives offer better optimization capabilities than a fully generic multiword arithmetic library.
摘要翻译：该实施例教导了基于GCD的筛选，主要产品的构建表的变化，但是有意地限制表条目的大小以适合单个机器词。这种组合允许混合两种最受欢迎的筛子的优点，同时保持简单而简单的结构。除数长度限制可以大大节省长部分的数量，但可以仅用两个非常特定的原语来实现。这两个原语提供比完全通用的多字算术库更好的优化功能。

99. 发明授权

US07536564B2 Method for encrypting a calculation using a modular function 有权
标题翻译：使用模块化功能加密计算的方法
公开(公告)号：US07536564B2
公开(公告)日：2009-05-19
申请号：US10476359
申请日：2002-04-29
申请人： Pierre-Yvan Liardet , Fabrice Romain
发明人： Pierre-Yvan Liardet , Fabrice Romain
IPC分类号： H04L21/00
CPC分类号： G06F7/72 , G06F21/755 , G06F2207/7247
摘要： The invention concerns a method for encrypting, with a random quantity (r), a calculation using at least a modular operation (3), the method consisting in multiplying a first modulo (n) by said random quantity, in taking as modulo of the operation, the result (m) of said multiplication and in carrying out a modular reduction of the result of the operation, on the basis of the first modulo (n).
摘要翻译：本发明涉及一种使用至少模块化操作（3）以随机数（r）加密计算的方法，所述方法包括将第一模（n）乘以所述随机数，以模数操作，所述乘法的结果（m）和基于第一模（n）执行操作结果的模块化减少。

100. 发明申请

US20090077144A1 METHOD AND APPARATUS FOR PERFORMING FINITE FIELD CALCULATIONS 有权
标题翻译：用于执行有限计算的方法和装置
公开(公告)号：US20090077144A1
公开(公告)日：2009-03-19
申请号：US12101590
申请日：2008-04-11
申请人： Robert J. Lambert
发明人： Robert J. Lambert
IPC分类号： G06F7/57
CPC分类号： G06F7/72 , G06F7/724 , G06F7/725 , G06F7/726
摘要： In general terms, the invention provides a finite field engine and methods for operating on elements in a finite field. The finite field engine provides finite field sub-engines suitable for any finite field size requiring a fixed number of machine words. The engine reuses these engines, along with some general purpose component or specific component providing modular reduction associated with the exact reduction (polynomial or prime) of a specific finite field. The engine has wordsized suitable code capable of adding, subtracting, multiplying, squaring, or inverting finite field elements, as long as the elements are representable in no more than the given number of words. The wordsized code produces unreduced values. Specific reduction is then applied to the unreduced value, as is suitable for the specific finite field. In this way, fast engines can be produced for many specific finite fields, without duplicating the bulk of the engine instructions (program).
摘要翻译：一般来说，本发明提供了一种有限域引擎和用于在有限域中对元素进行操作的方法。有限域引擎提供适合于需要固定数量的机器字的任何有限域大小的有限域子引擎。引擎重新使用这些引擎，以及一些通用组件或特定组件，提供与特定有限域的精确减少（多项式或素数）相关联的模块化减少。只要元素可以表示为不超过给定数量的单词，发动机就已经对适合的代码进行了加密，减法，乘法，平方或反转的适当代码。字节码产生未减少的值。然后将特定的减少应用于未减少的值，如适用于特定有限域。以这种方式，可以为许多特定的有限域生产快速发动机，而不会重复大量的发动机指令（程序）。

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