专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

91. 发明授权

US08327056B1 Processor management using a buffer 有权
标题翻译：处理器管理使用缓冲区
公开(公告)号：US08327056B1
公开(公告)日：2012-12-04
申请号：US13333551
申请日：2011-12-21
申请人： Ting Li Chan , Fredarico E Dutton
发明人： Ting Li Chan , Fredarico E Dutton
IPC分类号： G06F13/00 , G06F3/00
CPC分类号： G06F5/12 , G06F1/3209 , G06F1/3237 , G06F1/3287 , G06F2205/061 , G06F2205/126 , Y02D10/128 , Y02D10/171 , Y02D50/20
摘要： In an embodiment, an apparatus comprises a buffer, a plurality of processors, and a processor control module. The processor control module is to manage how many of the plurality of processors are used to process data from the buffer based at least in part on an amount of the data stored in the buffer.
摘要翻译：在一个实施例中，一种装置包括缓冲器，多个处理器和处理器控制模块。处理器控制模块至少部分地基于存储在缓冲器中的数据的量来管理多个处理器用于处理来自缓冲器的数据。

92. 发明申请

US20120079144A1 Low Latency First-In-First-Out (FIFO) Buffer 有权
标题翻译：低延迟先进先出（FIFO）缓冲区
公开(公告)号：US20120079144A1
公开(公告)日：2012-03-29
申请号：US13208675
申请日：2011-08-12
申请人： Evgeny Shumsky , Jonathan Kushnir
发明人： Evgeny Shumsky , Jonathan Kushnir
IPC分类号： G06F5/14
CPC分类号： G06F5/12 , G06F5/065 , G06F5/14 , G06F5/16 , G06F2205/065 , G06F2205/126
摘要： Systems and methods are provided for a first-in-first-out buffer. A buffer includes a first sub-buffer configured to store data received from a buffer input, and a second sub-buffer. The second sub-buffer is configured to store data received from either the buffer input or the first sub-buffer and to output data to a buffer output in a same order as that data is received at the buffer input. Buffer control logic is configured to selectively route data from the buffer input or the first sub-buffer to the second sub-buffer so that data received at the buffer input is available to be output from the second sub-buffer in a first-in-first-out manner.
摘要翻译：为先进先出缓冲区提供系统和方法。缓冲器包括被配置为存储从缓冲器输入接收的数据的第一子缓冲器和第二子缓冲器。第二子缓冲器被配置为存储从缓冲器输入或第一子缓冲器接收的数据，并以与在缓冲器输入处接收的数据相同的顺序将数据输出到缓冲器输出。缓冲器控制逻辑被配置为选择性地将数据从缓冲器输入或第一子缓冲器路由到第二子缓冲器，使得在缓冲器输入处接收到的数据可用于以第一子缓冲器的方式从第二子缓冲器输出，先到先得。

93. 发明授权

US07873796B2 Information processor system 有权
标题翻译：信息处理器系统
公开(公告)号：US07873796B2
公开(公告)日：2011-01-18
申请号：US11292218
申请日：2005-12-02
申请人： Seiji Miura
发明人： Seiji Miura
IPC分类号： G06F12/00 , G06F13/00
CPC分类号： G06F5/12 , G06F13/1663 , G06F13/1673
摘要： In an information processor system including a memory device (MEM0), a memory control device (SL0) capable of controlling an operation of the memory device, and a plurality of bus masters (MS0 to MS3) capable of giving access to the memory device through the memory control device, the memory control device includes a control circuit (SDCON) capable of giving a notice of information about a time that a data transfer from the memory device can be started to the bus master related to an access request. The bus master can cause the time information thus given to be a judgment factor as to whether an access request is given to the memory device or not. Consequently, each of the bus masters can avoid the generation of a useless access request and a data transfer to the masters to be accessed can be carried out smoothly.
摘要翻译：在包括存储装置（MEM0），能够控制存储装置的动作的存储器控制装置（SL0）的信息处理器系统中，以及能够通过存储装置访问存储装置的多个总线主机（MS0〜MS3）存储器控制装置，存储器控制装置包括控制电路（SDCON），该控制电路能够提供关于来自存储器装置的数据传输可以开始到与访问请求有关的总线主机的时间的信息的通知。总线主机可以使得给出的时间信息成为关于是否向存储器件提供访问请求的判断因素。因此，每个总线主机可以避免产生无用的访问请求，并且可以顺利地执行要访问的主机的数据传送。

94. 发明授权

US07827377B2 Method for reading out sensor data 有权
标题翻译：读出传感器数据的方法
公开(公告)号：US07827377B2
公开(公告)日：2010-11-02
申请号：US11664379
申请日：2005-08-03
申请人： Christian Ohl , Andreas Fink , Maike Moldenhauer
发明人： Christian Ohl , Andreas Fink , Maike Moldenhauer
IPC分类号： G06F12/00
CPC分类号： G06F5/12 , B60R2021/01068 , G06F5/14 , G06F2205/061
摘要： A method is described for reading out sensor data from an intermediate memory written by at least one sensor to the intermediate memory at a data-transfer rate (Tpas). A sampling rate (Tsg) is selected in such a way as to avoid an overflow of the intermediate memory and all buffered sensor data is read into a control unit memory at the predetermined sampling rate (Tsg), the intermediate memory generating a message (RBE) if no new sensor data is present in the intermediate memory at the time of sampling.
摘要翻译：描述了一种用于以由数据传送速率（Tpas）从中间存储器读出由至少一个传感器写入的中间存储器的传感器数据的方法。选择采样率（Tsg）以避免中间存储器的溢出，并且所有缓冲的传感器数据以预定采样率（Tsg）被读入控制单元存储器，中间存储器产生消息（RBE ）如果在采样时没有新的传感器数据存在于中间存储器中。

95. 发明申请

US20100077113A1 DATA COMMUNICATION SYSTEM AND METHOD 审中-公开
标题翻译：数据通信系统及方法
公开(公告)号：US20100077113A1
公开(公告)日：2010-03-25
申请号：US12262516
申请日：2008-10-31
申请人： Soon Jin CHOI , Seung Han Ko , Bo II Seo , Koon Shik Cho
发明人： Soon Jin CHOI , Seung Han Ko , Bo II Seo , Koon Shik Cho
IPC分类号： G06F3/00
CPC分类号： G06F5/12 , G06F2205/126
摘要： Provided is a data communication system including a first-in first-out (FIFO) buffer having a fixed size; a central processing unit (CPU) that writes data stored in a memory into the FIFO buffer; a modem that reads the data written by the CPU from the FIFO buffer; and a modem controller that is connected to the FIFO buffer, the CPU, and the modem, respectively, and controls the CPU such that data having a larger volume than the size of the FIFO buffer can be processed.
摘要翻译：提供了一种包括具有固定大小的先进先出（FIFO）缓冲器的数据通信系统; 将存储在存储器中的数据写入FIFO缓冲器的中央处理单元（CPU）调制解调器，从FIFO缓冲器读取CPU写入的数据; 以及分别连接到FIFO缓冲器，CPU和调制解调器的调制解调器控制器，并且控制CPU，使得可以处理具有比FIFO缓冲器的大小更大的数据的数据。

96. 发明授权

US07668983B2 System for designing data structures 失效
标题翻译：用于设计数据结构的系统
公开(公告)号：US07668983B2
公开(公告)日：2010-02-23
申请号：US10692957
申请日：2003-10-24
申请人： Anand Pande
发明人： Anand Pande
IPC分类号： H03M1/22 , H03M7/14 , H03M7/04 , H03K21/00 , G06F17/00 , G06F3/00 , G06F9/26
CPC分类号： G06F5/10 , G06F5/12 , G06F2205/102 , G06F2205/126
摘要： Systems and methods for designing data structures are provided. In one embodiment, an asynchronous first-in-first-out (FIFO) data structure may include, for example, a FIFO memory having a depth d in which d is an integer and a code generator coupled to the FIFO memory. The code generator may provide, for example, a first code sequence of length 2d. The first code sequence may have a circular property and a Hamming length of one for any two consecutive codes of the first code sequence. The first code sequence may be generated from a second code sequence by removing one or more pairs of mirrored codes of the second code sequence.
摘要翻译：提供了设计数据结构的系统和方法。在一个实施例中，异步先入先出（FIFO）数据结构可以包括例如具有深度d的FIFO存储器，其中d是整数，以及耦合到FIFO存储器的代码产生器。代码生成器可以提供例如长度为2d的第一代码序列。对于第一代码序列的任何两个连续代码，第一代码序列可以具有圆形属性和汉明长度1。可以通过去除第二代码序列的一个或多个镜像代码对，从第二代码序列生成第一代码序列。

97. 发明授权

US07653764B2 Fault-tolerant computer and method of controlling data transmission 失效
标题翻译：容错计算机和数据传输控制方法
公开(公告)号：US07653764B2
公开(公告)日：2010-01-26
申请号：US11302176
申请日：2005-12-14
申请人： Fumitoshi Mizutani
发明人： Fumitoshi Mizutani
IPC分类号： G06F13/28 , G06F5/00 , G06F11/00
CPC分类号： G06F11/1645 , G06F5/12 , G06F11/1679 , G06F2205/126
摘要： A fault-tolerant computer is capable of performing a data flow control process in a short period of time. The fault-tolerant computer includes a pair of duplicate systems each having a CPU subsystem and an IO subsystem. The IO subsystems of the duplicate systems are connected to each other through a cross link. The CPU system has an inbound reception buffer which receives data sent from the IO subsystem, and when the amount of the received data reaches a first threshold value, sends a first signal to the IO subsystem, and when the amount of the received data reaches a second threshold value greater than the first threshold value, sends a second signal to the IO subsystem. The IO subsystem has an IO I/F controller to stop sending data to the CPU subsystem when the IO I/F controller receives the first signal and the second signal, and a flow controller to send the second signal to the IO I/F controller of the paired IO subsystem through the cross link after the flow controller receives the second signal.
摘要翻译：容错计算机能够在短时间内执行数据流控制过程。容错计算机包括一对重复的系统，每个系统具有CPU子系统和IO子系统。重复系统的IO子系统通过交叉链接彼此连接。 CPU系统具有接收从IO子系统发送的数据的入站接收缓冲器，当接收到的数据量达到第一阈值时，向IO子系统发送第一信号，当接收到的数据量达到第二阈值大于第一阈值，向IO子系统发送第二信号。 IO子系统具有IO I / F控制器，当IO I / F控制器接收到第一信号和第二信号时，停止向CPU子系统发送数据，以及流量控制器将第二信号发送到IO I / F控制器在流量控制器接收到第二信号之后通过交叉连接的成对的IO子系统。

98. 发明授权

US07636834B2 Method and apparatus for resetting a gray code counter 失效
标题翻译：用于复位灰色代码计数器的方法和装置
公开(公告)号：US07636834B2
公开(公告)日：2009-12-22
申请号：US10302489
申请日：2002-11-21
申请人： Chengfuh Jeffrey Tang , Jiann-Tsuen Chen
发明人： Chengfuh Jeffrey Tang , Jiann-Tsuen Chen
IPC分类号： G06F13/00 , G11C7/10 , G06F5/00
CPC分类号： G06F5/10 , G06F5/12 , G06F5/14 , G06F13/1673 , G06F2205/102
摘要： Aspects of the invention may include gradually decrementing or incrementing a write pointer (370) associated with a data buffer such as the FIFO buffer (310) until a reset value of the write pointer (370) is reached in response to an indication that a data buffer controlled by the gray code counter is empty. Additionally, a read pointer (380) associated with the data buffer (310) may be gradually incremented or decremented until a reset value of the read pointer (380) is reached in response to an indication that the data buffer controlled by the gray code counter is full. The data buffer may be a first-in-first-out (FIFO) buffer such as FIFO buffer 310, which may be asynchronously clocked. The data buffer may be adapted to buffer any one or a combination of video, voice and data.
摘要翻译：本发明的各方面可以包括逐渐递减或增加与诸如FIFO缓冲器（310）的数据缓冲器相关联的写指针（370），直到达到写指针（370）的复位值，以响应于指示数据由灰色代码计数器控制的缓冲区为空。此外，与数据缓冲器（310）相关联的读指针（380）可以逐渐递增或递减，直到响应于由灰码计数器控制的数据缓冲器的指示达到读指针（380）的复位值已满。数据缓冲器可以是先入先出（FIFO）缓冲器，例如可以异步计时的FIFO缓冲器310。数据缓冲器可以适于缓冲视频，语音和数据的任何一种或组合。

99. 发明申请

US20090300234A1 BUFFER CONTROL METHOD AND STORAGE APPARATUS 审中-公开
标题翻译：缓冲控制方法和存储设备
公开(公告)号：US20090300234A1
公开(公告)日：2009-12-03
申请号：US12388340
申请日：2009-02-18
申请人： Tatsuya Haga
发明人： Tatsuya Haga
IPC分类号： G06F13/00
CPC分类号： G06F3/0656 , G06F3/0613 , G06F3/0676 , G06F5/12 , G06F2205/063
摘要： A buffer control method stores data to be written on a recording medium or data read from the recording medium to consecutive addresses within a storage region of a buffer, based on a sequential access command which instructs a continuous access to consecutive logical addresses of the recording medium, and variably sets a size of the storage region of the buffer depending on an unused region or a used region in the storage region of the buffer. The buffer is used as a buffer ring.
摘要翻译：缓冲器控制方法基于指示连续访问记录介质的连续逻辑地址的顺序访问命令，将要写入记录介质的数据或从记录介质读取的数据存储在缓冲器的存储区域内的连续地址并且根据缓冲器的存储区域中的未使用区域或使用区域可变地设置缓冲器的存储区域的大小。缓冲区用作缓冲环。

100. 发明申请

US20090216940A1 Method for accessing a first-in-first-out (FIFO) buffer and a FIFO controller therefor 有权
标题翻译：用于访问先进先出（FIFO）缓冲器和FIFO控制器的方法
公开(公告)号：US20090216940A1
公开(公告)日：2009-08-27
申请号：US12071828
申请日：2008-02-27
申请人： Mu-Hsien HSU , Tzung-Ren Wang
发明人： Mu-Hsien HSU , Tzung-Ren Wang
IPC分类号： G06F12/00
CPC分类号： G06F5/12 , G06F2205/126
摘要： A method of for accessing a first-in-first-out (FIFO) buffer is provided. The method comprises the following two steps. Firstly, issue a request to access a memory when the amount of the data buffered in the FIFO buffer is more than a threshold. Second, pop the data buffered in the FIFO buffer out to access the memory when the request is granted. If the FIFO buffer is a single-port FIFO buffer, the threshold is set based on the burst length of one burst of data. If the FIFO buffer is a dual-port FIFO buffer, the threshold is set based on the speed at which the data is pushed into the FIFO buffer and the speed at which the data is popped out of the FIFO buffer.
摘要翻译：提供了一种用于访问先进先出（FIFO）缓冲器的方法。该方法包括以下两个步骤。首先，当缓冲在FIFO缓冲器中的数据量大于阈值时，发出访问存储器的请求。其次，弹出FIFO缓冲区中缓存的数据，以便在请求被授权时访问内存。如果FIFO缓冲器是单端口FIFO缓冲器，则基于一个突发数据的突发长度来设置该阈值。如果FIFO缓冲器是双端口FIFO缓冲器，则基于将数据推入FIFO缓冲器的速度和数据从FIFO缓冲器中弹出的速度来设置阈值。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式