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91. 发明申请

US20150039979A1 METHOD AND APPARATUS FOR CONCEALING ERROR IN COMMUNICATION SYSTEM 有权
标题翻译：用于通信系统中的误差的方法和装置
公开(公告)号：US20150039979A1
公开(公告)日：2015-02-05
申请号：US14445619
申请日：2014-07-29
申请人： Samsung Electronics Co., Ltd.
发明人： Seungwon CHOI , Seongwook SONG
IPC分类号： G06F11/07 , H04B17/00
CPC分类号： G06F11/0763 , G10L19/005
摘要： A method and an apparatus for concealing an error of an apparatus for receiving an audio frame in a communication system are provided. The includes determining whether the error occurs in a current audio frame that is received from a transmitter, determining whether the audio frame includes a signal that corresponds to a preset specific frequency when the error occurs, setting a gain of the signal that corresponds to the specific frequency to be lower than a preset limit value if the audio frame includes the signal, and concealing the error of the current audio frame based on a previous audio frame of the audio frame in which the error occurs and the gain of the signal that corresponds to the set specific frequency.
摘要翻译：提供了一种用于在通信系统中隐藏用于接收音频帧的装置的错误的方法和装置。包括确定在从发送器接收的当前音频帧中是否发生错误，确定音频帧是否包括当出现错误时与预设的特定频率相对应的信号，设置与特定频率对应的信号的增益频率低于预设极限值，如果音频帧包括信号，并且基于发生错误的音频帧的先前音频帧和对应于该信号的信号的增益隐藏当前音频帧的误差设定具体频率。

92. 发明授权

US08930753B2 System, method and apparatus for error correction in multi-processor systems 有权
标题翻译：用于多处理器系统中纠错的系统，方法和装置
公开(公告)号：US08930753B2
公开(公告)日：2015-01-06
申请号：US13284647
申请日：2011-10-28
申请人： Robert Hillman , Gale Williamson
发明人： Robert Hillman , Gale Williamson
IPC分类号： G06F11/00 , G06F11/07 , G06F11/16 , G06F11/18
CPC分类号： G06F11/073 , G06F11/0724 , G06F11/0763 , G06F11/1658 , G06F11/184 , G06F2201/83
摘要： This disclosure provides apparatus, methods and systems for error correction in multi processor systems. Some implementations include a plurality of computing modules, each computing module including a processor. Each processor may include processing state. In some other implementations, each computing module may also include a memory. Upon receiving a signal to perform a partial re-synchronization, a hash of each processor's state data may be performed. In some embodiments, a hash of at least a portion of each computing module's memory data may also be performed. The hashes for each processor are then compared to determine majority hashes and possible minority hashes. Upon identifying a minority hash, the computing module that produced the minority hash may receive new processing state data from one of the computing modules that produced a majority hash.
摘要翻译：本公开提供了用于多处理器系统中的纠错的装置，方法和系统。一些实施方式包括多个计算模块，每个计算模块包括处理器。每个处理器可以包括处理状态。在一些其他实现中，每个计算模块还可以包括存储器。在接收到执行部分重新同步的信号时，可以执行每个处理器的状态数据的散列。在一些实施例中，还可以执行每个计算模块的存储器数据的至少一部分的散列。然后对每个处理器的散列进行比较，以确定大多数散列和可能的少数散列。在识别少数散列时，产生少数散列的计算模块可以从产生多数散列的计算模块之一接收新的处理状态数据。

93. 发明授权

US08869004B2 Memory storage device, memory controller thereof, and data transmission method thereof 有权
标题翻译：存储器存储装置，其存储器控制器及其数据发送方法
公开(公告)号：US08869004B2
公开(公告)日：2014-10-21
申请号：US13342204
申请日：2012-01-03
申请人： Shen-Yi Chao
发明人： Shen-Yi Chao
IPC分类号： G11C29/00
CPC分类号： G06F11/0745 , G06F11/0763 , G06F13/1684
摘要： A memory storage device, a memory controller thereof and a data transmission method thereof are provided. The memory storage device includes a rewritable non-volatile memory module having a first and a second memory dies, and the first and the second memory dies are coupled to the memory controller through the same data input/output bus. The method includes transmitting a read command to the first memory die and then transmitting a write command to the second memory die by the memory controller. The method further includes controlling the first and the second memory dies to respectively read out and put data onto the data input/output bus in accordance with the read command and write the data from the data input/output bus into the second memory die in accordance with the write command at the same time by the memory controller.
摘要翻译：提供了一种存储器存储装置，其存储器控制器及其数据传输方法。存储器存储设备包括具有第一和第二存储器管芯的可重写非易失性存储器模块，并且第一和第二存储器管芯通过相同的数据输入/输出总线耦合到存储器控制器。该方法包括将读取命令发送到第一存储器管芯，然后由存储器控制器向第二存储器管芯发送写入命令。该方法还包括根据读取命令控制第一和第二存储器模块分别读出数据并将其放入数据输入/输出总线，并根据读取命令将数据从数据输入/输出总线写入第二存储器管芯与内存控制器同时写入命令。

94. 发明申请

US20140310816A1 Method to Prevent Operating System Digital Product Key Activation Failures 有权
标题翻译：防止操作系统数字产品密钥激活失败的方法
公开(公告)号：US20140310816A1
公开(公告)日：2014-10-16
申请号：US13859871
申请日：2013-04-10
申请人： DELL PRODUCTS L.P.
发明人： Thomas Vrhel , Benjamin Brian Harry
IPC分类号： G06F21/12
CPC分类号： G06F21/121 , G06F8/70 , G06F11/004 , G06F11/07 , G06F11/0763 , G06F21/10 , G06F21/50
摘要： A method, an information handling system (IHS), and a computer program product initiates injection verification to determine whether a key injection procedure to support automated system activation within a target IHS was completed successfully. An injection verification module (IVM) compares a copy of a selected and limited character sequence for a unique digital product key (DPK) utilized during key injection to a character sequence reported by an operating system (OS) image on a selected, target IHS. If the selected character sequence matches the reported character sequence, the IVM identifies the selected information handling system as a “passing” system on which the key injection procedure was successfully performed. If the selected character sequence for the unique DPK does not match the reported character sequence, the IVM identifies the selected information handling system as a “failing” system on which the key injection procedure was not successfully performed.
摘要翻译：方法，信息处理系统（IHS）和计算机程序产品启动注射验证以确定是否成功完成了在目标IHS内支持自动化系统激活的密钥注入过程。注入验证模块（IVM）将用于在密钥注入期间使用的唯一数字产品密钥（DPK）的所选择和限制字符序列的副本与由所选择的目标IHS上的操作系统（OS）映像报告的字符序列进行比较。如果所选字符序列与报告的字符序列相匹配，则IVM将所选择的信息处理系统识别为成功执行密钥注入过程的“传递”系统。如果唯一DPK的所选字符序列与报告的字符序列不匹配，则IVM将所选择的信息处理系统标识为未成功执行密钥注入过程的“故障”系统。

95. 发明授权

US08799727B2 Arithmetic processing apparatus and method of controlling arithmetic processing apparatus 有权
标题翻译：算术处理装置和控制运算处理装置的方法
公开(公告)号：US08799727B2
公开(公告)日：2014-08-05
申请号：US13736238
申请日：2013-01-08
申请人： Fujitsu Limited
发明人： Noriko Takagi
IPC分类号： G11C29/00 , G06F13/00 , G06F11/10
CPC分类号： G06F11/1064 , G06F11/073 , G06F11/076 , G06F11/0763 , G06F11/0772
摘要： An arithmetic processing apparatus includes a cache memory to store data in cache lines, an error detecting unit to detect an error occurring in one of the cache lines, a way comparing unit to compare way identification information of a cache line to be accessed with error-way identification information, a word comparing unit to compare a word address of the cache line to be accessed with an error word address, a column comparing unit to compare a column address of the cache line to be accessed with an error column address, and a control unit to disable all cache lines sharing a failed word line in response to results of comparisons made by the way comparing unit, the word comparing unit, and the column comparing unit when the error detecting unit detects a second error occurring in any one of the cache lines after the occurrence of the first error.
摘要翻译：一种算术处理装置，包括：高速缓存存储器，用于将数据存储在高速缓存行中;检错单元，用于检测在一条高速缓存行中发生的错误;比较单元，用于将要访问的高速缓存行的识别信息与错误检测单元进行比较; 单词识别信息，字比较单元，用于将要访问的高速缓存行的字地址与错误字地址进行比较;列比较单元，用于将要访问的高速缓存行的列地址与错误列地址进行比较;以及控制单元，用于响应于比较单元，单词比较单元和列比较单元在比较单元检测到第二个错误时发生的第二个错误的比较结果来禁用所有共享失败字线的高速缓存行缓存行发生后第一个错误。

96. 发明申请

US20140189444A1 METHOD OF DETECTING AN ERROR OF A MULTI-TIME PROGRAMMABLE OPERATION, AND ORGANIC LIGHT EMITTING DISPLAY DEVICE EMPLOYING THE SAME 有权
标题翻译：检测多次可编程操作的错误的方法和使用其的有机发光显示装置
公开(公告)号：US20140189444A1
公开(公告)日：2014-07-03
申请号：US13955091
申请日：2013-07-31
申请人： Samsung Display Co., Ltd
发明人： Myoung-Ho KWON , Chang-Jin LEE , Chang-Kil LEE , Tae-Sik KIM
IPC分类号： G06F11/07
CPC分类号： G06F11/0763 , G06F11/0736 , G09G3/006 , G09G3/3208 , G09G5/06 , G09G2320/0276 , G09G2330/12
摘要： A method of detecting an error of a multi-time programmable (MTP) operation in which each gamma-offset and each header-bit at predetermined reference gray-levels are written in a MTP memory device while the MTP operation is performed on a pixel circuit, the each header-bit indicating whether or not the each gamma-offset is written in the MTP memory device, and it is detected whether or not the MTP operation is performed on the pixel circuit based on a logical operation between the header-bits at the predetermined reference gray-levels read from the MTP memory device when the MTP operation is finished on the pixel circuit.
摘要翻译：一种检测多时间可编程（MTP）操作的错误的方法，其中在对像素电路执行MTP操作的同时，在MTP存储器件中写入每个伽玛偏移和预定参考灰度级的每个标题位每个标题位指示每个伽玛偏移是否被写入MTP存储器件中，并且检测是否基于像素电路上的标题位之间的逻辑运算来执行MTP操作当MTP操作在像素电路上完成时，从MTP存储器件读取的预定参考灰度级。

97. 发明申请

US20140173357A1 SALVAGING EVENT TRACE INFORMATION IN POWER LOSS INTERRUPTION SCENARIOS 有权
标题翻译：电力损失中断场景中的抢救事件跟踪信息
公开(公告)号：US20140173357A1
公开(公告)日：2014-06-19
申请号：US13719209
申请日：2012-12-18
申请人： HGST NETHERLANDS B.V.
发明人： MICHAEL ANDERSON , KRAIG BOTTEMILLER , ADAM ESPESETH , LEE SENDELBACH
IPC分类号： G06F11/07
CPC分类号： G06F11/0778 , G06F11/0727 , G06F11/0763 , G06F11/1008 , G06F11/14 , G06F11/1438 , G06F11/1441
摘要： Salvaging event trace information in power loss interruption (PLI) scenarios, for use in solid-state drive (SSD) and hard disk drive (HDD) storage devices. If volatile state information that is salvaged after an inadvertent power loss were to include event trace information, then such information can provide a valuable debug resource. Event trace information from volatile memory is copied to a second memory upon a power on which is in response to a PLI event. A corrupt state of context reconstruction data stored on non-volatile memory is detected, and an indication of the corrupt state is set. The event trace information is passed to the host if requested based on the indication.
摘要翻译：断电事件跟踪信息在电力损失中断（PLI）情况下，用于固态硬盘（SSD）和硬盘驱动器（HDD）存储设备。如果在无意的功率损耗之后被抢救的易失性状态信息包括事件跟踪信息，则这样的信息可以提供有价值的调试资源。来自易失性存储器的事件跟踪信息在响应于PLI事件的上电时被复制到第二存储器。检测存储在非易失性存储器上的上下文重构数据的破坏状态，并设置损坏状态的指示。事件跟踪信息根据指示被传送到主机。

98. 发明申请

US20140157074A1 Systems and Methods for Selective Retry Data Retention Processing 有权
标题翻译：选择性重试数据保留处理的系统和方法
公开(公告)号：US20140157074A1
公开(公告)日：2014-06-05
申请号：US13692908
申请日：2012-12-03
申请人： LSI Corporation
发明人： Fan Zhang , Kaitlyn T. Nguyen , Jun Xiao
IPC分类号： G06F11/00
CPC分类号： G06F11/0763 , G06F11/0727 , G06F11/1443 , G11B20/10527 , G11B20/18 , H03M13/1111 , H03M13/1191 , H03M13/2957 , H03M13/3723 , H03M13/3738 , H03M13/3746 , H03M13/3753 , H03M13/6325 , H03M13/6343
摘要： Systems, circuits, devices and/or methods related to systems and methods for data processing, and more particularly to systems and methods for re-processing data sets not successfully processed during standard processing.
摘要翻译：与用于数据处理的系统和方法相关的系统，电路，设备和/或方法，更具体地涉及用于重新处理在标准处理期间未成功处理的数据集的系统和方法。

99. 发明授权

US08656208B2 Communication system with automatic restoring function against faulty operation and restoring method thereof 有权
标题翻译：具有故障运行自动恢复功能的通信系统及其恢复方法
公开(公告)号：US08656208B2
公开(公告)日：2014-02-18
申请号：US12937617
申请日：2009-03-05
申请人： Jae-Surk Hong , Chul-Yong Joung
发明人： Jae-Surk Hong , Chul-Yong Joung
IPC分类号： G06F11/00
CPC分类号： G06F11/0745 , G06F11/0763
摘要： Provided are a communication system and a method of restoring the communication system. The communication system includes a master device for transmitting a reference clock through a clock line, transmitting and receiving data through a data line, and requesting and receiving input data and error detection data, and a slave device for detecting human touch input data, transmitting and receiving the data in synchronization with the reference clock or generating and transmitting the input data, and transmitting the error detection data in response to the request for error detection data. Here, the master device compares stored error detection data with the received error detection data and initializes the slave device when the stored error detection data is not the same as the received error detection data. Therefore, in the master-slave communication system capable of automatic restoration from a malfunction and the method of restoring the communication system, a master device recognizes malfunction of a slave device having a volatile storage due to its surroundings, initializes the slave device, and thus can restore the slave device to its normal operating state.
摘要翻译：提供一种恢复通信系统的通信系统和方法。通信系统包括主装置，用于通过时钟线发送参考时钟，通过数据线发送和接收数据，以及请求和接收输入数据和错误检测数据;以及用于检测人触摸输入数据的从装置，与参考时钟同步地接收数据或产生和发送输入数据，以及响应于错误检测数据的请求发送错误检测数据。这里，主设备将存储的错误检测数据与接收到的错误检测数据进行比较，并且当存储的错误检测数据与接收到的错误检测数据不同时，初始化从设备。因此，在能够从故障自动恢复的主从通信系统和恢复通信系统的方法中，主设备识别由于周围具有易失性存储器的从设备的故障，初始化从设备，因此可以将从设备恢复到正常工作状态。

100. 发明申请

US20140033225A1 METHOD FOR MONITORING THE COORDINATED EXECUTION OF SEQUENCED TASKS BY AN ELECTRONIC CARD COMPRISING AT LEAST TWO PROCESSORS SYNCHRONIZED TO TWO DIFFERENT CLOCKS 有权
标题翻译：通过包含两个同步到两个不同时钟的两个处理器的电子卡监视序列化任务的协调执行的方法
公开(公告)号：US20140033225A1
公开(公告)日：2014-01-30
申请号：US13949868
申请日：2013-07-24
申请人： Airbus Operations SAS
发明人： Gilles Tost , David Roblero Martinez , Thierry Dejean , Sophie Deneuville , Laurent Marliere , Hélène Blouin
IPC分类号： G06F9/52
CPC分类号： G06F9/52 , G06F1/12 , G06F11/0715 , G06F11/0724 , G06F11/0739 , G06F11/0763 , H04W56/00
摘要： A method for monitoring the coordinated execution of sequenced tasks by an electronic device including a main electronic card including at least one main processor synchronized to a main clock and at least one auxiliary electronic card including at least one auxiliary processor synchronized to an auxiliary clock, includes emitting by the main processor of a coordination marker to the auxiliary processor at the start of each main time period; emitting by the auxiliary processor of a response word formed on the basis of the last coordination marker received to the main processor at the end of each auxiliary time period; validating by the main processor of the response word received with respect to the first coordination marker emitted; and signaling by the main processor if the response word received is not valid so as to signal a defect of coordination of the auxiliary processor.
摘要翻译：一种用于监视由包括与主时钟同步的至少一个主处理器的主电子卡和包括与辅助时钟同步的至少一个辅助处理器的至少一个辅助电子卡的主电子卡的电子设备的协调执行的排序任务的方法，每个主时间段开始时由主处理器将协调标记发射到辅助处理器; 由辅助处理器根据在每个辅助时间段结束时接收到主处理器的最后协调标记形成的响应字发出; 由主处理器验证相对于发射的第一协调标记接收的响应字; 如果接收到的响应字无效，则由主处理器发信号通知辅助处理器的协调缺陷。

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