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91. 发明申请

US20030149913A1 Method and apparatus for efficient burn-in of electronic circuits 审中-公开
标题翻译：电子电路有效老化的方法和装置
公开(公告)号：US20030149913A1
公开(公告)日：2003-08-07
申请号：US10330502
申请日：2002-12-27
发明人： Hari Balachandran , Scott Shaw , Jayashree Saxena
IPC分类号： H02H003/05
CPC分类号： G01R31/318577 , G01R31/2856 , G06F2201/83
摘要： A method and apparatus to efficiently burn-in electronic circuits (30), where the electronic circuits (30) comprise at least one set of scan chains (18). The method of the invention comprises the steps of: coupling a scan-in channel to the input of each scan chain (18); coupling in parallel each output of each scan chain (18) to form a single compressed scan-out channel for each set of scan chains (18); applying a test data signal to each scan-in channel; and monitoring each signal from each compressed scan-out channel.
摘要翻译：一种有效地插入电子电路（30）的方法和装置，其中电子电路（30）包括至少一组扫描链（18）。本发明的方法包括以下步骤：将扫描通道耦合到每个扫描链（18）的输入端; 并联每个扫描链（18）的每个输出，以形成每组扫描链（18）的单个压缩扫描输出通道; 将测试数据信号应用于每个扫入通道; 并监测来自每个压缩扫描输出通道的每个信号。

92. 发明申请

US20020153914A1 AC testing of leakage current 失效
标题翻译：交流测试漏电流
公开(公告)号：US20020153914A1
公开(公告)日：2002-10-24
申请号：US09838730
申请日：2001-04-19
申请人： Intel Corporation
发明人： Tawfik R. Arabi , Gregory F. Taylor , Srirama Pedarla , Patrick Elwer , Dan Murray
IPC分类号： G01R031/26
CPC分类号： G01R31/3008 , G01R31/3004 , G01R31/3012 , G01R31/318577
摘要： A method of leakage test for an integrated circuit by sampling the RC time constant of leakage current of the pins of the integrated circuit.
摘要翻译：通过对集成电路引脚的漏电流的RC时间常数进行采样，对集成电路进行漏电检测的方法。

93. 发明授权

US06445235B1 Iddq-testable uni-directional master-slave 失效
标题翻译： Iddq可测试的单向主从
公开(公告)号：US06445235B1
公开(公告)日：2002-09-03
申请号：US08498549
申请日：1995-07-05
申请人： Manoj Sachdev
发明人： Manoj Sachdev
IPC分类号： H03K3356
CPC分类号： G06F11/2236 , G01R31/3004 , G01R31/3008 , G01R31/318541 , G01R31/318577
摘要： A flipflop has master and slave interconnected through a buffer. The master has its inverters located outside the signal path from input to output, as the buffer provides the driving capability required for both IDDQ-testing and operational use. This configuration enables IDDQ-testing without further circuitry added to the flipflop and reduces propagation delay in the signal path.
摘要翻译：触发器具有通过缓冲器互连的主机和从机。主器件的反相器位于从输入到输出的信号路径之外，因为缓冲器提供了IDDQ测试和操作使用所需的驱动能力。这种配置可以进行IDDQ测试，而不需要将额外的电路添加到触发器，并减少信号路径中的传播延迟。

94. 发明申请

US20020087929A1 Test circuit for logical integrated circuit and method for testing same 失效
标题翻译：逻辑集成电路测试电路及其测试方法
公开(公告)号：US20020087929A1
公开(公告)日：2002-07-04
申请号：US10026532
申请日：2001-12-27
发明人： Ryouichirou Nagamine , Yasuteru Makita
IPC分类号： G01R031/28 , G01R031/26
CPC分类号： G01R31/318577
摘要： A part of a scan path lying in the x th stage of a test circuit is formed by successively connecting the FF11x standing at the head of the xth stage to the FF1mx standing at the end of the same in series. The scan path connects the scan input SIN with the input terminal of the FF11n standing at the head of the n th stage, and successively connects the FFs arranged in the second to (nnull1) th stages in series, after restarting from the output terminal of the FF1mn standing at the end of then th stage. The output terminal of the FF1m(nnull1) standing at the end of the (nnull1) th stage is connected with the input terminal of the FF111 standing at the hed of the first stage, and, finally, the output terminal of the FF1m1 standing at the end of the first stage is connected with the scan output SOT.
摘要翻译：位于测试电路的第X级的扫描路径的一部分通过将站立在第x级的头部的FF11x连续地连接到站立在其末端的FF1mx来形成。扫描路径将扫描输入SIN与FF11n的输入端连接在第n级的头部，并且从输出重新开始后，依次连接布置在第二至第（n-1）级的FF 终点站在第二阶段结束时。站在第（n-1）级末端的FF1m（n-1）的输出端与位于第一级的总线的FF111的输入端相连，最后连接到第站在第一级结束时的FF1m1与扫描输出SOT相连。

95. 发明授权

US6000050A Method for minimizing ground bounce during DC parametric tests using boundary scan register 失效
标题翻译：在使用边界扫描寄存器的直流参数测试期间最小化地面反弹的方法
公开(公告)号：US6000050A
公开(公告)日：1999-12-07
申请号：US956872
申请日：1997-10-23
申请人： Michio Komoda , Timothy Neal Ayres , Amitava Majumdar
发明人： Michio Komoda , Timothy Neal Ayres , Amitava Majumdar
IPC分类号： G01R31/3185 , G01R31/28
CPC分类号： G01R31/318577
摘要： The method of controlling ground bounce during DC parametric tests disclosed herein is based on the formulation of tests that best achieve two broad goals. The first goal is to reduce the number of I/O pins that are switched simultaneously. In the formulation of the VIL and VIH tests this goal is implemented by preferably only switching one input at a time. The second goal is to simultaneously switch I/O pins that are distant from one another. In the formulation of the VOL and VOH tests this goal is implemented by partitioning the outputs into subsets and selecting preferably one and only one output at a time from each and every subset.
摘要翻译：本文公开的DC参数测试期间控制地面反弹的方法基于最佳实现两个广泛目标的测试的配方。第一个目标是减少同时切换的I / O引脚数。在VIL和VIH测试的配方中，这个目标最好只能一次切换一个输入。第二个目标是同时切换彼此远的I / O引脚。在制定VOL和VOH测试中，通过将输出划分为子集并且优选地从每个子集一次选择一个且仅一个输出来实现该目标。

96. 发明授权

US5757203A Multiple on-chip IDDQ monitors 失效
标题翻译：多个片上IDDQ显示器
公开(公告)号：US5757203A
公开(公告)日：1998-05-26
申请号：US732077
申请日：1996-10-16
申请人： Charles Allen Brown
发明人： Charles Allen Brown
IPC分类号： G01R31/30 , G01R31/3185 , G01R31/28
CPC分类号： G01R31/318577 , G01R31/3008 , G01R31/3004
摘要： In order to measure IDDQ in a large integrated circuit, multiple IDDQ monitors sampling the current drawn by selected portions of the circuit are placed on the integrated circuit chip. The output of each IDDQ monitor is combined and supplied to one output port when any of the IDDQ monitors detect current in excess of a predetermined threshold. The output of each IDDQ monitor is also stored in a memory for subsequent readout at a second output port for detection of particular portions drawing the excessive current.
摘要翻译：为了在大型集成电路中测量IDDQ，多个IDDQ监视器采样将电路的选定部分绘制的电流放置在集成电路芯片上。当任何IDDQ监视器检测到超过预定阈值的电流时，每个IDDQ监视器的输出被组合并提供给一个输出端口。每个IDDQ监视器的输出也存储在存储器中用于随后在第二输出端口读出以检测绘制过量电流的特定部分。

97. 发明授权

US5612962A Pin-scan-in type LSI logic circuit, pin-scan-in system driving circuit, and method of testing circuit-mounting substrates 失效
标题翻译：引脚扫描型LSI逻辑电路，引脚扫描系统驱动电路和测试电路安装基板的方法
公开(公告)号：US5612962A
公开(公告)日：1997-03-18
申请号：US70412
申请日：1993-06-04
申请人： Toshiro Sato , Kunitoshi Yamamoto , Hiroyuki Adachi
发明人： Toshiro Sato , Kunitoshi Yamamoto , Hiroyuki Adachi
IPC分类号： G01R31/317 , G01R31/3185 , G01R31/28
CPC分类号： G01R31/31855 , G01R31/317 , G01R31/318558 , G01R31/318577
摘要： A pin-scan-in system driving circuit drives a pin-scan-in circuit to test short-circuit of the wirings or breaking of the wirings in the circuit-mounting substrate, and this circuit is driven using a reduced number of gates. The pin-scan-in system driving circuit drives the pin-scan-in circuit provided in an LSI logic circuit, and the LSI logic circuit is provided with a pin-scan-in circuit selector which selects the pin-scan-in circuit and a selected condition-holding circuit which holds the condition selected by the pin-scan-in circuit selector.
摘要翻译： PCT No.PCT / JP92 / 01289。 371日期：1993年6月4日 102（e）日期1993年6月4日PCT提交于1992年10月5日PCT公布。公开号WO93 / 07502 日期：1993年04月15日引脚扫描系统驱动电路驱动引脚扫描电路以测试布线的短路或电路安装基板中的布线断线，并且该电路使用减少的门数。引脚扫描系统驱动电路驱动LSI逻辑电路中提供的引脚扫描电路，并且LSI逻辑电路设置有引脚扫描输入电路选择器，其选择引脚扫描输入电路和选择状态保持电路，其保持由引脚扫描电路选择器选择的状态。

98. 发明授权

US11644503B2 TSV testing using test circuits and grounding means 有权
公开(公告)号：US11644503B2
公开(公告)日：2023-05-09
申请号：US17848383
申请日：2022-06-23
申请人： TEXAS INSTRUMENTS INCORPORATED
发明人： Lee D. Whetsel , Baher S. Haroun
IPC分类号： G01R31/3177 , G01R31/26 , G01R31/3185 , G01R31/317
CPC分类号： G01R31/3177 , G01R31/26 , G01R31/31723 , G01R31/318505 , G01R31/318577
摘要： This disclosure describes a novel method and apparatus for testing TSVs within a semiconductor device. According to embodiments illustrated and described in the disclosure, a TSV may be tested by stimulating and measuring a response from a first end of a TSV while the second end of the TSV held at ground potential. Multiple TSVs within the semiconductor device may be tested in parallel to reduce the TSV testing time according to the disclosure.

99. 发明授权

US10060980B2 Two signal JTAG with TLM, scan domain and diagnostics domain 有权
公开(公告)号：US10060980B2
公开(公告)日：2018-08-28
申请号：US15863147
申请日：2018-01-05
申请人： TEXAS INSTRUMENTS INCORPORATED
发明人： Lee D. Whetsel
IPC分类号： G01R31/3177 , G01R31/317 , G01R31/3185 , G01R31/3187 , G01R31/28 , G06F1/32
CPC分类号： G01R31/3177 , G01R31/2884 , G01R31/31721 , G01R31/31723 , G01R31/31724 , G01R31/31727 , G01R31/318511 , G01R31/318533 , G01R31/318544 , G01R31/318555 , G01R31/318558 , G01R31/318563 , G01R31/318572 , G01R31/318575 , G01R31/318577 , G01R31/318583 , G01R31/3187 , G06F1/3234
摘要： Testing of die on wafer is achieved by; (1) providing a tester with the capability of externally communicating JTAG test signals using simultaneously bidirectional transceiver circuitry, (2) providing die on wafer with the capability of externally communicating JTAG test signals using simultaneously bidirectional transceiver circuity, and (3) providing a connectivity mechanism between the bidirectional transceiver circuitry's of the tester and a selected group or all of the die on wafer for communication of the JTAG signals.

100. 发明授权

US10006964B2 Chip performance monitoring system and method 有权
公开(公告)号：US10006964B2
公开(公告)日：2018-06-26
申请号：US15134781
申请日：2016-04-21
申请人： International Business Machines Corporation
发明人： Margaret R. Charlebois , Christopher D. Hanudel , Robert D. Herzl , David W. Milton , Clarence R. Ogilvie , Paul M. Schanely , Tad J. Wilder
IPC分类号： G01R31/28 , G01R31/3177 , G06F1/08 , G06F11/34 , G01R31/3185 , G01R31/317
CPC分类号： G01R31/3177 , G01R31/31727 , G01R31/318577 , G06F1/08 , G06F11/348
摘要： Disclosed are a chip performance monitoring system, method and a computer program product, wherein a performance monitor output signal is propagated through an adjacent scan chain to avoid signal degradation incident to across-chip transmission of high frequency signals. Since the clock signal frequency used to control signal propagation through the scan chain will typically be less than twice the performance monitor output signal frequency, frequency sub-sampling with aliasing occurs. To compensate, signal propagation through the scan chain can be controlled during different time periods using different clock signals having different clock signal frequencies and, during these different time periods, different data outputs can be captured at an output node of the scan chain. The data output frequencies of these different data outputs can be measured and the performance monitor output signal frequency can be determined based on the different data output frequencies given the different clock signal frequencies.

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