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    • 93. 发明授权
    • Device for generating clock signals for asymmetric comparison of phase errors
    • 用于产生不对称比较相位误差的时钟信号的装置
    • US08487676B2
    • 2013-07-16
    • US13503738
    • 2010-10-28
    • Eric ColinetDimitri GalaykoAnton Korniienko
    • Eric ColinetDimitri GalaykoAnton Korniienko
    • H03L7/06
    • H03L7/087H03L7/07H03L7/091H03L2207/50
    • A device for generating a clock signal, including a phase-locked loop including: a controlled oscillator to deliver a clock signal; plural phase comparators to compare a phase of the clock signal delivered by the controlled oscillator with plural clock signal phases applied at an input of the phase-locked loop; a mechanism for weighted summation of output signals of the plural phase comparators such that one or more of the weighting coefficients applied to one of the output signals has an absolute value that overrides the absolute values of the other weighting coefficients applied to the other output signals; and a mechanism filtering the weighted sum of the output signals of the plural phase comparators, to deliver at an output a control signal to the controlled oscillator.
    • 一种用于产生时钟信号的装置,包括锁相环,包括:控制振荡器,用于传送时钟信号; 多个相位比较器,用于将由受控振荡器发送的时钟信号的相位与施加在锁相环输入端的多个时钟信号相位进行比较; 用于对所述多个相位比较器的输出信号进行加权求和的机构,使得施加到所述输出信号之一的加权系数中的一个或多个具有覆盖施加到所述其它输出信号的其他加权系数的绝对值的绝对值; 以及滤除多个相位比较器的输出信号的加权和的机构,以将输出的控制信号传送到受控振荡器。