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91. 发明授权

US09461939B2 Processing concurrency in a network device 有权
标题翻译：处理网络设备中的并发性
公开(公告)号：US09461939B2
公开(公告)日：2016-10-04
申请号：US14517570
申请日：2014-10-17
申请人： Marvell Israel (M.I.S.L) Ltd.
发明人： Aron Wohlgemuth , Rami Zemach , Gil Levy
IPC分类号： H04L12/28 , H04L12/935 , H04L12/741 , H04L29/06 , G06F9/52 , G06F12/02
CPC分类号： H04L49/3063 , G06F9/524 , G06F12/023 , G06F2212/163 , H04L45/74 , H04L69/12 , H04L69/22
摘要： A processing unit of a packet processing node initiates a transaction with an accelerator engine to trigger the accelerator engine for performing a processing operation with respect to a packet, and triggers the accelerator engine to perform the processing operation. The processing unit attempts to retrieve a result of the first processing operation from a memory location to which a result is to be written. It is determined whether the result has been written to the memory location, and when it is determined that the result has not yet been written to the memory location, the processing unit is locked until at least a portion of the result is written to the memory location.
摘要翻译：分组处理节点的处理单元与加速器引擎进行交易，以触发加速器引擎执行关于分组的处理操作，并且触发加速器引擎执行处理操作。处理单元尝试从要写入结果的存储单元检索第一处理操作的结果。确定结果是否被写入存储器位置，并且当确定结果尚未被写入存储器位置时，处理单元被锁定，直到结果的至少一部分被写入存储器位置。

92. 发明授权

US09443733B2 Method and apparatus for authenticating a semiconductor die 有权
标题翻译：用于认证半导体管芯的方法和装置
公开(公告)号：US09443733B2
公开(公告)日：2016-09-13
申请号：US14528870
申请日：2014-10-30
申请人： Marvell World Trade Ltd.
发明人： Patrick A. McKinley , Walter Lee McNall , Robert W. Shreeve , Thomas Page Bruch , Neal C. Jaarsma
IPC分类号： H01L21/268 , H01L21/768 , H03K19/177 , G06F21/73 , H01L23/00 , H01L21/265
CPC分类号： H01L21/268 , G06F21/73 , H01L21/265 , H01L21/76892 , H01L23/544 , H01L23/576 , H01L2223/5444 , H01L2924/0002 , H03K19/17768 , H01L2924/00
摘要： The present disclosure describes apparatuses and techniques for device-based die authentication. In some aspects, an intensity of a particle beam is varied during semiconductor processing to provide a semiconductor die having devices of varied values. In other aspects, different areas of semiconductor dies are exposed during semiconductor processing to provide semiconductor dies with devices that vary in value from one die to the next. For each semiconductor die, a value generated based on the values of the die's respective devices can be associated with that die thereby enabling subsequent authentication of the semiconductor die.
摘要翻译：本公开描述了用于基于设备的管芯认证的设备和技术。在一些方面，粒子束的强度在半导体处理期间变化以提供具有不同值的器件的半导体管芯。在其他方面，半导体管芯的不同区域在半导体处理期间被暴露，以向半导体管芯提供从一个管芯到下一个管芯的价值变化的器件。对于每个半导体管芯，基于管芯的各个器件的值产生的值可以与该管芯相关联，从而能够进行半导体管芯的后续认证。

93. 发明授权

US09436629B2 Dynamic boot image streaming 有权
标题翻译：动态启动映像流
公开(公告)号：US09436629B2
公开(公告)日：2016-09-06
申请号：US13676701
申请日：2012-11-14
申请人： Marvell World Trade Ltd.
发明人： Vamsi Krishna Baratam , Tolga Nihat Aytek
IPC分类号： G06F9/00 , G06F15/177 , G06F13/28 , G06F9/44
CPC分类号： G06F13/28 , G06F3/0607 , G06F3/0659 , G06F3/0685 , G06F9/441 , G06F13/1694 , G06F2213/2802
摘要： The present disclosure describes apparatuses and techniques for dynamic boot image streaming. In some aspects a memory controller that is streaming multiple boot images from a first memory to a second memory is stalled, a descriptor for streaming one of the multiple boot images from the first memory to a non-contiguous memory location is generated while the memory controller is stalled, and the memory controller is resumed effective to cause the memory controller to stream, based on the descriptor generated while the memory controller is stalled, the second boot image to the non-contiguous memory location.
摘要翻译：本公开描述了用于动态引导图像流的装置和技术。在一些方面，将多个引导映像从第一存储器流传输到第二存储器的存储器控制器被停止，产生用于将多个引导映像之一从第一存储器流传输到非连续存储器位置的描述符，而存储器控制器并且存储器控制器恢复有效，以使存储器控制器基于在存储器控制器停止时产生的描述符流将第二启动映像传送到非连续存储器位置。

94. 发明申请

US20160253278A1 Dynamic Boot Image Streaming 审中-公开
公开(公告)号：US20160253278A1
公开(公告)日：2016-09-01
申请号：US15151016
申请日：2016-05-10
申请人： Marvell World Trade Ltd.
发明人： Vamsi Krishna Baratam , Tolga Nihat Aytek
IPC分类号： G06F13/28 , G06F13/16 , G06F3/06 , G06F9/44
CPC分类号： G06F13/28 , G06F3/0607 , G06F3/0659 , G06F3/0685 , G06F9/441 , G06F13/1694 , G06F2213/2802
摘要： The present disclosure describes apparatuses and techniques for dynamic boot image streaming. In some aspects a memory controller that is streaming multiple boot images from a first memory to a second memory is stalled, a descriptor for streaming one of the multiple boot images from the first memory to a non-contiguous memory location is generated while the memory controller is stalled, and the memory controller is resumed effective to cause the memory controller to stream, based on the descriptor generated while the memory controller is stalled, the second boot image to the non-contiguous memory location.

95. 发明授权

US09432154B2 Frequency domain duplication in a long-range wireless local area network 有权
公开(公告)号：US09432154B2
公开(公告)日：2016-08-30
申请号：US14834210
申请日：2015-08-24
申请人： Marvell World Trade Ltd.
发明人： Hongyuan Zhang , Yong Liu
IPC分类号： H04J11/00 , H04L5/00 , H04W72/04 , H04L27/26 , H04W84/12
CPC分类号： H04L5/001 , H04L5/0044 , H04L27/2602 , H04L27/2613 , H04L27/2621 , H04W72/04 , H04W72/048 , H04W84/12
摘要： A method for generating OFDM signals is implemented in a device operating according to a communication protocol. The protocol defines non-duplicate mode data units corresponding to single component channels of a BSS channel, and non-duplicate mode data units corresponding to sets of adjacent component channels. Non-duplicate mode data units corresponding to a set of component channels have more lower-edge and/or upper-edge guard tones than non-duplicate mode data units corresponding to single component channels. The method includes determining that a duplicate mode will be utilized for an OFDM transmission in the set of component channels and, in response, generating a duplicate mode data unit. The duplicate mode data unit has fewer lower-edge and/or upper-edge guard tones than a non-duplicate mode data unit corresponding to a set of component channels, and includes one duplicate of the non-duplicate mode data unit corresponding to the single component channel for each adjacent component channel.

96. 发明授权

US09431052B2 Two dimensional magnetic recording systems, devices and methods 有权
标题翻译：二维磁记录系统，装置和方法
公开(公告)号：US09431052B2
公开(公告)日：2016-08-30
申请号：US14749492
申请日：2015-06-24
申请人： Marvell World Trade Ltd.
发明人： Mats Oberg , Nitin Nangare
IPC分类号： G11B5/09 , G11B20/10 , G11B5/012 , G11B5/49 , G11B5/39
CPC分类号： G11B20/10046 , G11B5/012 , G11B5/02 , G11B5/3964 , G11B5/4976 , G11B20/10009 , G11B20/10037 , G11B20/18
摘要： The present disclosure describes systems and techniques relating to storage devices, such as storage devices that employ Two Dimensional Magnetic Recording (TDMR). According to an aspect of the described systems and techniques, a device includes: a first read channel to process a first input signal obtained from a Two Dimensional Magnetic Recording (TDMR) storage medium using a first read head, wherein the first read channel includes a first analog to digital converter (ADC); a second read channel to process a second input signal obtained from the TDMR, storage medium using a second read head, wherein the second read channel includes a second ADC; and a single digital timing loop (DTL) for both the first read channel and the second read channel, wherein the single DTL is configured to control interpolation of timing of sampling for the first and second ADCs.
摘要翻译：本公开描述了与存储设备相关的系统和技术，例如采用二维磁记录（TDMR）的存储设备。根据所描述的系统和技术的一个方面，一种设备包括：第一读取通道，用于使用第一读取头处理从二维磁记录（TDMR）存储介质获得的第一输入信号，其中第一读取通道包括第一个模数转换器（ADC）; 第二读取通道，用于处理从TDMR获得的第二输入信号，使用第二读取头的存储介质，其中所述第二读取通道包括第二ADC; 以及用于第一读取通道和第二读取通道的单个数字定时循环（DTL），其中单个DTL被配置为控制第一和第二ADC的采样定时的内插。

97. 发明授权

US09425721B2 Systems and methods for adaptive motor speed control 有权
标题翻译：自适应电机速度控制的系统和方法
公开(公告)号：US09425721B2
公开(公告)日：2016-08-23
申请号：US14338908
申请日：2014-07-23
申请人： Marvell World Trade LTD.
发明人： Ravishanker Krishnamoorthy , Edy Susanto , Cheng Yong Teoh , Foo Leng Leong
IPC分类号： H02P21/06 , H02P6/08 , H02P6/06
CPC分类号： H02P6/08 , H02P6/06 , H02P6/15 , H02P6/28
摘要： A system including memory to store a plurality of sets of values, where each set is used to control speed of a different type of motor. A pulse width modulation (PWM) module receives an input indicating a type of motor sensed in the system, selects a set corresponding to the type of the sensed motor, and generates, based on the selected set, a pulse width modulation signal to control speed of the sensed motor. A speed module receives a requested speed for the sensed motor and generates an output indicating a range of speed corresponding to the requested speed. The PWM module selects, based on the range of speed, a value from the selected set; shifts, based on the selected value, the pulse width modulation signal; and adjusts, based on the shifted pulse width modulation signal, the speed of the sensed motor by adjusting torque applied to the sensed motor.
摘要翻译：一种包括用于存储多组值的存储器的系统，其中每组用于控制不同类型的电动机的速度。脉冲宽度调制（PWM）模块接收指示在系统中感测到的电动机的类型的输入，选择与感测到的电动机的类型相对应的一组，并且基于所选择的组生成用于控制速度的脉宽调制信号的感应电动机。速度模块接收所感测的电动机的请求速度，并产生指示对应于所请求速度的速度范围的输出。 PWM模块根据速度范围选择来自所选组的值; 基于选择的值移位脉宽调制信号; 并且通过调整施加到感测到的电动机的转矩，基于移动的脉宽调制信号来调整感测电动机的速度。

98. 发明授权

US09423451B2 Method and apparatus for testing a semiconductor package having a package on package (PoP) design 有权
标题翻译：用于测试具有封装封装（PoP）设计的半导体封装的方法和装置
公开(公告)号：US09423451B2
公开(公告)日：2016-08-23
申请号：US14284241
申请日：2014-05-21
申请人： Marvell World Trade Ltd.
发明人： Yat Fai Leung
IPC分类号： G01R31/26 , G01R31/28 , H01L21/66
CPC分类号： G01R31/2889 , G01R31/2863 , G01R31/2896 , H01L22/14
摘要： Embodiments include a testing arrangement for testing a first package, the testing arrangement comprising a frame having a top section and a bottom section, wherein the bottom section of the frame comprises a pickup section, and wherein the pickup section has a first air pathway; a second package mounted on a top surface of the bottom section of the frame such that a second air pathway is defined between (i) the second package and (ii) the top surface of the bottom section of the frame; and a vacuum path defined by (i) the first air pathway and (ii) the second air pathway, wherein during testing of the first package, a vacuum in the vacuum path is generated such that the pickup section of the bottom section of the frame holds the first package.
摘要翻译：实施例包括用于测试第一包装件的测试装置，所述测试装置包括具有顶部部分和底部部分的框架，其中所述框架的底部部分包括拾取部分，并且其中所述拾取部分具有第一空气通路; 第二包装，其安装在所述框架的底部的顶部表面上，使得在（i）所述第二包装和（ii）所述框架的所述底部的所述顶部表面之间限定第二空气通道; 以及由（i）第一空气路径和（ii）第二空气路径限定的真空路径，其中在第一包装的测试期间，产生真空路径中的真空，使得框架的底部的拾取部分拥有第一个包装。

99. 发明授权

US09417641B2 Memory effect reduction using low impedance biasing 有权
标题翻译：使用低阻抗偏置降低记忆效应
公开(公告)号：US09417641B2
公开(公告)日：2016-08-16
申请号：US14532816
申请日：2014-11-04
申请人： Marvell World Trade, Ltd.
发明人： David M. Signoff , Ming He , Wayne A. Loeb
IPC分类号： G05F1/46 , H03H7/01 , H03F1/30 , H03F3/24 , H03F3/26
CPC分类号： H03F3/245 , G05F1/46 , H03F1/301 , H03F1/308 , H03F3/195 , H03F3/265 , H03F3/505 , H03F2200/24 , H03F2200/451 , H03F2200/453 , H03F2200/534 , H03F2200/555 , H03F2200/69 , H03H7/0107
摘要： A circuit includes a bias circuit for a biased transistor. The bias circuit includes a master-slave source follower circuit, a reference transistor, and a bias circuit voltage output coupled to the biased transistor and configured to provide a bias voltage. The reference transistor has a transconductance substantially identical to a transconductance of the biased transistor. A signal ground circuit may be coupled between the biased transistor and one or more components of the bias circuit that do not generate significant return currents to a power supply ground. A method includes generating a current in a reference transistor according to a first voltage generated using a master source follower circuit, generating a second voltage substantially identical to the first voltage using a slave source follower circuit, and providing the second voltage to a biased transistor. The reference transistor has a transconductance substantially identical to a transconductance of the biased transistor.
摘要翻译：电路包括用于偏置晶体管的偏置电路。偏置电路包括主从源极跟随器电路，参考晶体管和耦合到偏置晶体管并被配置为提供偏置电压的偏置电路电压输出。参考晶体管具有与偏置晶体管的跨导基本相同的跨导。信号接地电路可以耦合在偏置晶体管和偏置电路的一个或多个组件之间，其不产生对电源接地的大的返回电流。一种方法包括根据使用主源跟随器电路产生的第一电压在参考晶体管中产生电流，使用从源跟随器电路产生与第一电压基本相同的第二电压，以及将第二电压提供给偏置晶体管。参考晶体管具有与偏置晶体管的跨导基本相同的跨导。

100. 发明授权

US09414432B2 Physical layer frame format for WLAN 有权
标题翻译： WLAN的物理层帧格式
公开(公告)号：US09414432B2
公开(公告)日：2016-08-09
申请号：US14274475
申请日：2014-05-09
申请人： MARVELL WORLD TRADE LTD.
发明人： Hongyuan Zhang
IPC分类号： H04W80/04 , H04L1/00 , H03M13/29 , H03M13/09 , H04L27/18
CPC分类号： H04W80/045 , H03M13/09 , H03M13/2933 , H04L1/003 , H04L1/0041 , H04L1/0059 , H04L1/0061 , H04L1/0072 , H04L1/0079 , H04L27/18 , H04W84/12
摘要： A field of a preamble of the data unit is decoded using a tail biting technique, including decoding a received cyclic redundancy check (CRC) included in the field. A first CRC for the field is generated using a first CRC generation scheme, and a second CRC for the field is generated using a second CRC generation scheme. The first generated CRC and the second generated CRC are compared to the received CRC. It is determined that the data unit conforms to a first communication protocol when the first generated CRC matches the received CRC, and it is determined that the data unit conforms to a second communication protocol when the second generated CRC matches the received CRC.
摘要翻译：使用尾部咬合技术对数据单元的前置码的字段进行解码，包括对包括在该字段中的接收到的循环冗余校验（CRC）进行解码。使用第一CRC生成方案生成用于该字段的第一CRC，并且使用第二CRC生成方案生成用于该字段的第二CRC。将第一个生成的CRC和第二个生成的CRC与接收到的CRC进行比较。当第一个生成的CRC与接收的CRC匹配时，确定数据单元符合第一通信协议，并且当第二个生成的CRC与接收的CRC匹配时，确定数据单元符合第二通信协议。

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