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91. 发明授权

US07927963B2 Integrated circuit structure, design structure, and method having improved isolation and harmonics 有权
标题翻译：集成电路结构，设计结构和方法具有改进的隔离和谐波
公开(公告)号：US07927963B2
公开(公告)日：2011-04-19
申请号：US12187415
申请日：2008-08-07
申请人： Brennan J. Brown , James R. Elliott , Alvin J. Joseph , Edward J. Nowak
发明人： Brennan J. Brown , James R. Elliott , Alvin J. Joseph , Edward J. Nowak
IPC分类号： H01L21/76
CPC分类号： H01L21/76224 , H01L21/76283 , H01L21/764 , H01L27/12
摘要： Disclosed are embodiments of a semiconductor structure, a design structure for the semiconductor structure and a method of forming the semiconductor structure. The embodiments reduce harmonics and improve isolation between the active semiconductor layer and the substrate of a semiconductor-on-insulator (SOI) wafer. Specifically, the embodiments incorporate a trench isolation region extending to a fully or partially amorphized region of the wafer substrate. The trench isolation region is positioned outside lateral boundaries of at least one integrated circuit device located at or above the active semiconductor layer of the SOI wafer and, thereby improves isolation. The fully or partially amorphized region of the substrate reduces substrate mobility, which reduces the charge layer at the substrate/BOX interface and, thereby reduces harmonics. Optionally, the embodiments can incorporate an air gap between the wafer substrate and integrated circuit device(s) in order to further improve isolation.
摘要翻译：公开了半导体结构的实施例，半导体结构的设计结构和形成半导体结构的方法。这些实施例减少谐波并改善有源半导体层和绝缘体上半导体（SOI）晶片的衬底之间的隔离。具体地，实施例结合了延伸到晶片衬底的完全或部分非晶化区域的沟槽隔离区域。沟槽隔离区位于位于SOI晶片的有源半导体层之上或之上的至少一个集成电路器件的横向边界的外侧，从而提高了隔离度。衬底的完全或部分非晶化区域降低衬底迁移率，这降低了衬底/ BOX界面处的电荷层，从而减少了谐波。可选地，实施例可以在晶片衬底和集成电路器件之间并入气隙，以进一步改善隔离。

92. 发明授权

US07804151B2 Integrated circuit structure, design structure, and method having improved isolation and harmonics 有权
标题翻译：集成电路结构，设计结构和方法具有改进的隔离和谐波
公开(公告)号：US07804151B2
公开(公告)日：2010-09-28
申请号：US12187419
申请日：2008-08-07
申请人： Brennan J. Brown , James R. Elliott , Alvin J. Joseph , Edward J. Nowak
发明人： Brennan J. Brown , James R. Elliott , Alvin J. Joseph , Edward J. Nowak
IPC分类号： H01L23/58
CPC分类号： H01L23/66 , H01L21/76289 , H01L21/764 , H01L23/585 , H01L27/12 , H01L2924/0002 , H01L2924/00
摘要： Disclosed are embodiments of a semiconductor structure, a design structure for the semiconductor structure and a method of forming the semiconductor structure. The embodiments reduce harmonics and improve isolation between the active semiconductor layer and the substrate of a semiconductor-on-insulator (SOI) wafer. Specifically, the embodiments incorporate a trench isolation region extending to a fully or partially amorphized region of the wafer substrate. The trench isolation region is positioned outside lateral boundaries of at least one integrated circuit device located at or above the active semiconductor layer of the SOI wafer and, thereby improves isolation. The fully or partially amorphized region of the substrate reduces substrate mobility, which reduces the charge layer at the substrate/BOX interface and, thereby reduces harmonics. Optionally, the embodiments can incorporate an air gap between the wafer substrate and integrated circuit device(s) in order to further improve isolation.
摘要翻译：公开了半导体结构的实施例，半导体结构的设计结构和形成半导体结构的方法。这些实施例减少谐波并改善有源半导体层和绝缘体上半导体（SOI）晶片的衬底之间的隔离。具体地，实施例结合了延伸到晶片衬底的完全或部分非晶化区域的沟槽隔离区域。沟槽隔离区位于位于SOI晶片的有源半导体层之上或之上的至少一个集成电路器件的横向边界的外侧，从而提高了隔离度。衬底的完全或部分非晶化区域降低衬底迁移率，这降低了衬底/ BOX界面处的电荷层，从而减少了谐波。可选地，实施例可以在晶片衬底和集成电路器件之间并入气隙，以进一步改善隔离。

93. 发明申请

US20100230753A1 LATERAL HYPERABRUPT JUNCTION VARACTOR DIODE IN AN SOI SUBSTRATE 有权
标题翻译： SOI衬底中的横向高压连接变压器二极管
公开(公告)号：US20100230753A1
公开(公告)日：2010-09-16
申请号：US12550658
申请日：2009-08-31
申请人： Jeffrey B. Johnson , Alvin J. Joseph , Robert M. Rassel , Yun Shi
发明人： Jeffrey B. Johnson , Alvin J. Joseph , Robert M. Rassel , Yun Shi
IPC分类号： H01L29/786 , H01L21/336 , G06F17/50
CPC分类号： H01L29/93 , H01L29/7391
摘要： A varactor diode includes a portion of a top semiconductor layer of a semiconductor-on-insulator (SOI) substrate and a gate electrode located thereupon. A first electrode having a doping of a first conductivity type laterally abuts a doped semiconductor region having the first conductivity type, which laterally abuts a second electrode having a doping of a second conductivity type, which is the opposite of the first conductivity type. A hyperabrupt junction is formed between the second doped semiconductor region and the second electrode. The gate electrode controls the depletion of the first and second doped semiconductor regions, thereby varying the capacitance of the varactor diode. A design structure for the varactor diode is also provided.
摘要翻译：变容二极管包括绝缘体上半导体（SOI）衬底的顶部半导体层的一部分和位于其上的栅电极。具有第一导电类型的掺杂的第一电极横向邻接具有第一导电类型的掺杂半导体区域，其横向邻接具有与第一导电类型相反的第二导电类型的掺杂的第二电极。在第二掺杂半导体区域和第二电极之间形成超破坏结。栅电极控制第一和第二掺杂半导体区的耗尽，从而改变变容二极管的电容。还提供了变容二极管的设计结构。

94. 发明申请

US20100035403A1 Integrated Circuit Structure, Design Structure, and Method Having Improved Isolation and Harmonics 有权
标题翻译：集成电路结构，设计结构和改进隔离和谐波的方法
公开(公告)号：US20100035403A1
公开(公告)日：2010-02-11
申请号：US12187415
申请日：2008-08-07
申请人： Brennan J. Brown , James R. Elliott , Alvin J. Joseph , Edward J. Nowak
发明人： Brennan J. Brown , James R. Elliott , Alvin J. Joseph , Edward J. Nowak
IPC分类号： H01L21/762
CPC分类号： H01L21/76224 , H01L21/76283 , H01L21/764 , H01L27/12
摘要： Disclosed are embodiments of a semiconductor structure, a design structure for the semiconductor structure and a method of forming the semiconductor structure. The embodiments reduce harmonics and improve isolation between the active semiconductor layer and the substrate of a semiconductor-on-insulator (SOI) wafer. Specifically, the embodiments incorporate a trench isolation region extending to a fully or partially amorphized region of the wafer substrate. The trench isolation region is positioned outside lateral boundaries of at least one integrated circuit device located at or above the active semiconductor layer of the SOI wafer and, thereby improves isolation. The fully or partially amorphized region of the substrate reduces substrate mobility, which reduces the charge layer at the substrate/BOX interface and, thereby reduces harmonics. Optionally, the embodiments can incorporate an air gap between the wafer substrate and integrated circuit device(s) in order to further improve isolation.
摘要翻译：公开了半导体结构的实施例，半导体结构的设计结构和形成半导体结构的方法。这些实施例减少谐波并改善有源半导体层和绝缘体上半导体（SOI）晶片的衬底之间的隔离。具体地，实施例结合了延伸到晶片衬底的完全或部分非晶化区域的沟槽隔离区域。沟槽隔离区位于位于SOI晶片的有源半导体层之上或之上的至少一个集成电路器件的横向边界的外侧，从而提高了隔离度。衬底的完全或部分非晶化区域降低衬底迁移率，这降低了衬底/ BOX界面处的电荷层，从而减少了谐波。可选地，实施例可以在晶片衬底和集成电路器件之间并入气隙，以进一步改善隔离。

95. 发明申请

US20090250739A1 Device Structures with a Hyper-Abrupt P-N Junction, Methods of Forming a Hyper-Abrupt P-N Junction, and Design Structures for an Integrated Circuit 失效
标题翻译：具有超突发P-N结的器件结构，形成超突发P-N结的方法和集成电路的设计结构
公开(公告)号：US20090250739A1
公开(公告)日：2009-10-08
申请号：US12099316
申请日：2008-04-08
申请人： Jeffrey B. Johnson , Alvin J. Joseph , Robert M. Rassel , Yun Shi
发明人： Jeffrey B. Johnson , Alvin J. Joseph , Robert M. Rassel , Yun Shi
IPC分类号： H01L29/93 , H01L21/329
CPC分类号： H01L29/93
摘要： Device structures with hyper-abrupt p-n junctions, methods of forming hyper-abrupt p-n junctions, and design structures for an integrated circuit containing devices structures with hyper-abrupt p-n junctions. The hyper-abrupt p-n junction is defined in a SOI substrate by implanting a portion of a device layer to have one conductivity type and then implanting a portion of this doped region to have an opposite conductivity type. The counterdoping defines the hyper-abrupt p-n junction. A gate structure carried on a top surface of the device layer operates as a hard mask during the ion implantations to assist in defining a lateral boundary for the hyper-abrupt-n junction.
摘要翻译：具有超突变p-n结的器件结构，形成超突变p-n结的方法以及包含具有超突变p-n结的器件结构的集成电路的设计结构。通过将器件层的一部分注入具有一种导电类型，然后将该掺杂区域的一部分注入具有相反的导电型，在SOI衬底中限定超突变p-n结。反渗透定义了超突变p-n结。在离子注入期间，在器件层的顶表面上承载的栅极结构作为硬掩模进行操作，以有助于限定超突变n结的横向边界。

96. 发明申请

US20090146247A1 SEMICONDUCTOR GROUND SHIELD 有权
标题翻译：半导体接地屏蔽
公开(公告)号：US20090146247A1
公开(公告)日：2009-06-11
申请号：US12371662
申请日：2009-02-16
申请人： Mete Erturk , Alvin J. Joseph , Anthony K. Stamper
发明人： Mete Erturk , Alvin J. Joseph , Anthony K. Stamper
IPC分类号： H01L29/70
CPC分类号： H01L23/5225 , H01L2924/0002 , H01L2924/00
摘要： A ground shield is disclosed that includes a ‘cheesed’ metal positioned within a dielectric layer and a metal region positioned within a first metal level over the cheesed metal. The ground shield can have different forms depending on the metal used, and provisions are made to prevent diffusion of copper (Cu) when that is used as the metal in the cheese metal of the ground shield. The ground shield provides a low resistance, very thick metal at a first metal (M1) level for passive RF elements in conjunction with the standard back-end-of-line (BEOL) integration. The invention also includes a method of forming the ground shield.
摘要翻译：公开了一种接地屏蔽，其包括位于电介质层内的“干酪”金属和位于干酪金属上的第一金属层内的金属区域。接地屏蔽可以根据所使用的金属具有不同的形式，并且当用作接地屏蔽的奶酪金属中的金属时，设置防止铜（Cu）的扩散。接地屏蔽为第一金属（M1）级别提供低电阻，非常厚的金属，用于与标准后端（BEOL）集成结合的无源RF元件。本发明还包括形成接地屏蔽的方法。

97. 发明申请

US20090101887A1 SILICON GERMANIUM HETEROSTRUCTURE BARRIER VARACTOR 失效
标题翻译：硅锗锗结构障碍物
公开(公告)号：US20090101887A1
公开(公告)日：2009-04-23
申请号：US11876787
申请日：2007-10-23
申请人： Erik M. Dahlstrom , Alvin J. Joseph , Robert M. Rassel , David C. Sheridan
发明人： Erik M. Dahlstrom , Alvin J. Joseph , Robert M. Rassel , David C. Sheridan
IPC分类号： H01L29/12 , H01L21/329
CPC分类号： H01L29/93 , H01L29/155 , H01L29/165
摘要： Methods and heterostructure barrier varactor (HBV) diodes optimized for application with frequency multipliers at providing outputs at submillimeter wave frequencies and above. The HBV diodes include a silicon-containing substrate, an electrode over the silicon-containing substrate, and one or more heterojunction quantum wells of alternating layers of Si and SiGe of one or more electrodes of the diode. Each SiGe quantum well preferably has a floating SiGe layer between adjacent SiGe gradients followed by adjacent Si layers, such that, a single homogeneous structure is provided characterized by having no distinct separations. The plurality of Si/SiGe heterojunction quantum wells may be symmetric or asymmetric.
摘要翻译：优化的方法和异质结构屏障变容二极管（HBV）二极管，用于在亚毫米波频率及以上提供输出的频率乘法器。 HBV二极管包括含硅衬底，位于含硅衬底上的电极以及二极管的一个或多个电极的Si和SiGe的交替层的一个或多个异质结量子阱。每个SiGe量子阱优选地在相邻SiGe梯度之间具有相邻SiGe梯度之间的浮动SiGe层，随后是相邻的Si层，使得提供单一的均匀结构，其特征在于没有明显的分离。多个Si / SiGe异质结量子阱可以是对称的或不对称的。

98. 发明授权

US07501690B2 Semiconductor ground shield method 失效
标题翻译：半导体接地屏蔽法
公开(公告)号：US07501690B2
公开(公告)日：2009-03-10
申请号：US10908354
申请日：2005-05-09
申请人： Mete Erturk , Alvin J. Joseph , Anthony K. Stamper
发明人： Mete Erturk , Alvin J. Joseph , Anthony K. Stamper
IPC分类号： H01L29/70
CPC分类号： H01L23/5225 , H01L2924/0002 , H01L2924/00
摘要： A ground shield is disclosed that includes a ‘cheesed’ metal positioned within a dielectric layer and a metal region positioned within a first metal level over the cheesed metal. The ground shield can have different forms depending on the metal used, and provisions are made to prevent diffusion of copper (Cu) when that is used as the metal in the cheese metal of the ground shield. The ground shield provides a low sheet resistance, very thick metal at a first metal (M1) level for passive RF elements in conjunction with the standard back-end-of-line (BEOL) integration. The invention also includes a method of forming the ground shield.
摘要翻译：公开了一种接地屏蔽，其包括位于电介质层内的“干酪”金属和位于干酪金属上的第一金属层内的金属区域。接地屏蔽可以根据所使用的金属具有不同的形式，并且当用作接地屏蔽的奶酪金属中的金属时，设置防止铜（Cu）的扩散。接地屏蔽层为标准后端（BEOL）集成的无源RF元件提供了第一金属（M1）级别的低电阻，非常厚的金属。本发明还包括形成接地屏蔽的方法。

99. 发明授权

US07491985B2 Method of collector formation in BiCMOS technology 有权
标题翻译： BiCMOS技术中收集器形成的方法
公开(公告)号：US07491985B2
公开(公告)日：2009-02-17
申请号：US11288843
申请日：2005-11-29
申请人： Peter J. Geiss , Peter B. Gray , Alvin J. Joseph , Qizhi Liu
发明人： Peter J. Geiss , Peter B. Gray , Alvin J. Joseph , Qizhi Liu
IPC分类号： H01L31/072 , H01L31/109 , H01L31/0328 , H01L31/0336
CPC分类号： H01L29/0821 , H01L21/8249 , H01L27/0623 , H01L29/66242 , H01L29/66318
摘要： A heterobipolar transistor (HBT) for high-speed BiCMOS applications is provided in which the collector resistance, Rc, is lowered by providing a buried refractory metal silicide layer underneath the shallow trench isolation region on the subcollector of the device. Specifically, the HBT of the present invention includes a substrate including at least a subcollector; a buried refractory metal silicide layer located on the subcollector; and a shallow trench isolation region located on a surface of the buried refractory metal silicide layer. The present invention also provides a method of fabricating such a HBT. The method includes forming a buried refractory metal silicide underneath the shallow trench isolation region on the subcollector of the device.
摘要翻译：提供了用于高速BiCMOS应用的异步双极晶体管（HBT），其中通过在器件的子集电极上的浅沟槽隔离区域的下面提供掩埋难熔金属硅化物层来降低集电极电阻Rc。具体地，本发明的HBT包括至少包括子集电极的基板; 位于子集电极上的埋置难熔金属硅化物层; 以及位于掩埋难熔金属硅化物层的表面上的浅沟槽隔离区域。本发明还提供一种制造这种HBT的方法。该方法包括在器件的子集电极上的浅沟槽隔离区域的下面形成埋置难熔金属硅化物。

100. 发明授权

US07002190B1 Method of collector formation in BiCMOS technology 有权
公开(公告)号：US07002190B1
公开(公告)日：2006-02-21
申请号：US10711479
申请日：2004-09-21
申请人： Peter J. Geiss , Peter B. Gray , Alvin J. Joseph , Qizhi Liu
发明人： Peter J. Geiss , Peter B. Gray , Alvin J. Joseph , Qizhi Liu
IPC分类号： H01L31/072 , H01L31/109 , H01L31/0328 , H01L31/0336
CPC分类号： H01L29/0821 , H01L21/8249 , H01L27/0623 , H01L29/66242 , H01L29/66318
摘要： A heterobipolar transistor (HBT) for high-speed BiCMOS applications is provided in which the collector resistance, Rc, is lowered by providing a buried refractory metal silicide layer underneath the shallow trench isolation region on the subcollector of the device. Specifically, the HBT of the present invention includes a substrate including at least a subcollector; a buried refractory metal silicide layer located on the subcollector; and a shallow trench isolation region located on a surface of the buried refractory metal silicide layer. The present invention also provides a method of fabricating such a HBT. The method includes forming a buried refractory metal silicide underneath the shallow trench isolation region on the subcollector of the device.

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