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91. 发明授权

US08742475B2 Field effect transistor device and fabrication 有权
标题翻译：场效应晶体管器件和制造
公开(公告)号：US08742475B2
公开(公告)日：2014-06-03
申请号：US13554294
申请日：2012-07-20
申请人： Dechao Guo , Shu-Jen Han , Chung-Hsun Lin , Yanfeng Wang
发明人： Dechao Guo , Shu-Jen Han , Chung-Hsun Lin , Yanfeng Wang
IPC分类号： H01L21/02
CPC分类号： H01L29/42368 , H01L21/823842 , H01L21/823857 , H01L21/823871 , H01L29/66477
摘要： In one aspect of the present invention, a field effect transistor (FET) device includes a first FET including a dielectric layer disposed on a substrate, a first portion of a first metal layer disposed on the dielectric layer, and a second metal layer disposed on the first metal layer, a second FET including a second portion of the first metal layer disposed on the dielectric layer, and a boundary region separating the first FET from the second FET.
摘要翻译：在本发明的一个方面中，场效应晶体管（FET）器件包括：第一FET，其包括设置在基板上的电介质层，设置在电介质层上的第一金属层的第一部分和设置在电介质层上的第二金属层第一金属层，包括设置在电介质层上的第一金属层的第二部分的第二FET以及将第一FET与第二FET分离的边界区域。

92. 发明申请

US20140073093A1 SELF-ALIGNED CARBON NANOSTRUCTURE FIELD EFFECT TRANSISTORS USING SELECTIVE DIELECTRIC DEPOSITION 有权
标题翻译：使用选择性电介质沉积的自对准碳纳米管结构场效应晶体管
公开(公告)号：US20140073093A1
公开(公告)日：2014-03-13
申请号：US13610991
申请日：2012-09-12
申请人： Damon B. Farmer , Aaron D. Franklin , Shu-Jen Han , George S. Tulevski
发明人： Damon B. Farmer , Aaron D. Franklin , Shu-Jen Han , George S. Tulevski
IPC分类号： H01L21/336
CPC分类号： H01L29/78669 , B82Y10/00 , B82Y40/00 , H01L29/0673 , H01L29/775 , H01L29/78678 , H01L29/78696 , H01L51/0048 , H01L51/0516 , Y10S977/742
摘要： Self-aligned carbon nanostructure field effect transistor structures are provided, which are foamed using selective dielectric deposition techniques. For example, a transistor device includes an insulating substrate and a gate electrode embedded in the insulating substrate. A dielectric deposition-prohibiting layer is formed on a surface of the insulating substrate surrounding the gate electrode. A gate dielectric is selectively formed on the gate electrode. A channel structure (such as a carbon nanostructure) is disposed on the gate dielectric A passivation layer is selectively formed on the gate dielectric. Source and drain contacts are formed on opposing sides of the passivation layer in contact with the channel structure. The dielectric deposition-prohibiting layer prevents deposition of dielectric material on a surface of the insulating layer surrounding the gate electrode when selectively forming the gate dielectric and passivation layer.
摘要翻译：提供了自对准碳纳米结构场效应晶体管结构，其使用选择性电介质沉积技术发泡。例如，晶体管器件包括绝缘衬底和嵌入绝缘衬底中的栅电极。在围绕栅电极的绝缘基板的表面上形成介电沉积禁止层。选择性地在栅电极上形成栅极电介质。沟道结构（例如碳纳米结构）设置在栅极电介质上钝化层选择性地形成在栅极电介质上。源极和漏极触点形成在与沟道结构接触的钝化层的相对侧上。当选择性地形成栅极电介质和钝化层时，介电沉积禁止层防止介电材料沉积在围绕栅电极的绝缘层的表面上。

93. 发明授权

US08604519B2 Self-aligned III-V field effect transistor (FET) and integrated circuit (IC) chip 有权
标题翻译：自对准III-V场效应晶体管（FET）和集成电路（IC）芯片
公开(公告)号：US08604519B2
公开(公告)日：2013-12-10
申请号：US13487473
申请日：2012-06-04
申请人： Cheng-Wei Cheng , Shu-Jen Han , Kuen-Ting Shiu
发明人： Cheng-Wei Cheng , Shu-Jen Han , Kuen-Ting Shiu
IPC分类号： H01L29/66 , H01L21/02 , H01L31/06
CPC分类号： H01L29/0847 , H01L29/0653 , H01L29/454 , H01L29/66462 , H01L29/7781 , H01L29/78681
摘要： Field Effect Transistors (FETs), Integrated Circuit (IC) chips including the FETs, and a method of forming the FETs and IC. FET locations are defined on a layered semiconductor wafer. The layered semiconductor wafer preferably includes a III-V semiconductor surface layer, e.g., Gallium Arsenide (GaAs), and a buried layer, e.g., Aluminum Arsenide (AlAs). Portions of the buried layer are converted to dielectric material, e.g., Aluminum Oxide (AlO), at least beneath FET source/drain regions. The converted dielectric material may extend completely under the FET. Source/drain contacts are formed to FETs above the dielectric material in the buried layer.
摘要翻译：场效应晶体管（FET），包括FET的集成电路（IC）芯片，以及形成FET和IC的方法。 FET位置限定在分层半导体晶片上。分层半导体晶片优选地包括III-V半导体表面层，例如砷化镓（GaAs）和掩埋层，例如砷化铝（AlAs）。掩埋层的一部分至少在FET源极/漏极区下面被转换为电介质材料，例如氧化铝（AlO）。转换的电介质材料可以在FET下完全延伸。源极/漏极触点形成在掩埋层中的电介质材料上方的FET上。

94. 发明授权

US08519454B2 Structure and process for metal fill in replacement metal gate integration 有权
标题翻译：金属填充金属栅极整合的结构和工艺
公开(公告)号：US08519454B2
公开(公告)日：2013-08-27
申请号：US13075443
申请日：2011-03-30
申请人： Dechao Guo , Shu-Jen Han , Keith Kwong Hon Wong , Jun Yuan
发明人： Dechao Guo , Shu-Jen Han , Keith Kwong Hon Wong , Jun Yuan
IPC分类号： H01L29/76 , H01L21/338 , H01L21/84
CPC分类号： H01L29/4966 , H01L29/66545 , H01L29/7843
摘要： Processes for metal fill in replacement metal gate integration schemes and resultant devices are provided herein. The method includes forming a dummy gate on a semiconductor substrate. The dummy gate includes forming a metal layer between a first material and a second material. The method further includes partially removing the dummy gate to form an opening bounded by a spacer material. The method further includes forming a recess in the spacer material to widen a portion of the opening. The method further includes removing a remaining portion of the dummy gate through the opening to form a trench having the recess forming an upper portion thereof. The method further includes filling the trench and the recess with a replacement metal gate stack.
摘要翻译：本文提供了用于替换金属栅极集成方案和所得器件的金属填充工艺。该方法包括在半导体衬底上形成虚拟栅极。虚拟门包括在第一材料和第二材料之间形成金属层。该方法还包括部分地去除伪栅极以形成由间隔物材料限定的开口。该方法还包括在间隔物材料中形成凹槽以加宽开口的一部分。该方法还包括通过开口去除虚拟栅极的剩余部分以形成具有形成其上部的凹部的沟槽。该方法还包括用替换的金属栅极堆叠填充沟槽和凹部。

95. 发明授权

US08466493B2 Self-aligned III-V field effect transistor (FET), integrated circuit (IC) chip with self-aligned III-V FETS and method of manufacture 有权
标题翻译：具有自对准III-V FET的自对准III-V场效应晶体管（FET），集成电路（IC）芯片及其制造方法
公开(公告)号：US08466493B2
公开(公告)日：2013-06-18
申请号：US13074854
申请日：2011-03-29
申请人： Cheng-Wei Cheng , Shu-Jen Han , Kuen-Ting Shiu
发明人： Cheng-Wei Cheng , Shu-Jen Han , Kuen-Ting Shiu
IPC分类号： H01L29/66 , H01L21/8238 , H01L21/4763
CPC分类号： H01L29/0847 , H01L29/0653 , H01L29/454 , H01L29/66462 , H01L29/7781 , H01L29/78681
摘要： Field Effect Transistors (FETs), Integrated Circuit (IC) chips including the FETs, and a method of forming the FETs and IC. FET locations are defined on a layered semiconductor wafer. The layered semiconductor wafer preferably includes a III-V semiconductor surface layer, e.g., Gallium Arsenide (GaAs), and a buried layer, e.g., Aluminum Arsenide (AlAs). Portions of the buried layer are converted to dielectric material, e.g., Aluminum Oxide (AlO), at least beneath FET source/drain regions. The converted dielectric material may extend completely under the FET. Source/drain contacts are formed to FETs above the dielectric material in the buried layer.
摘要翻译：场效应晶体管（FET），包括FET的集成电路（IC）芯片，以及形成FET和IC的方法。 FET位置限定在分层半导体晶片上。分层半导体晶片优选地包括III-V半导体表面层，例如砷化镓（GaAs）和掩埋层，例如砷化铝（AlAs）。掩埋层的一部分至少在FET源极/漏极区下面被转换为电介质材料，例如氧化铝（AlO）。转换的电介质材料可以在FET下完全延伸。源极/漏极触点形成在掩埋层中的电介质材料上方的FET上。

96. 发明授权

US08445371B2 Self-aligned contacts 有权
公开(公告)号：US08445371B2
公开(公告)日：2013-05-21
申请号：US12755752
申请日：2010-04-07
申请人： Dechao Guo , Wilfried E. A. Haensch , Shu-Jen Han , Chung-Hsun Lin
发明人： Dechao Guo , Wilfried E. A. Haensch , Shu-Jen Han , Chung-Hsun Lin
IPC分类号： H01L21/3205
CPC分类号： H01L21/28008 , H01L21/28052 , H01L21/28097 , H01L21/76897 , H01L29/517 , H01L29/66507 , H01L29/66545
摘要： A method of forming a gate structure with a self-aligned contact is provided and includes sequentially depositing a sacrificial layer and a secondary layer onto poly-Si disposed at a location of the gate structure, encapsulating the sacrificial layer, the secondary layer and the poly-Si, removing the sacrificial layer through openings formed in the secondary layer and forming silicide within at least the space formally occupied by the sacrificial layer.

97. 发明申请

US20130082243A1 TRANSISTOR DEVICE WITH REDUCED GATE RESISTANCE 有权
标题翻译：具有降低栅极电阻的晶体管器件
公开(公告)号：US20130082243A1
公开(公告)日：2013-04-04
申请号：US13610381
申请日：2012-09-11
申请人： Shu-Jen Han , Alberto Valdes Garcia
发明人： Shu-Jen Han , Alberto Valdes Garcia
IPC分类号： H01L29/78 , B82Y99/00
CPC分类号： H01L29/66742 , H01L29/42384 , H01L29/7781 , H01L29/78603 , H01L29/78636 , H01L29/78684
摘要： A device with reduced gate resistance includes a gate structure having a first conductive portion and a second conductive portion formed in electrical contact with the first conductive portion and extending laterally beyond the first conductive portion. The gate structure is embedded in a dielectric material and has a gate dielectric on the first conductive portion. A channel layer is provided over the first conductive portion. Source and drain electrodes are formed on opposite end portions of a channel region of the channel layer. Methods for forming a device with reduced gate resistance are also provided.
摘要翻译：具有降低的栅极电阻的器件包括具有第一导电部分和形成为与第一导电部分电接触并且横向延伸超过第一导电部分延伸的第二导电部分的栅极结构。栅极结构嵌入电介质材料中，并且在第一导电部分上具有栅极电介质。沟道层设置在第一导电部分上。源极和漏极形成在沟道层的沟道区的相对端部上。还提供了形成栅极电阻降低的器件的方法。

98. 发明授权

US08338258B2 Embedded stressor for semiconductor structures 有权
标题翻译：半导体结构的嵌入式应力器
公开(公告)号：US08338258B2
公开(公告)日：2012-12-25
申请号：US12625827
申请日：2009-11-25
申请人： Dechao Guo , Shu-Jen Han , Pranita Kulkarni , Philip J. Oldiges
发明人： Dechao Guo , Shu-Jen Han , Pranita Kulkarni , Philip J. Oldiges
IPC分类号： H01L21/336
CPC分类号： H01L29/1054 , H01L29/517 , H01L29/66651 , H01L29/66772 , H01L29/78687
摘要： A method of fabricating an embedded stressor within a semiconductor structure and a semiconductor structure including the embedded stressor includes forming forming a dummy gate stack over a substrate of stressor material, anistropically etching sidewall portions of the substrate subjacent to the dummy gate stack to form the embedded stressor having angled sidewall portions, forming conductive material onto the angled sidewall portions of the embedded stressor, removing the dummy gate stack, planarizing the conductive material, and forming a gate stack on the conductive material.
摘要翻译：一种在半导体结构内制造嵌入式应力器的方法以及包括所述嵌入式应力器的半导体结构的方法包括在所述应力源材料的衬底上形成形成虚拟栅极叠层的方法，将所述衬底的与所述虚拟栅极堆叠相邻的衬底的侧壁部分，应力器具有成角度的侧壁部分，将导电材料形成在嵌入式应力源的成角度的侧壁部分上，去除虚拟栅极堆叠，平坦化导电材料，以及在导电材料上形成栅极叠层。

99. 发明授权

US08338256B2 Multi-gate transistor having sidewall contacts 有权
标题翻译：具有侧壁接触的多栅极晶体管
公开(公告)号：US08338256B2
公开(公告)日：2012-12-25
申请号：US12832829
申请日：2010-07-08
申请人： Josephine B. Chang , Dechao Guo , Shu-Jen Han , Chung-Hsun Lin
发明人： Josephine B. Chang , Dechao Guo , Shu-Jen Han , Chung-Hsun Lin
IPC分类号： H01L21/336 , H01L29/76
CPC分类号： H01L29/785 , H01L29/66795 , H01L2029/7858
摘要： A multi-gate transistor having a plurality of sidewall contacts and a fabrication method that includes forming a semiconductor fin on a semiconductor substrate and etching a trench within the semiconductor fin, depositing an oxide material within the etched trench, and etching the oxide material to form a dummy oxide layer along exposed walls within the etched trench; and forming a spacer dielectric layer along vertical sidewalls of the dummy oxide layer. The method further includes removing exposed dummy oxide layer in a channel region in the semiconductor fin and beneath the spacer dielectric layer, forming a high-k material liner along sidewalls of the channel region in the semiconductor fin, forming a metal gate stack within the etched trench, and forming a plurality of sidewall contacts within the semiconductor fin along adjacent sidewalls of the dummy oxide layer.
摘要翻译：一种具有多个侧壁触点的多栅极晶体管及其制造方法，包括在半导体衬底上形成半导体鳍片并蚀刻半导体鳍片内的沟槽，在蚀刻沟槽内沉积氧化物材料，并蚀刻氧化物材料以形成沿着蚀刻沟槽内的暴露壁的虚拟氧化物层; 以及沿所述虚拟氧化物层的垂直侧壁形成间隔电介质层。该方法还包括去除半导体鳍片中的沟道区域中的暴露的虚拟氧化物层并且在间隔物电介质层下方形成沿着半导体鳍片中的沟道区域的侧壁形成高k材料衬垫，在蚀刻沟槽，并且在半导体鳍片内沿虚拟氧化物层的相邻侧壁形成多个侧壁接触。

100. 发明申请

US20120261728A1 EMBEDDED STRESSOR FOR SEMICONDUCTOR STRUCTURES 有权
标题翻译：用于半导体结构的嵌入式压电器
公开(公告)号：US20120261728A1
公开(公告)日：2012-10-18
申请号：US13529558
申请日：2012-06-21
申请人： Dechao Guo , Shu-Jen Han , Pranita Kulkarni , Philip J. Oldiges
发明人： Dechao Guo , Shu-Jen Han , Pranita Kulkarni , Philip J. Oldiges
IPC分类号： H01L29/78
CPC分类号： H01L29/1054 , H01L29/517 , H01L29/66651 , H01L29/66772 , H01L29/78687
摘要： A semiconductor structure includes a semiconductor substrate; a gate stack on the semiconductor substrate; a plurality of spacers disposed on laterally opposing sides of the gate stack; source and drain regions proximate to the spacers, and a channel region subjacent to the gate stack and disposed between the source and drain regions; and a stressor subjacent to the channel region, and embedded within the semiconductor substrate, the embedded stressor being formed of a triangular-shape.
摘要翻译：半导体结构包括半导体衬底; 半导体衬底上的栅极堆叠; 设置在所述栅极堆叠的横向相对侧上的多个间隔件; 邻近间隔物的源极和漏极区域以及位于栅极堆叠下方并设置在源极和漏极区域之间的沟道区域; 以及位于所述沟道区域的下方并嵌入在所述半导体衬底内的应力器，所述嵌入式应力器由三角形形成。

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