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91. 发明授权

US06309962B1 Film stack and etching sequence for dual damascene 有权
标题翻译：双重镶嵌薄膜叠层和蚀刻顺序
公开(公告)号：US06309962B1
公开(公告)日：2001-10-30
申请号：US09396516
申请日：1999-09-15
申请人： Chao-Cheng Chen , Li-Chi Chao , Jen-Cheng Liu , Min-Huei Lui , Chia-Shiung Tsai
发明人： Chao-Cheng Chen , Li-Chi Chao , Jen-Cheng Liu , Min-Huei Lui , Chia-Shiung Tsai
IPC分类号： H01L214763
CPC分类号： H01L21/76811 , H01L21/31144 , H01L21/76813
摘要： A process for forming a dual damascene cavity in a dielectric, particularly a low k organic dielectric, is described. The dielectric is composed of two layers separated by an etch stop layer. Formation of the damascene cavity is achieved by using a hard mask that is made up of two layers of silicon oxynitride separated by layer of silicon oxide. For both the trench first and via first approaches, the first cavity is formed using only the upper silicon oxynitride layer as the mask. Thus, when the second portion is patterned, little or no misalignment occurs because said upper layer is relatively thin. Additional etching steps result in a cavity and trench part that extend as far as the etch stop layer located between the dielectric layers. Final removal of photoresist occurs with a hard mask still in place so no damage to the organic dielectric occurs. A final etch step then completes the process.
摘要翻译：描述了在电介质，特别是低k有机电介质中形成双镶嵌腔的工艺。电介质由两层由蚀刻停止层隔开组成。通过使用由两层氧氮化硅分离的氧化硅层组成的硬掩模来实现镶嵌腔的形成。对于沟槽第一和通过第一方法，仅使用上部氧氮化硅层作为掩模形成第一腔体。因此，当第二部分被图案化时，由于所述上层相对较薄，所以几乎不发生不对准。另外的蚀刻步骤导致空腔和沟槽部分延伸到位于电介质层之间的蚀刻停止层的尽可能深。光致抗蚀剂的最终去除是在硬掩模仍然存在的情况下发生的，因此不会损害有机电介质。最终蚀刻步骤然后完成该过程。

92. 发明授权

US06211061B1 Dual damascene process for carbon-based low-K materials 有权
标题翻译：用于碳基低K材料的双镶嵌工艺
公开(公告)号：US06211061B1
公开(公告)日：2001-04-03
申请号：US09431536
申请日：1999-10-29
申请人： Chao-Cheng Chen , Ming-Huei Lui , Jen-Cheng Liu , Li-chih Chao , Chia-Shiung Tsai
发明人： Chao-Cheng Chen , Ming-Huei Lui , Jen-Cheng Liu , Li-chih Chao , Chia-Shiung Tsai
IPC分类号： H01L214763
CPC分类号： H01L21/76808
摘要： A method for forming a dual damascene structure in a carbon-based, low-K material. The process begins by providing a semiconductor structure having a first metal pattern thereover, wherein the first metal pattern has a first barrier layer thereon. An organic dielectric layer is formed on the first barrier layer, and a hard mask layer is formed on the dielectric layer. The hard mask layer and the dielectric layer are patterned to form a trench. A second barrier layer is formed over the hard mask layer and on the bottom and sidewalls of the trench. A barc layer is formed over the second barrier layer, thereby filling the trench. The barc layer, the second barrier layer, and the dielectric layer are patterned to form a via opening, preferably using a photoresist mask. The barc layer is patterned without faceting the edges of the via opening due to the second barrier layer. The barc layer and the etch mask are removed by the dielectric layer etch. The first barrier layer and the second barrier layer are removed. A third barrier layer is formed on the bottom and sidewalls of the trench, on the sidewalls of the via opening, and on the first metal pattern through the via opening. The trench and the via opening are filled with metal to form a damascene structure.
摘要翻译：一种在碳基低K材料中形成双镶嵌结构的方法。该过程开始于提供其上具有第一金属图案的半导体结构，其中第一金属图案在其上具有第一阻挡层。在第一阻挡层上形成有机电介质层，在电介质层上形成硬掩模层。图案化硬掩模层和电介质层以形成沟槽。第二阻挡层形成在硬掩模层之上以及沟槽的底部和侧壁上。在第二阻挡层上形成棒状层，由此填充沟槽。将棒状层，第二阻挡层和电介质层图案化以形成通孔，优选使用光致抗蚀剂掩模。由于第二阻挡层，棒状层被图案化而不使通孔开口的边缘刻划。通过电介质层蚀刻去除棒状层和蚀刻掩模。去除第一阻挡层和第二阻挡层。第三阻挡层形成在沟槽的底部和侧壁上，通孔开口的侧壁上，通过通孔开口形成在第一金属图案上。沟槽和通孔开口用金属填充以形成镶嵌结构。

93. 发明授权

US06194284B1 Method for forming residue free etched silicon layer 有权
标题翻译：无残留蚀刻硅层的形成方法
公开(公告)号：US06194284B1
公开(公告)日：2001-02-27
申请号：US09385522
申请日：1999-08-30
申请人： Chao-Cheng Chen
发明人： Chao-Cheng Chen
IPC分类号： H01L2176
CPC分类号： H01L21/76224 , H01L21/3065
摘要： A method for forming within a semiconductor substrate layer employed within a semiconductor microelectronics fabrication a shallow trench structure with improved surface properties. There is provided a silicon semiconductor substrate layer. There is then formed over the substrate a patterned photoresist etch mask layer containing the trench pattern. There may be an optional layer formed intermediate between the substrate layer and the patterned photoeresist etch mask layer comprising a pad oxide sub-layer and a silicon nitride etch stop sub-layer. There is then etched the trench pattern employing the photoresist etch mask layer into the substrate layer with a first anisotropic subtractive etching environment. There is then further etched the anisotropically etched trench pattern with a second isotropic subtractive etching environment to form the isotropically etched trench with smooth surfaces. There is then stripped the photoresist etch mask layer and process residues to form a shallow trench structure with attenuated defects and asperities.
摘要翻译：一种用于在半导体微电子学制造中使用的半导体衬底层内形成具有改进的表面性质的浅沟槽结构的方法。提供硅半导体衬底层。然后在衬底上形成包含沟槽图案的图案化的光致抗蚀剂蚀刻掩模层。可以在衬底层和包括衬垫氧化物子层和氮化硅蚀刻停止子层的图案化光致抗蚀剂蚀刻掩模层之间形成可选层。然后，利用第一各向异性的减去蚀刻环境，将采用光致抗蚀剂蚀刻掩模层的沟槽图案蚀刻到衬底层中。然后用第二各向同性的消减蚀刻环境进一步蚀刻各向异性蚀刻的沟槽图案，以形成具有光滑表面的各向同性蚀刻的沟槽。然后剥离光致抗蚀剂蚀刻掩模层并处理残留物以形成具有减弱的缺陷和粗糙度的浅沟槽结构。

94. 发明授权

US06194128B1 Method of dual damascene etching 有权
标题翻译：双镶嵌蚀刻方法
公开(公告)号：US06194128B1
公开(公告)日：2001-02-27
申请号：US09156053
申请日：1998-09-17
申请人： Hun-Jan Tao , Chao-Cheng Chen , Chia-Shiung Tsai
发明人： Hun-Jan Tao , Chao-Cheng Chen , Chia-Shiung Tsai
IPC分类号： G03F700
CPC分类号： H01L21/76835 , H01L21/0332 , H01L21/0337 , H01L21/31116 , H01L21/3144 , H01L21/3145 , H01L21/76807 , H01L21/76813 , H01L21/76814 , H01L2221/1036
摘要： A novel method of dual damascene etching is disclosed. It is shown that the performance of ULSI circuits can be improved by shrinking interconnect dimensions through the use of dual damascene processes, using hard-masks to achieve vertical walls and hence smaller spaces in the damascene structures, introducing low-k (dielectric constant) insulating materials to reduce RC delays, and metallizing with copper without the deleterious effects of bridging after CMP. These are accomplished by using a novel recipe for etching the hard-masks used in a dual damascene process and still another recipe for etching low-k dielectric layers in three different combinations with oxide-based dielectric layers.
摘要翻译：公开了一种双镶嵌蚀刻的新方法。通过使用双镶嵌工艺，通过使用硬掩模实现垂直壁并因此在镶嵌结构中实现更小的空间来缩小互连尺寸，可以提高ULSI电路的性能，引入低k（介电常数）绝缘减少RC延迟的材料，以及铜的金属化，而没有CMP后的桥接的有害影响。这些是通过使用用于蚀刻在双镶嵌工艺中使用的硬掩模的新配方来实现的，还有另一种用于蚀刻具有氧化物基电介质层的三种不同组合的低k电介质层的方案。

95. 发明授权

US6027861A VLSIC patterning process 失效
标题翻译： VLSIC图案化工艺
公开(公告)号：US6027861A
公开(公告)日：2000-02-22
申请号：US44763
申请日：1998-03-20
申请人： Chen-Hua Yu , Syun-Ming Jang , Chao-Cheng Chen
发明人： Chen-Hua Yu , Syun-Ming Jang , Chao-Cheng Chen
IPC分类号： H01L21/033 , H01L21/311 , H01L21/3205 , H01L21/768 , G03F7/20 , H01L21/027
CPC分类号： H01L21/76855 , H01L21/31144 , H01L21/32053 , H01L21/76802 , H01L21/76841 , H01L21/76843 , H01L21/76877 , H01L21/0332 , H01L21/31116
摘要： A method for etching of sub-quarter micron openings in insulative layers for contacts and vias is described. The method uses high resolution DUV photolithography. By using a thin layer of photoresist to pattern a hardmask, full advantage of the high resolution can be attained. The hardmask in turn, is sufficiently durable to withstand subsequent etching of the insulative layer. The methods taught by this invention are of particular value for the formation of contacts to semiconductive devices although they are also applied to forming via openings. DUV photoresists having thicknesses of less than 500 nm are used with a DUV stepper. The hardmask materials include Ti/TiN and amorphous silicon. Etching selectivities of these materials with respect to typical insulative materials used in integrated circuit manufacture are of the order of 50:1.
摘要翻译：描述了用于在接触和通孔的绝缘层中蚀刻二分之一微米开口的方法。该方法采用高分辨率DUV光刻技术。通过使用薄层的光致抗蚀剂来模拟硬掩模，可以获得高分辨率的全部优点。依次进行硬掩模，足够耐用以承受绝缘层的后续蚀刻。本发明教导的方法对于形成与半导体器件的接触具有特别的价值，尽管它们也用于形成通孔。使用厚度小于500nm的DUV光刻胶与DUV步进器一起使用。硬掩模材料包括Ti / TiN和非晶硅。相对于集成电路制造中使用的典型绝缘材料，这些材料的蚀刻选择性为50：1。

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