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91. 发明授权

US08194724B1 Adaptive equalization methods and apparatus for programmable logic devices 有权
标题翻译：用于可编程逻辑器件的自适应均衡方法和装置
公开(公告)号：US08194724B1
公开(公告)日：2012-06-05
申请号：US12823783
申请日：2010-06-25
申请人： Wilson Wong , Sergey Shumarayev , Simardeep Maangat , Rakesh Patel
发明人： Wilson Wong , Sergey Shumarayev , Simardeep Maangat , Rakesh Patel
IPC分类号： H03H7/30 , H03H7/40
CPC分类号： H04L25/03044 , H04L2025/03356 , H04L2025/03579 , H04L2025/03783
摘要： A programmable logic device is provided with adaptive equalization circuitry that is programmable in one or more respects. Examples of the programmable aspects of the equalization circuitry are (1) the number of taps used, (2) whether integer or fractional spaced taps are used, (3) what starting values are used in the computation of coefficient values, (4) whether satisfactory coefficient values are computed only once or on an on-going basis, (5) whether an error signal is generated using a decision directed algorithm or using a training pattern, (6) what training pattern (if any) is used, and/or (7) the location of the sampling point in the bit period of the signal to be equalized.
摘要翻译：可编程逻辑器件设置有可在一个或多个方面可编程的自适应均衡电路。均衡电路的可编程方面的示例是（1）使用的抽头数量，（2）是否使用整数或分数间隔抽头，（3）在系数值的计算中使用什么起始值，（4）是否（5）是否使用决策导向算法或使用训练模式生成错误信号，（6）使用何种训练模式（如果有的话）和/ 或者（7）要被均衡的信号的位周期内的采样点的位置。

92. 发明申请

US20100058099A1 HETEROGENEOUS TRANSCEIVER ARCHITECTURE FOR WIDE RANGE PROGRAMMABILITY OF PROGRAMMABLE LOGIC DEVICES 有权
标题翻译：用于可编程逻辑器件的宽范围可编程性的异构收发器架构
公开(公告)号：US20100058099A1
公开(公告)日：2010-03-04
申请号：US12576507
申请日：2009-10-09
申请人： Sergey Shumarayev , Bill W. Bereza , Chong H. Lee , Rakesh H. Patel , Wilson Wong
发明人： Sergey Shumarayev , Bill W. Bereza , Chong H. Lee , Rakesh H. Patel , Wilson Wong
IPC分类号： G06F1/04 , G06F1/12
CPC分类号： H04L5/14 , H03K19/17744 , H04L27/00
摘要： High-speed serial data transceiver circuitry on a programmable logic device (“PLD”) includes some channels that are able to operate at data rates up to a first, relatively low maximum data rate, and other channels that are able to operate at data rates up to a second, relatively high maximum data rate. The relatively low-speed channels are served by relatively low-speed phase locked loop (“PLL”) circuitry, and have other circuit components that are typically needed for handling data that is transmitted at relatively low data rates. The relatively high-speed channels are served by relatively high-speed PLLs, and have other circuit components that are typically needed for handling data that is transmitted at relatively high data rates.
摘要翻译：可编程逻辑器件（“PLD”）上的高速串行数据收发器电路包括一些能够以高达第一，相对较低的最大数据速率的数据速率工作的通道，以及能够以数据速率操作的其他通道达到第二个相对较高的最大数据速率。相对低速的通道由相对低速的锁相环（“PLL”）电路服务，并且具有通常用于处理以相对低的数据速率发送的数据所需的其他电路组件。相对高速的信道由相对高速的PLL服务，并且具有通常用于处理以相对高的数据速率传输的数据所需的其他电路部件。

93. 发明申请

US20090284292A1 SIGNAL ADJUSTMENT RECEIVER CIRCUITRY 审中-公开
公开(公告)号：US20090284292A1
公开(公告)日：2009-11-19
申请号：US12511024
申请日：2009-07-28
申请人： Wilson Wong , Rakesh H. Patel , Sergey Shumarayev , Tin H. Lai
发明人： Wilson Wong , Rakesh H. Patel , Sergey Shumarayev , Tin H. Lai
IPC分类号： H03K5/12
CPC分类号： H04B7/005 , H04L25/03006 , H04L25/061
摘要： Systems and methods for adjusting a signal received from a communication path are disclosed. A receiver can receive a signal from a communication path which attenuates at least some frequency components of the signal. The receiver can include an equalization block that adjusts at least some of the frequency content of the received signal, a signal normalization block that provides a normalized signal amplitude and/or a normalized edge slope, and a control block. In one embodiment, the control block controls frequency adjustment in the equalization block for high frequencies but not for low frequencies. For low frequency adjustment, the control block controls the normalized signal amplitude in the signal normalization block. In this manner, controlled adjustment for low frequency content is performed in the signal normalization block.

94. 发明授权

US07541857B1 Comparator offset cancellation assisted by PLD resources 有权
标题翻译：比较器偏移消除由PLD资源辅助
公开(公告)号：US07541857B1
公开(公告)日：2009-06-02
申请号：US11323571
申请日：2005-12-29
申请人： Wilson Wong , Tin H. Lai , Sergey Shumarayev , Rakesh H. Patel
发明人： Wilson Wong , Tin H. Lai , Sergey Shumarayev , Rakesh H. Patel
IPC分类号： H03L5/00
CPC分类号： H03F3/45183 , H03F3/45632 , H03F2203/45212 , H03F2203/45646 , H03F2203/45681 , H03F2203/45702 , H03F2203/45726
摘要： An impedance compensation circuit for inputs of a programmable device includes programmable impedance circuits connected with input nodes. The programmable impedance circuits can be configured to apply a compensating voltages to input nodes to reduce or eliminate unwanted offset voltages. An impedance compensation circuit may include resistors in series or current sources in parallel. A set of bypass switches selectively apply each resistor or current source to an input node, thereby changing the offset voltage of the node and compensating for impedance mismatches. Control logic provides signals to control the bypass switches. The control logic may be implemented using programmable device resources, enabling the control logic to be updated and improved after the manufacturing of the device is complete. The control logic can automatically evaluate offset voltages at any time and change compensating impedances accordingly. This reduces manufacturing costs and takes into account temperature and aging effects.
摘要翻译：用于可编程器件的输入的阻抗补偿电路包括与输入节点连接的可编程阻抗电路。可编程阻抗电路可以配置为向输入节点施加补偿电压以减少或消除不期望的失调电压。阻抗补偿电路可以包括并联的串联或电流源的电阻器。一组旁路开关选择性地将每个电阻器或电流源施加到输入节点，从而改变节点的偏移电压并补偿阻抗失配。控制逻辑提供信号来控制旁路开关。可以使用可编程设备资源实现控制逻辑，使得在设备的制造完成之后能够更新和改进控制逻辑。控制逻辑可以随时自动评估偏移电压，并相应地改变补偿阻抗。这降低了制造成本并考虑了温度和老化的影响。

95. 发明授权

US07514968B1 H-tree driver circuitry 有权
标题翻译： H树驱动电路
公开(公告)号：US07514968B1
公开(公告)日：2009-04-07
申请号：US11786295
申请日：2007-04-10
申请人： Tin H. Lai , Wilson Wong , Sergey Shumarayev , Tim Tri Hoang
发明人： Tin H. Lai , Wilson Wong , Sergey Shumarayev , Tim Tri Hoang
IPC分类号： H03K3/00
CPC分类号： H03K19/018528 , H04L25/0272
摘要： An H-tree driver circuit has pull-up and pull-down current sources, each of which is implemented using a low-voltage-cascode topology.
摘要翻译： H-tree驱动电路具有上拉和下拉电流源，每个都使用低压共源共栅拓扑来实现。

96. 发明授权

US07492816B1 Adaptive equalization methods and apparatus 失效
标题翻译：自适应均衡方法和装置
公开(公告)号：US07492816B1
公开(公告)日：2009-02-17
申请号：US10853987
申请日：2004-05-25
申请人： Wilson Wong , Sergey Shumarayev , Rakesh Patel
发明人： Wilson Wong , Sergey Shumarayev , Rakesh Patel
IPC分类号： H03H7/30
CPC分类号： H04L1/205 , H04B17/21 , H04B17/24 , H04B17/309 , H04L25/03006
摘要： A system includes a programmable transmitter device (e.g., a PLD) connected to a programmable receiver device (e.g., another PLD) via a transmission medium for transmitting a high-speed data signal from the transmitter to the receiver. During a test mode of operation a low-speed communication link between the transmitter and receiver allows those devices to work together to transmit test signals having known characteristics from the transmitter to the receiver via the transmission medium, to analyze the test signals as received by the receiver, and to adjust at least some aspect of the system (e.g., equalizer circuitry in the receiver) to at least partly compensate for losses in the test signals as received by the receiver.
摘要翻译：系统包括经由用于从发射机向接收机发送高速数据信号的传输介质连接到可编程接收机设备（例如，另一个PLD）的可编程发射机设备（例如，PLD）。在测试操作模式期间，发射机和接收机之间的低速通信链路允许这些设备一起工作，以经由传输介质从发射机向接收机发送具有已知特性的测试信号，以分析由接收器，并且至少部分地补偿由接收器接收的测试信号中的损耗，系统的至少一些方面（例如，接收机中的均衡器电路）。

97. 发明授权

US07436228B1 Variable-bandwidth loop filter methods and apparatus 失效
标题翻译：可变带宽环路滤波器的方法和装置
公开(公告)号：US07436228B1
公开(公告)日：2008-10-14
申请号：US11317126
申请日：2005-12-22
申请人： Tim Tri Hoang , Sergey Shumarayev , Wilson Wong
发明人： Tim Tri Hoang , Sergey Shumarayev , Wilson Wong
IPC分类号： H03K5/00 , H03L7/06
CPC分类号： H03L7/087 , H03L7/0891 , H03L7/093 , H03L7/18
摘要： Methods and apparatus are provided for varying the bandwidth of a loop filter in a loop circuit (e.g., a phase-locked loop circuit). The loop filter can include first and second resistor circuitries coupled to a capacitor. One of the resistor circuitries can be coupled to an output of the loop circuit in response to selection of a mode of operation. The resistor circuitries can each include a plurality of resistors that can be selectively coupled in series to the capacitor or bypassed. In addition, the output of the loop circuit can be coupled to a second capacitor. Either or both of the capacitors can be programmable.
摘要翻译：提供了用于改变环路电路（例如，锁相环电路）中的环路滤波器的带宽的方法和装置。环路滤波器可以包括耦合到电容器的第一和第二电阻器电路。响应于操作模式的选择，电阻器电路中的一个可以耦合到环路电路的输出。电阻器电路可以各自包括可以选择性地串联耦合到电容器或绕过的多个电阻器。此外，环路电路的输出可以耦合到第二电容器。电容器中的任一个或两个可以是可编程的。

98. 发明申请

US20080225933A1 PROTOCOL-AGNOSTIC AUTOMATIC RATE NEGOTIATION FOR HIGH-SPEED SERIAL INTERFACE IN A PROGRAMMABLE LOGIC DEVICE 有权
标题翻译：可编程逻辑器件中高速串行接口的协议自动比率自动调节
公开(公告)号：US20080225933A1
公开(公告)日：2008-09-18
申请号：US11687052
申请日：2007-03-16
申请人： Allen Chan , Wilson Wong , Sergey Shumarayev
发明人： Allen Chan , Wilson Wong , Sergey Shumarayev
IPC分类号： H04B17/00
CPC分类号： G06F13/385 , H03K19/177 , H03K19/17744 , H04L5/1446
摘要： Automatic rate negotiation logic for a high speed serial interface in a programmable logic device determines whether multiple occurrences of a single-bit transition (i.e., a data transition from “0” to “1” to “0” or from “1” to “0” to “1”) occur within a predetermined time interval on a data channel of a high-speed serial interface. The interval preferably is selected such that multiple occurrences of a single-bit transition mean that the data channel is operating in full-rate mode. The rate negotiation logic may share a phase detector with clock data recovery circuitry in the interface. The phase detector may be a bang-bang phase detector specially adapted to detect single-bit transitions.
摘要翻译：用于可编程逻辑器件中的高速串行接口的自动速率协商逻辑确定单个位转换的多次出现（即，从“0”到“1”到“0”或从“1”到“1”的数据转换 0“到”1“）发生在高速串行接口的数据信道上的预定时间间隔内。间隔优选地被选择为使得多次出现单位转换意味着数据信道以全速率模式运行。速率协商逻辑可以在接口中共享具有时钟数据恢复电路的相位检测器。相位检测器可以是专门用于检测单位转换的爆发相位检测器。

99. 发明申请

US20070071084A1 Programmable digital equalization control circuitry and methods 失效
标题翻译：可编程数字均衡控制电路和方法
公开(公告)号：US20070071084A1
公开(公告)日：2007-03-29
申请号：US11238365
申请日：2005-09-28
申请人： Tin Lai , Sergey Shumarayev , Simardeep Maangat , Wilson Wong
发明人： Tin Lai , Sergey Shumarayev , Simardeep Maangat , Wilson Wong
IPC分类号： H03H7/30 , H04L25/06 , H04L27/08
CPC分类号： H03G3/3089 , H04L25/03885
摘要： Equalization circuitry may be used to compensate for the attenuation of a data signal caused by a transmission medium. The control circuitry for the equalization circuitry may generate control inputs for equalization stages that control the amount of gain provided to the data signal. A comparator may determine whether the gain from the equalization circuitry is less than or more than the desired amount of gain. A programmable up/down counter may adjust the counter value based on the output of the comparator. The counter value may be converted into one or more analog voltages using one or more digital-to-analog converters. These analog voltages may be provided to the equalization stages as control inputs. The control circuitry may also include hysteresis circuitry that prevents the counter value from being adjusted when the gain produced by the equalization stages is close to the desired amount of gain.
摘要翻译：均衡电路可用于补偿由传输介质引起的数据信号的衰减。用于均衡电路的控制电路可以产生用于控制提供给数据信号的增益量的均衡级的控制输入。比较器可以确定来自均衡电路的增益是否小于或大于期望的增益量。可编程上/下计数器可以根据比较器的输出来调整计数器值。可以使用一个或多个数模转换器将计数器值转换成一个或多个模拟电压。这些模拟电压可以作为控制输入提供给均衡级。控制电路还可以包括滞后电路，当由均衡级产生的增益接近期望的增益量时，阻止计数器值被调整。

100. 发明授权

US07176710B1 Dynamically adjustable termination impedance control techniques 有权
标题翻译：动态可调终端阻抗控制技术
公开(公告)号：US07176710B1
公开(公告)日：2007-02-13
申请号：US11093188
申请日：2005-03-28
申请人： Mei Luo , Wilson Wong , Sergey Shumarayev
发明人： Mei Luo , Wilson Wong , Sergey Shumarayev
IPC分类号： H03K19/175
CPC分类号： H04L25/0278
摘要： The on-chip impedance termination circuits can be dynamically adjusted to match transmission line impedance values. A network of termination resistors on an integrated circuit provides termination impedance to a transmission line coupled to an IO pin. The termination resistors are coupled in series and in parallel with each other. Pass gates are coupled to the resistors. The pass gates are individually turned ON or OFF to couple or decouple resistors from the transmission line. Each pass gate is set to be ON or OFF to provide a selected termination resistance value to the transmission line. The termination resistance of the resistor network can be increased or decreased to match the impedance of different transmission lines. The termination resistance can also be varied to compensate for changes in the resistors caused by temperature variations on the integrated circuit or other factors.
摘要翻译：片内阻抗终端电路可以动态调节，以匹配传输线阻抗值。集成电路上的终端电阻网络为耦合到IO引脚的传输线提供终端阻抗。终端电阻器串联耦合并且彼此并联。通孔与电阻耦合。传递门单独接通或断开以将电阻与传输线耦合或去耦。每个通过门被设置为ON或OFF以向传输线提供所选择的终端电阻值。可以增加或减少电阻网络的终端电阻以匹配不同传输线路的阻抗。也可以改变终端电阻以补偿由集成电路上的温度变化或其他因素引起的电阻器的变化。

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