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91. 发明授权

US5091027A Process for producing hard roll 失效
标题翻译：硬辊生产工艺
公开(公告)号：US5091027A
公开(公告)日：1992-02-25
申请号：US567529
申请日：1990-08-15
申请人： Atsuo Watanabe
发明人： Atsuo Watanabe
IPC分类号： B29C63/18 , B29D99/00 , D21F3/08 , D21G1/02 , F16C13/00
CPC分类号： D21G1/0246 , B29C63/18 , B29D99/0035 , D21F3/08 , D21G1/0233 , F16C13/00 , B29L2031/324 , Y10T156/103 , Y10T29/49551
摘要： A hard roll is produced by a process utilizing the steps of winding a fiber material impregnated with a thermosetting resin around the outer peripheral surface of a metal roll core to form a fiber-reinforced lower winding layer, then injecting a thermosetting synthetic resin material into a mold of predetermined size and curing the material at a specified temperature to form an outer layer hollow cylinder separately from the first step. The next stepsave fitting the outer layer cylinder around the roll core covered with the winding layer, and injecting an adhesive of low viscosity into an annular clearance between the winding layer and the cylinder and then curing the adhesive at a specified temperature to bond the winding layer to the cylinder with the layer of adhesive.
摘要翻译：通过以下步骤生产硬卷，该方法采用以下步骤：将浸渍有热固性树脂的纤维材料缠绕在金属辊芯的外周表面上，以形成纤维增强的下卷绕层，然后将热固性合成树脂材料注入预定尺寸的模具，并在特定温度下固化材料以形成与第一步骤分离的外层中空筒体。下一个步骤将外层圆筒围绕卷绕在卷芯上的辊芯安装，并将低粘度的粘合剂注入到卷绕层和圆筒之间的环形间隙中，然后在特定温度下固化粘合剂以将卷绕层到气瓶与粘合剂层。

92. 发明授权

US4368568A Elastomeric material covered rolls and a method of making the same 失效
标题翻译：弹性材料覆盖辊及其制造方法
公开(公告)号：US4368568A
公开(公告)日：1983-01-18
申请号：US174244
申请日：1980-07-31
申请人： Atsuo Watanabe
发明人： Atsuo Watanabe
IPC分类号： B29C57/00 , B29C67/00 , B29C70/06 , B29D99/00 , B32B15/095 , B32B27/20 , D06B23/02 , D06F67/02 , D21F3/08 , F16C13/00 , B21B31/08
CPC分类号： D06B23/026 , B29D99/0035 , D06F67/02 , D21F3/08 , F16C13/00 , B29L2031/324
摘要： A polyurethane rubber covered roll comprises a metallic roll core, a reinforcing layer adhering to the outer surface of the roll core, and formed by a nonwoven fabric impregnated with a mixture of a thermosetting resin and a fine inorganic powder, and a layer of polyurethane rubber united integrally with the outer surface of the reinforcing layer. The roll is useful when used, for example, in a paper machine.
摘要翻译：聚氨酯橡胶覆盖辊包括金属辊芯，附着在辊芯外表面上的增强层，并且由浸渍有热固性树脂和无机细粉末的混合物的无纺布形成，并且由聚氨酯橡胶层与加强层的外表面整体结合。当在例如造纸机中使用时，该卷是有用的。

93. 发明授权

US07704350B2 Press belt and shoe press roll 有权
标题翻译：压榨皮带和鞋压榨辊
公开(公告)号：US07704350B2
公开(公告)日：2010-04-27
申请号：US10571228
申请日：2004-09-01
申请人： Takahisa Hikita , Atsuo Watanabe
发明人： Takahisa Hikita , Atsuo Watanabe
IPC分类号： D21F3/02 , B30B3/02 , B30B5/04
CPC分类号： D21F3/0218 , D21F3/0227 , Y10S162/901 , Y10T428/24479 , Y10T428/2457 , Y10T442/2369 , Y10T442/3854
摘要： A press belt (2) comprises both-end corresponding regions B positioned so as to correspond to both ends of a press roll (1) or a press shoe (3) in a width direction and having a small thickness and a center region A positioned between the both-end corresponding regions B and having a thickness larger than that of the both-end corresponding region B.
摘要翻译：压榨带（2）包括两端对应的区域B，其定位成对应于压榨辊（1）或压板（3）在宽度方向上的两端并且具有小的厚度并且中心区域A定位在两端对应区域B之间，其厚度大于两端对应区域B的厚度。

94. 发明申请

US20090115506A1 INTERFACE DEVICE AND INFORMATION PROCESSING SYSTEM 失效
标题翻译：接口设备和信息处理系统
公开(公告)号：US20090115506A1
公开(公告)日：2009-05-07
申请号：US12345049
申请日：2008-12-29
申请人： Fumio Murabayashi , Takashi Sase , Mutsumi Kikuchi , Atsuo Watanabe , Masatsugu Amishiro , Kenji Tabuchi
发明人： Fumio Murabayashi , Takashi Sase , Mutsumi Kikuchi , Atsuo Watanabe , Masatsugu Amishiro , Kenji Tabuchi
IPC分类号： H03F1/50
CPC分类号： H01L21/76283 , G05B19/0428 , G05B2219/25428 , G05B2219/25462 , H01L27/0629 , H04L25/0266
摘要： A first converter circuit converts a state signal, whose level is constant or slowly varies during a predetermine period of time, into a pulse signal to allow the signal to propagate across an electrically insulating area. A second converter circuit converts the pulse signal, which has propagated through an insulating circuit, into the original state signal or a signal having the same characteristics as the original state signal.
摘要翻译：第一转换器电路将预定时间段内的电平恒定或缓慢变化的状态信号转换成脉冲信号，以允许信号通过电绝缘区域传播。第二转换器电路将已经通过绝缘电路传播的脉冲信号转换成原始状态信号或具有与原始状态信号相同特性的信号。

95. 发明授权

US07307313B2 Semiconductor device including a vertical field effect transistor, having trenches, and a diode 有权
标题翻译：包括具有沟槽的垂直场效应晶体管和二极管的半导体器件
公开(公告)号：US07307313B2
公开(公告)日：2007-12-11
申请号：US11206212
申请日：2005-08-18
申请人： Takasumi Ohyanagi , Atsuo Watanabe , Toshio Sakakibara , Tsuyoshi Yamamoto , Hiroki Nakamura , Rajesh Kumar Malhan
发明人： Takasumi Ohyanagi , Atsuo Watanabe , Toshio Sakakibara , Tsuyoshi Yamamoto , Hiroki Nakamura , Rajesh Kumar Malhan
IPC分类号： H01L29/76
CPC分类号： H01L29/1066 , H01L29/7722 , H01L29/8083
摘要： A semiconductor device includes (a) a vertical field effect transistor, the vertical field effect transistor including a drain electrode formed on a first surface of a first conductivity type of a semiconductor, a pair of first trenches formed from a second surface of the semiconductor, control regions of a second conductivity type formed respectively along the first trenches, a source region of the first conductivity type formed along the second surface of the semiconductor between the first trenches, a source electrode joined to the source region, and a gate electrode adjacent to the control regions, (b) a pair of second trenches formed from the second surface of the semiconductor independently of the field effect transistor, (c) control regions of the second conductivity type formed along the second trenches, and (d) a diode having a junction formed on the second surface between the second trenches.
摘要翻译：半导体器件包括（a）垂直场效应晶体管，垂直场效应晶体管包括形成在第一导电类型的半导体的第一表面上的漏电极，由半导体的第二表面形成的一对第一沟槽，沿着第一沟槽分别形成的第二导电类型的控制区域，沿着第一沟槽之间的半导体的第二表面形成的第一导电类型的源极区域，与源极区域连接的源极电极和与源极区域相邻的栅电极控制区域，（b）与场效应晶体管独立地由半导体的第二表面形成的一对第二沟槽，（c）沿着第二沟槽形成的第二导电类型的控制区，以及（d）二极管，在第二沟槽之间的第二表面上形成的结。

96. 发明授权

US07289553B2 Isolator and a modem device using the isolator 失效
公开(公告)号：US07289553B2
公开(公告)日：2007-10-30
申请号：US10377670
申请日：2003-03-04
申请人： Seigoh Yukutake , Yasuyuki Kojima , Minehiro Nemoto , Masatsugu Amishiro , Takayuki Iwasaki , Shinichiro Mitani , Katsuhiro Furukawa , Chiyoshi Kamada , Atsuo Watanabe , Takayuki Oouchi , Nobuyasu Kanekawa
发明人： Seigoh Yukutake , Yasuyuki Kojima , Minehiro Nemoto , Masatsugu Amishiro , Takayuki Iwasaki , Shinichiro Mitani , Katsuhiro Furukawa , Chiyoshi Kamada , Atsuo Watanabe , Takayuki Oouchi , Nobuyasu Kanekawa
IPC分类号： H04B1/38 , H01L29/00
CPC分类号： H04L25/0266 , H01L2924/0002 , H04L25/0268 , H04L25/0272 , H04L25/028 , H04L25/0292 , H04L27/0002 , H04M11/06 , H01L2924/00
摘要： A communication system is provided including a transceiver and an application controller to transmit and receive signals through the transceiver. An isolator which insulates and separates the transceiver and application controller includes primary and secondary side circuits insulated from each other on a substrate and a capacitive insulating means to transfer signals between the primary and second sides while insulating and separating the primary side circuit from the secondary side circuit.

97. 发明申请

US20070210408A1 DIELECTRIC MATERIAL SEPARATED-TYPE, HIGH BREAKDOWN VOLTAGE SEMICONDUCTOR CIRCUIT DEVICE, AND PRODUCTION METHOD THEREOF 有权
公开(公告)号：US20070210408A1
公开(公告)日：2007-09-13
申请号：US11684032
申请日：2007-03-09
申请人： Atsuo Watanabe , Mitsutoshi Honda , Norio Ishitsuka , Masahiro Ito , Toshihito Tabata , Shinichi Kurita , Hidekazu Kamioka
发明人： Atsuo Watanabe , Mitsutoshi Honda , Norio Ishitsuka , Masahiro Ito , Toshihito Tabata , Shinichi Kurita , Hidekazu Kamioka
IPC分类号： H01L29/00
CPC分类号： H01L21/76286 , H01L29/7394 , H01L29/7824
摘要： It is an object of the present invention to provide an integrated circuit device structured to uniformly apply a voltage to side oxide films formed in a trench at both sides in an SOI substrate.The semiconductor integrated circuit device of the present invention comprises a substrate which supports a first insulation layer below an active device region, trench formed in the active device region to come into contact with the first insulation layer, second insulation film formed on the trench side wall, polycrystalline silicon with which the trench is filled, and third insulation film formed on the polycrystalline silicon, wherein the thickness ratio of the third insulation film to the first insulation film is 0.25 or more to uniformly apply a voltage to the oxide insulation films formed in the trench at both sides.It is another object of the present invention to provide a dielectrically isolated semiconductor device of high reliability by realizing a fine and deep element isolating region which can prevent dislocation of an oxide film as an insulation layer by oxidation-induced stress. It is still another object to provide a process for fabrication of the above device.The dielectrically isolated semiconductor device of the present invention comprises a substrate supporting single-crystalline silicon via an oxide film (SOI substrate), the substrate supporting an active element layer deeper than an expanded distance of a depletion layer subjected to the highest voltage applied to the device, and element isolating region which encloses the active element layer. The element isolating region contains a deep trench which comes into contact with the insulation layer on the SOI substrate, and is filled with n heavily doped layers on both side walls, second insulation films each adjacent to the n heavily doped layer and polycrystalline semiconductor layer formed between the second insulation films.

98. 发明授权

US07256453B2 Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：US07256453B2
公开(公告)日：2007-08-14
申请号：US11038929
申请日：2005-01-18
申请人： Hidekatsu Onose , Atsuo Watanabe
发明人： Hidekatsu Onose , Atsuo Watanabe
IPC分类号： H01L29/76 , H01L29/94
CPC分类号： H01L29/1066 , H01L29/7722 , H01L29/808
摘要： A structure is provided that ensures a low on-resistance and a better blocking effect. In a lateral type SIT (Static Induction Transistor) in which a first region is used as a p+ gate and a gate electrode is formed on the bottom of the first region, the structure is built such that the p+ gate and an n+ source are contiguous. An insulating film is formed on the surface of an n− channel, and an auxiliary gate electrode is formed on the insulating film. In addition, the auxiliary gate electrode and the source electrode are shorted.
摘要翻译：提供了一种确保低导通电阻和更好的阻塞效果的结构。在其中第一区被用作栅极的横向型SIT（静态感应晶体管）中，并且栅极电极形成在第一区域的底部上，构造为使得p ^{+ 门和n ^{+ 源是连续的。在n通道的表面上形成绝缘膜，在绝缘膜上形成辅助栅电极。此外，辅助栅电极和源电极短路。}}

99. 发明申请

US20070096145A1 Switching semiconductor devices and fabrication process 审中-公开
标题翻译：开关半导体器件和制造工艺
公开(公告)号：US20070096145A1
公开(公告)日：2007-05-03
申请号：US11590789
申请日：2006-11-01
申请人： Atsuo Watanabe
发明人： Atsuo Watanabe
IPC分类号： H01L31/111
CPC分类号： H01L29/8083 , H01L29/0692 , H01L29/1608 , H01L29/2003 , H01L29/66909
摘要： A switching semiconductor device is provided, in which a negative gate voltage can be applied to the semiconductor device in an OFF state so as to increase a breakdown voltage of the gate junction without impairing a normally-off function of the semiconductor device and the ON-resistance. The switching semiconductor device is fabricated by using a semiconductor substrate with a band gap of 2.0 eV or more. In a JFET structure where a p+ type gate region and an n type source region are in contact so that a negative gate voltage can be applied, the p+ type gate region and an n+ type source region with a high impurity concentration are disposed with interposing an n type source region with an impurity concentration lower than that of the p+ type gate region and higher than that of a drift region of the JFET therebetween.
摘要翻译：提供了一种切换半导体器件，其中可以在OFF状态下对半导体器件施加负栅极电压，以便增加栅极结的击穿电压而不损害半导体器件的常关功能，抵抗性。通过使用带隙为2.0eV以上的半导体衬底来制造开关半导体器件。在其中ap + +型栅极区和n型源区接触的JFET结构中，使得可以施加负栅极电压，p + +型栅极区和以杂质浓度低于p + +型栅极区域的杂质浓度的n型源极区域设置具有高杂质浓度的n + 比它们之间的JFET的漂移区域的漂移区域更高。

100. 发明申请

US20050218424A1 Semiconductor device 审中-公开
标题翻译：半导体器件
公开(公告)号：US20050218424A1
公开(公告)日：2005-10-06
申请号：US11135417
申请日：2005-05-24
申请人： Hidekatsu Onose , Hideo Homma , Atsuo Watanabe
发明人： Hidekatsu Onose , Hideo Homma , Atsuo Watanabe
IPC分类号： H01L29/80 , H01L21/337 , H01L29/10 , H01L29/772 , H01L29/808 , H01L29/32
CPC分类号： H01L29/1066 , H01L29/1608 , H01L29/7722
摘要： A semiconductor switching device for an inverter includes a first conductivity type, low impurity concentration, semiconductor substrate having a band gap equal to or greater than 2.0 eV, a first conductivity type first region formed in a first plane of the substrate having a resistance lower than the substrate, a first electrode formed in another plane of the first region, a first conductivity type second region formed in a second plane of the substrate, and a second electrode formed on the second region. A trench is formed in the second plane, a control region is formed from a bottom of the trench into the substrate and a control electrode of a different conductivity type is formed on the control region. The second electrode is formed over the control electrode through an insulator film, and the control electrode is formed on the trench sidewalls so the control region contacts the second region.
摘要翻译：用于逆变器的半导体开关器件包括第一导电类型，低杂质浓度，具有等于或大于2.0eV的带隙的半导体衬底，形成在衬底的第一平面中的电阻低于所述基板，形成在所述第一区域的另一平面中的第一电极，形成在所述基板的第二平面中的第一导电类型的第二区域和形成在所述第二区域上的第二电极。在第二平面中形成沟槽，控制区域从沟槽的底部形成到衬底中，并且在控制区域上形成不同导电类型的控制电极。第二电极通过绝缘膜形成在控制电极上，并且控制电极形成在沟槽侧壁上，使得控制区域接触第二区域。

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