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91. 发明授权

US08593720B2 Electronic paper and method for producing same 有权
标题翻译：电子纸及其制造方法
公开(公告)号：US08593720B2
公开(公告)日：2013-11-26
申请号：US13383010
申请日：2011-04-14
申请人： Koichi Hirano , Masami Nakagawa , Seiichi Nakatani
发明人： Koichi Hirano , Masami Nakagawa , Seiichi Nakatani
IPC分类号： G02B26/00 , G09G3/34
CPC分类号： G09F9/372 , G02F1/167 , G02F2001/1676 , G02F2201/18 , G09F9/301 , G09F15/0075
摘要： Provided is an electronic paper that permits a high-quality, large area to be easily created. Also provided is a method for producing the electronic paper. The electronic paper comprises: a first substrate upon which first electrodes are formed and a second substrate upon which second electrodes are formed, said first substrate and second substrate disposed so as to face each other; and a plurality of cell spaces constituting pixels between said first substrate and second substrate. The first substrate comprises a plurality of first sheet members, each having a first electrode formed thereon. By disposing a cover substrate on said first sheet members, each with a partition wall therebetween, a plurality of subsheet formations comprising the plurality of cell spaces partitioned by the partition walls are formed, and the first electrodes are connected in between adjacent subsheet formations.
摘要翻译：提供了允许容易地创建高质量，大面积的电子纸。还提供了一种用于生产电子纸的方法。电子纸包括：形成有第一电极的第一基板和形成有第二电极的第二基板，所述第一基板和第二基板彼此相对配置; 以及在所述第一基板和第二基板之间构成像素的多个单元空间。第一衬底包括多个第一片构件，每个第一片构件具有形成在其上的第一电极。通过将覆盖基板设置在所述第一板状部件上，每个在其间具有隔壁，形成包括由隔壁分隔的多个电池单元的多个子片形成层，并且第一电极连接在相邻的子片层之间。

92. 发明申请

US20130168681A1 FLEXIBLE SEMICONDUCTOR DEVICE, METHOD FOR MANUFACTURING THE SAME, IMAGE DISPLAY DEVICE USING THE SAME AND METHOD FOR MANUFACTURING THE IMAGE DISPLAY DEVICE 有权
标题翻译：柔性半导体器件，其制造方法，使用其的图像显示器件以及用于制造图像显示器件的方法
公开(公告)号：US20130168681A1
公开(公告)日：2013-07-04
申请号：US13821352
申请日：2012-02-21
申请人： Takeshi Suzuki , Koichi Hirano , Shinobu Masuda
发明人： Takeshi Suzuki , Koichi Hirano , Shinobu Masuda
IPC分类号： H01L29/66 , H01L29/786
CPC分类号： H01L29/66765 , H01L21/0274 , H01L23/544 , H01L27/3262 , H01L29/78603 , H01L29/78669 , H01L29/78678 , H01L29/7869 , H01L2223/5442 , H01L2223/54426 , H01L2227/323 , H01L2251/5338 , H01L2924/0002 , H01L2924/00
摘要： There is provided a method for manufacturing a flexible semiconductor device. The method of the flexible semiconductor device according to the present invention comprises the steps of: (i) forming an insulating layer on one of principal surfaces of a metal foil; (ii) forming a semiconductor layer on the insulating layer, and then forming source and drain electrodes so that the source and drain electrodes contact with the semiconductor layer; (iii) forming a flexible film layer so that the flexible film layer covers the semiconductor layer and the source and drain electrodes; (iv) forming vias in the flexible film layer, and thereby a semiconductor device precursor is provided; and (v) subjecting the metal foil to a processing treatment, and thereby forming a gate electrode from the metal foil, wherein, in the step (v) of the processing treatment of the metal foil, the gate electrode is formed in a predetermined position by using at least one of the vias of the semiconductor device precursor as an alignment marker.
摘要翻译：提供了一种用于制造柔性半导体器件的方法。根据本发明的柔性半导体器件的方法包括以下步骤：（i）在金属箔的主表面之一上形成绝缘层; （ii）在所述绝缘层上形成半导体层，然后形成源电极和漏电极，使得所述源极和漏极与所述半导体层接触; （iii）形成柔性膜层，使得柔性膜层覆盖半导体层和源极和漏极; （iv）在柔性膜层中形成通孔，从而提供半导体器件前体; 和（v）对所述金属箔进行处理处理，从而从所述金属箔形成栅电极，其中在所述金属箔的所述加工处理的步骤（v）中，所述栅电极形成在预定位置通过使用半导体器件前体的至少一个通孔作为对准标记。

93. 发明授权

US08367488B2 Manufacturing method of flexible semiconductor device 有权
标题翻译：柔性半导体器件的制造方法
公开(公告)号：US08367488B2
公开(公告)日：2013-02-05
申请号：US13054049
申请日：2010-02-05
申请人： Takashi Ichiryu , Seiichi Nakatani , Koichi Hirano
发明人： Takashi Ichiryu , Seiichi Nakatani , Koichi Hirano
IPC分类号： H01L29/786 , H01L21/336
CPC分类号： H01L29/78603 , H01L27/1218 , H01L27/1266 , H01L29/458 , H01L29/4908 , H01L29/78681 , H01L29/7869 , H01L2224/24195 , H01L2224/32245 , H01L2224/73267 , H01L2224/82 , H01L2224/92244 , H01L2924/3511 , H01L2924/3512
摘要： A method includes the steps of preparing a multilayer film 80 formed by sequentially stacking a first metal layer 10, an inorganic insulating layer 20, a semiconductor layer 30, and a second metal layer 40; forming a source electrode 42s and a drain electrode 42d comprised of the second metal layer 40 by etching the second metal layer 40; pressure-bonding a resin layer 50 onto a surface of the multilayer film 80 provided with the source electrode 42s and the drain electrode 42d to burry the source electrode 42s and the drain electrode 42d in the resin layer 50; and forming a gate electrode 10g comprised of the first metal layer 10 by etching the first metal layer 10. The inorganic insulating layer 20g functions as a gate insulating film. The semiconductor layer 30 functions as a channel.
摘要翻译：一种方法包括制备通过顺序堆叠第一金属层10，无机绝缘层20，半导体层30和第二金属层40而形成的多层膜80的步骤; 通过蚀刻第二金属层40形成由第二金属层40构成的源电极42s和漏电极42d; 将树脂层50压接到设置有源电极42s和漏电极42d的多层膜80的表面，以将树脂层50中的源电极42s和漏电极42d嵌入; 以及通过蚀刻第一金属层10形成由第一金属层10构成的栅极电极10g。无机绝缘层20g用作栅极绝缘膜。半导体层30用作沟道。

94. 发明授权

US08063486B2 Circuit board, method for manufacturing the same, and semiconductor device 有权
标题翻译：电路基板及其制造方法以及半导体装置
公开(公告)号：US08063486B2
公开(公告)日：2011-11-22
申请号：US11748111
申请日：2007-05-14
申请人： Koichi Hirano , Tsukasa Shiraishi , Seiichi Nakatani , Tatsuo Ogawa
发明人： Koichi Hirano , Tsukasa Shiraishi , Seiichi Nakatani , Tatsuo Ogawa
IPC分类号： H01L23/48
CPC分类号： H05K1/0271 , H01L23/49811 , H01L24/12 , H01L24/16 , H01L24/81 , H01L2224/05568 , H01L2224/05573 , H01L2224/13011 , H01L2224/13099 , H01L2224/13111 , H01L2224/16 , H01L2224/81191 , H01L2224/81801 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01024 , H01L2924/01027 , H01L2924/01029 , H01L2924/0103 , H01L2924/01033 , H01L2924/01042 , H01L2924/01046 , H01L2924/01047 , H01L2924/01051 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/09701 , H01L2924/14 , H01L2924/15787 , H01L2924/351 , H05K1/09 , H05K1/111 , H05K3/243 , H05K2201/0338 , H05K2201/0355 , H05K2201/09109 , H01L2924/00 , H01L2224/05599
摘要： A circuit board 1 having a base material 10 and an electrode 11 formed on at least one main surface of the base material 10 includes an easy peeling portion 12 formed in at least one of an inner portion and a side portion of the electrode 11, with the adhesive strength between the electrode 11 and the easy peeling portion 12 being less than the adhesive strength between the electrode 11 and the base material 10. A circuit board that has high connection reliability and enables narrow pitch mounting thereby can be provided.
摘要翻译：具有基材10和形成在基材10的至少一个主表面上的电极11的电路板1包括形成在电极11的内部和侧部中的至少一个中的易剥离部分12，电极11和容易剥离部12之间的粘合强度小于电极11与基材10之间的粘合强度。可以提供具有高连接可靠性并能实现窄间距安装的电路板。

95. 发明授权

US07977741B2 Manufacturing method of flexible semiconductor device and flexible semiconductor device 有权
标题翻译：柔性半导体器件和柔性半导体器件的制造方法
公开(公告)号：US07977741B2
公开(公告)日：2011-07-12
申请号：US12939729
申请日：2010-11-04
申请人： Koichi Hirano , Seiichi Nakatani , Shingo Komatsu , Yoshihisa Yamashita , Takashi Ichiryu
发明人： Koichi Hirano , Seiichi Nakatani , Shingo Komatsu , Yoshihisa Yamashita , Takashi Ichiryu
IPC分类号： H01L29/786
CPC分类号： H01L51/0024 , H01L29/41733 , H01L29/66742 , H01L29/78603 , H01L51/0023 , H01L51/0097 , H01L51/0525 , H01L51/055 , H01L51/102 , Y10T428/24917
摘要： A layered film of a three-layer clad foil formed with a first metal layer 23, a second metal layer 25, and an inorganic insulating layer 35 interposed therebetween is prepared. After the second metal layer 25 is partially etched to form a gate electrode 20g, the first metal layer 23 is partially etched to form source/drain electrodes 20s, 20d in a region corresponding to the gate electrode 20g. A semiconductor layer 40 is then formed in contact with the source/drain electrodes 20s, 20d and on the gate electrode 20g with the inorganic insulating layer 35 interposed therebetween. The inorganic insulating layer 35 on the gate electrode 20g functions as a gate insulating film 30, and the semiconductor layer 40 between the source/drain electrodes 20s, 20d on the inorganic insulating layer 35 functions as a channel.
摘要翻译：制备形成有第一金属层23，第二金属层25和介于其间的无机绝缘层35的三层复合箔的分层膜。在第二金属层25被部分蚀刻以形成栅电极20g之后，第一金属层23被部分蚀刻以在对应于栅电极20g的区域中形成源/漏电极20s，20d。然后，将半导体层40形成为与源极/漏极20s，20d接触并且在栅极电极20g上形成有绝缘层35。栅电极20g上的无机绝缘层35用作栅极绝缘膜30，无机绝缘层35上的源/漏电极20s，20d之间的半导体层40用作沟道。

96. 发明申请

US20110133137A1 METAL PARTICLES-DISPERSED COMPOSITION AND FLIP CHIP MOUNTING PROCESS AND BUMP-FORMING PROCESS USING THE SAME 审中-公开
标题翻译：金属颗粒分散组合物和浮选芯片安装工艺和使用其的成型工艺
公开(公告)号：US20110133137A1
公开(公告)日：2011-06-09
申请号：US13027498
申请日：2011-02-15
申请人： Koichi Hirano , Seiji Karashima , Takashi Ichiryu , Yoshihiro Tomita
发明人： Koichi Hirano , Seiji Karashima , Takashi Ichiryu , Yoshihiro Tomita
IPC分类号： H01B1/22
CPC分类号： H01L24/81 , H01L21/6835 , H01L23/49883 , H01L24/11 , H01L24/12 , H01L24/16 , H01L2224/0554 , H01L2224/05568 , H01L2224/05573 , H01L2224/11003 , H01L2224/11005 , H01L2224/1141 , H01L2224/1152 , H01L2224/11524 , H01L2224/13099 , H01L2224/16 , H01L2224/293 , H01L2224/294 , H01L2224/73104 , H01L2224/83886 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01011 , H01L2924/01013 , H01L2924/01015 , H01L2924/01019 , H01L2924/01023 , H01L2924/01029 , H01L2924/0103 , H01L2924/01033 , H01L2924/01047 , H01L2924/0105 , H01L2924/01051 , H01L2924/01056 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/09701 , H01L2924/14 , H01L2924/15787 , H01L2924/15788 , H05K3/323 , H05K3/3484 , H05K2201/10977 , H05K2203/0425 , H05K2203/087 , H05K2203/1178 , H01L2924/00 , H01L2224/05599 , H01L2224/0555 , H01L2224/0556
摘要： A flip chip mounting process wherein a semiconductor chip and a circuit substrate are electrically interconnected. The process includes the steps of preparing a semiconductor chip on which a first plurality of electrodes are formed and a circuit substrate on which a second plurality of electrodes are formed; supplying a composition onto a surface of the circuit substrate, such surface being provided with second plurality of electrodes; bringing the semiconductor chip into contact with a surface of said composition such that the first plurality of electrodes are opposed to the second plurality of electrodes; and heating the circuit substrate, and thereby electrical connections including a metal component constituting the metal particles dispersed in the composition are formed between the first plurality of electrodes and the second plurality of electrodes. Also, a thermoset resin layer is formed between the semiconductor chip and the circuit substrate.
摘要翻译：一种倒装芯片安装工艺，其中半导体芯片和电路基板电连接。该方法包括制备其上形成有第一多个电极的半导体芯片和形成有第二多个电极的电路基板的步骤; 在电路基板的表面上提供组合物，该表面设置有第二多个电极; 使所述半导体芯片与所述组合物的表面接触，使得所述第一多个电极与所述第二多个电极相对; 并且加热电路基板，从而在第一多个电极和第二多个电极之间形成包括构成分散在组合物中的金属颗粒的金属组分的电连接。此外，在半导体芯片和电路基板之间形成热固性树脂层。

97. 发明授权

US07851281B2 Manufacturing method of flexible semiconductor device and flexible semiconductor device 有权
标题翻译：柔性半导体器件和柔性半导体器件的制造方法
公开(公告)号：US07851281B2
公开(公告)日：2010-12-14
申请号：US12518602
申请日：2008-10-01
申请人： Koichi Hirano , Seiichi Nakatani , Shingo Komatsu , Yoshihisa Yamashita , Takashi Ichiryu
发明人： Koichi Hirano , Seiichi Nakatani , Shingo Komatsu , Yoshihisa Yamashita , Takashi Ichiryu
IPC分类号： H01L21/336
CPC分类号： H01L51/0024 , H01L29/41733 , H01L29/66742 , H01L29/78603 , H01L51/0023 , H01L51/0097 , H01L51/0525 , H01L51/055 , H01L51/102 , Y10T428/24917
摘要： A layered film of a three-layer clad foil formed with a first metal layer 23, a second metal layer 25, and an inorganic insulating layer 35 interposed therebetween is prepared. After the second metal layer 25 is partially etched to form a gate electrode 20g, the first metal layer 23 is partially etched to form source/drain electrodes 20s, 20d in a region corresponding to the gate electrode 20g. A semiconductor layer 40 is then formed in contact with the source/drain electrodes 20s, 20d and on the gate electrode 20g with the inorganic insulating layer 35 interposed therebetween. The inorganic insulating layer 35 on the gate electrode 20g functions as a gate insulating film 30, and the semiconductor layer 40 between the source/drain electrodes 20s, 20d on the inorganic insulating layer 35 functions as a channel.
摘要翻译：制备形成有第一金属层23，第二金属层25和介于其间的无机绝缘层35的三层复合箔的分层膜。在第二金属层25被部分蚀刻以形成栅电极20g之后，第一金属层23被部分蚀刻以在对应于栅电极20g的区域中形成源/漏电极20s，20d。然后，将半导体层40形成为与源极/漏极20s，20d接触并且在栅极电极20g上形成有绝缘层35。栅电极20g上的无机绝缘层35用作栅极绝缘膜30，无机绝缘层35上的源/漏电极20s，20d之间的半导体层40用作沟道。

98. 发明申请

US20100283054A1 FLEXIBLE SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME 有权
标题翻译：柔性半导体器件及其制造方法
公开(公告)号：US20100283054A1
公开(公告)日：2010-11-11
申请号：US12681445
申请日：2009-07-30
申请人： Koichi Hirano , Seiichi Nakatani , Tatsuo Ogawa , Takashi Ichiryu , Takeshi Suzuki
发明人： Koichi Hirano , Seiichi Nakatani , Tatsuo Ogawa , Takashi Ichiryu , Takeshi Suzuki
IPC分类号： H01L29/786 , H01L21/336
CPC分类号： H01L29/78651 , H01L27/1218 , H01L27/124 , H01L27/1266 , H01L29/41733 , H01L29/42384 , H01L29/78603 , H01L29/7869
摘要： There is provided a method for manufacturing a flexible semiconductor device characterized by comprising (i) a step of forming an insulating film on the upper surface of metal foil, (ii) a step of forming an extraction electrode pattern on the upper surface of the metal foil, (iii) a step of forming a semiconductor layer on the insulating film in such a manner that the semiconductor layer is in contact with the extraction electrode pattern, (iv) a step of forming a sealing resin layer on the upper surface of the metal foil in such a manner that the sealing resin layer covers the semiconductor layer and the extraction electrode pattern, and (v) a step of forming electrodes by etching the metal foil, wherein the metal foil is used as a support for the insulating film, the extraction electrode pattern, the semiconductor layer, and the sealing resin layer formed in (i) to (iv) and used as a constituent material for the electrodes in (v). A TFT element can be fabricated by a simple process because the metal foil serving as the support need not be finally stripped off. Further, a high-temperature process can be introduced to the fabrication of the insulating film and the semiconductor layer because the metal foil is used as the support, whereby the TFT characteristic is improved.
摘要翻译：提供了一种制造柔性半导体器件的方法，其特征在于包括：（i）在金属箔的上表面上形成绝缘膜的步骤，（ii）在金属的上表面上形成引出电极图案的步骤箔，（iii）以半导体层与引出电极图案接触的方式在绝缘膜上形成半导体层的步骤，（iv）在所述绝缘膜的上表面上形成密封树脂层的步骤金属箔以密封树脂层覆盖半导体层和引出电极图案，以及（v）通过蚀刻金属箔形成电极的步骤，其中金属箔用作绝缘膜的支撑体，（i）〜（iv）中形成的并用作（v）中的电极的构成材料的引出电极图案，半导体层和密封树脂层。由于作为支撑体的金属箔不需要最终被剥离，所以可以通过简单的工艺制造TFT元件。此外，由于使用金属箔作为支撑体，因此可以将绝缘膜和半导体层的制造引入高温处理，从而提高TFT特性。

99. 发明授权

US07754529B2 Flip chip mounting body and method for mounting such flip chip mounting body and bump forming method 有权
标题翻译：倒装芯片安装体和安装这种倒装芯片安装体和凸块成型方法
公开(公告)号：US07754529B2
公开(公告)日：2010-07-13
申请号：US11814337
申请日：2006-02-02
申请人： Yoshihiro Tomita , Koichi Hirano , Seiji Karashima , Takashi Ichiryu , Toshio Fujii
发明人： Yoshihiro Tomita , Koichi Hirano , Seiji Karashima , Takashi Ichiryu , Toshio Fujii
IPC分类号： H01L21/00
CPC分类号： H05K3/3436 , H01L21/565 , H01L21/6835 , H01L24/11 , H01L24/742 , H01L24/83 , H01L2224/05568 , H01L2224/05573 , H01L2224/11003 , H01L2224/11005 , H01L2224/1152 , H01L2224/13099 , H01L2224/16238 , H01L2224/83205 , H01L2224/83801 , H01L2224/83886 , H01L2924/00014 , H01L2924/01006 , H01L2924/01009 , H01L2924/01012 , H01L2924/01019 , H01L2924/01029 , H01L2924/01032 , H01L2924/01033 , H01L2924/01047 , H01L2924/0105 , H01L2924/01078 , H01L2924/01082 , H01L2924/01327 , H01L2924/014 , H01L2924/14 , H01L2924/30105 , H05K3/323 , H05K3/3484 , H05K2201/10977 , H05K2203/0285 , Y02P70/613 , H01L2224/05599
摘要： In a flip chip mounted body in which a semiconductor chip (20) having a plurality of electrode terminals (21) is disposed so as to be opposed to a wiring board (10) having a plurality of connection terminals (11), with the connection terminals (11) and the electrode terminals (21) being connected electrically, a resin (13) containing electrically conductive particles (12) is supplied between the connection terminals (11) and the electrode terminals (21), the electrically conductive particles (12) and the resin (13) are heated and melted, and vibrations are applied so as to make them flow. The molten electrically conductive particles (12) are allowed to self-assemble between the connection terminals (11) and the electrode terminals (21), thereby forming connectors (22) that connect them electrically. It becomes more likely that the molten electrically conductive particles in the resin contact the connection terminals or the electrode terminals, whereby the molten electrically conductive particles self-assemble between the electrode terminals and the connection terminals that have a high wettability, making it possible to form connectors for establishing an electric connection between these terminals in a uniform manner.
摘要翻译：在其中具有多个电极端子（21）的半导体芯片（20）设置成与具有多个连接端子（11）的布线板（10）相对的倒装芯片安装体中，连接端子（11）和电极端子（21）电连接，在连接端子（11）和电极端子（21）之间提供包含导电颗粒（12）的树脂（13），导电颗粒（12））和树脂（13）被加热和熔化，并且施加振动以使其流动。允许熔融的导电颗粒（12）在连接端子（11）和电极端子（21）之间自组装，从而形成将它们电连接的连接器（22）。树脂中的熔融的导电性粒子更可能接触连接端子或电极端子，由此熔融的导电性粒子在电极端子和具有高润湿性的连接端子之间自组装，从而形成用于以均匀的方式在这些端子之间建立电连接的连接器。

100. 发明申请

US20100012936A1 MANUFACTURING METHOD OF FLEXIBLE SEMICONDUCTOR DEVICE AND FLEXIBLE SEMICONDUCTOR DEVICE 有权
标题翻译：柔性半导体器件和柔性半导体器件的制造方法
公开(公告)号：US20100012936A1
公开(公告)日：2010-01-21
申请号：US12518602
申请日：2008-10-01
申请人： Koichi Hirano , Seiichi Nakatani , Shingo Komatsu , Yoshihisa Yamashita , Takashi Ichiryu
发明人： Koichi Hirano , Seiichi Nakatani , Shingo Komatsu , Yoshihisa Yamashita , Takashi Ichiryu
IPC分类号： H01L29/786 , H01L21/336 , H01L21/8234 , B32B3/02
CPC分类号： H01L51/0024 , H01L29/41733 , H01L29/66742 , H01L29/78603 , H01L51/0023 , H01L51/0097 , H01L51/0525 , H01L51/055 , H01L51/102 , Y10T428/24917
摘要： A layered film of a three-layer clad foil formed with a first metal layer 23, a second metal layer 25, and an inorganic insulating layer 35 interposed therebetween is prepared. After the second metal layer 25 is partially etched to form a gate electrode 20g, the first metal layer 23 is partially etched to form source/drain electrodes 20s, 20d in a region corresponding to the gate electrode 20g. A semiconductor layer 40 is then formed in contact with the source/drain electrodes 20s, 20d and on the gate electrode 20g with the inorganic insulating layer 35 interposed therebetween. The inorganic insulating layer 35 on the gate electrode 20g functions as a gate insulating film 30, and the semiconductor layer 40 between the source/drain electrodes 20s, 20d on the inorganic insulating layer 35 functions as a channel.
摘要翻译：制备形成有第一金属层23，第二金属层25和介于其间的无机绝缘层35的三层复合箔的分层膜。在第二金属层25被部分蚀刻以形成栅电极20g之后，第一金属层23被部分蚀刻以在对应于栅电极20g的区域中形成源/漏电极20s，20d。然后，将半导体层40形成为与源极/漏极20s，20d接触并且在栅极电极20g上形成有绝缘层35。栅电极20g上的无机绝缘层35用作栅极绝缘膜30，无机绝缘层35上的源/漏电极20s，20d之间的半导体层40用作沟道。

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