专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

91. 发明申请

US20100270683A1 Semiconductor device and method of manufacturing semiconductor device 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US20100270683A1
公开(公告)日：2010-10-28
申请号：US12662335
申请日：2010-04-12
申请人： Tatsuya Usami
发明人： Tatsuya Usami
IPC分类号： H01L23/48 , H01L21/768
CPC分类号： H01L21/7682 , H01L21/76834 , H01L21/76885 , H01L2924/0002 , H01L2924/00
摘要： An interconnect is provided in a first insulating layer and the upper surface of the interconnect is higher than the upper surface of the first insulating layer. An air gap is disposed between the interconnect and the first insulating layer. An etching stopper film is formed over the first insulating layer, the air gap, and the interconnect. A second insulating layer is formed over the etching stopper film. A via is provided in the second insulating layer and is connected to the interconnect. A portion of the etching stopper film that is disposed over the air gap is thicker than another portion that is disposed over the interconnect.
摘要翻译：在第一绝缘层中提供互连，并且互连的上表面高于第一绝缘层的上表面。在互连和第一绝缘层之间设置气隙。在第一绝缘层，气隙和互连件之上形成蚀刻阻挡膜。在蚀刻停止膜上形成第二绝缘层。通孔设置在第二绝缘层中并连接到互连。设置在气隙上的蚀刻阻挡膜的一部分比设置在互连上的另一部分厚。

92. 发明申请

US20080070400A1 Semiconductor device and manufacturing method thereof 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US20080070400A1
公开(公告)日：2008-03-20
申请号：US11892923
申请日：2007-08-28
申请人： Tatsuya Usami
发明人： Tatsuya Usami
IPC分类号： H01L21/283 , H01L21/318
CPC分类号： H01L21/0337 , H01L21/3185 , H01L21/76898 , H01L23/147 , H01L23/49827 , H01L2224/05573 , H01L2224/16 , H01L2924/00014 , H01L2924/13091 , H01L2924/00 , H01L2224/05599
摘要： When forming a silicon nitride film to protect and insulate a surface on which a silicon substrate has been ground or polishing, by use of a mixed gas containing SiH4, N2, and NH3 as a reaction gas, a film is formed by a single-frequency parallel-plate plasma CVD method. Thereby, even when the film forming temperature is made not more than an allowable temperature limit of an adhesive to adhere a support (for example, approximately 100° C. or less, which is an allowable temperature limit when the adhesive is an ultraviolet curing resin), a high-quality film without exfoliation in a CMP step of the following step and with less leakage can be formed. This high-quality film is, if being prescribed by a refractive index, a film whose refractive index with respect to a wavelength of 633 nm is approximately 1.8 through 1.9.
摘要翻译：当形成氮化硅膜以保护和绝缘其上已经研磨或抛光硅衬底的表面时，通过使用含有SiH 4 N 2 N 2的混合气体，和NH 3作为反应气体，通过单频平行板等离子体CVD法形成膜。因此，即使当成膜温度不大于粘合剂的粘合剂的允许温度极限时（例如约100℃或更低，这是当粘合剂是紫外线固化树脂时的允许温度极限）），可以形成在后续步骤的CMP步骤中没有剥离并且具有较少泄漏的高质量膜。如果由折射率规定，则该高品质膜的折射率相对于633nm的折射率为1.8〜1.9左右。

93. 发明授权

US07291911B2 Semiconductor device and manufacturing method thereof 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US07291911B2
公开(公告)日：2007-11-06
申请号：US11047576
申请日：2005-02-02
申请人： Tatsuya Usami
发明人： Tatsuya Usami
IPC分类号： H01L23/48
CPC分类号： H01L21/0337 , H01L21/3185 , H01L21/76898 , H01L23/147 , H01L23/49827 , H01L2224/05573 , H01L2224/16 , H01L2924/00014 , H01L2924/13091 , H01L2924/00 , H01L2224/05599
摘要： When forming a silicon nitride film to protect and insulate a surface on which a silicon substrate has been ground or polishing, by use of a mixed gas containing SiH4, N2, and NH3 as a reaction gas, a film is formed by a single-frequency parallel-plate plasma CVD method. Thereby, even when the film forming temperature is made not more than an allowable temperature limit of an adhesive to adhere a support (for example, approximately 100° C. or less, which is an allowable temperature limit when the adhesive is an ultraviolet curing resin), a high-quality film without exfoliation in a CMP step of the following step and with less leakage can be formed. This high-quality film is, if being prescribed by a refractive index, a film whose refractive index with respect to a wavelength of 633 nm is approximately 1.8 through 1.9.
摘要翻译：当形成氮化硅膜以保护和绝缘其上已经研磨或抛光硅衬底的表面时，通过使用含有SiH 4 N 2 N 2的混合气体，和NH 3作为反应气体，通过单频平行板等离子体CVD法形成膜。因此，即使当成膜温度不大于粘合剂的粘合剂的允许温度极限时（例如约100℃或更低，这是当粘合剂是紫外线固化树脂时的允许温度极限）），可以形成在后续步骤的CMP步骤中没有剥离并且具有较少泄漏的高质量膜。如果由折射率规定，则该高品质膜的折射率相对于633nm的折射率为1.8〜1.9左右。

94. 发明授权

US07230337B2 Semiconductor device including ladder-shaped siloxane hydride and method for manufacturing same 有权
标题翻译：包括梯形硅氢化硅氢化物的半导体器件及其制造方法
公开(公告)号：US07230337B2
公开(公告)日：2007-06-12
申请号：US10760554
申请日：2004-01-21
申请人： Tatsuya Usami , Takashi Ishigami , Tetsuya Kurokawa , Noriaki Oda
发明人： Tatsuya Usami , Takashi Ishigami , Tetsuya Kurokawa , Noriaki Oda
IPC分类号： H01L23/48 , H01L23/29 , H01L23/28 , H01L23/52 , H01L23/532
CPC分类号： H01L23/53295 , H01L21/76829 , H01L21/76832 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： The present invention reduces the effective dielectric constant of the interlayer insulating film while inhibiting the decrease of the reliability of the semiconductor device, which otherwise is caused by a moisture absorption. A copper interconnect comprising a Cu film 209 is formed in multilayer films comprising a L-Ox™ film 203 and a SiO2 film 204. Since the L-Ox™ film 203 comprises ladder-shaped siloxane hydride structure, the film thickness and the film characteristics are stable, and thus changes in the film quality is scarcely occurred during the manufacturing process.
摘要翻译：本发明降低了层间绝缘膜的有效介电常数，同时抑制了由吸湿引起的半导体器件的可靠性的降低。包括Cu膜209的铜互连形成在包括L-Ox TM膜203和SiO 2膜204的多层膜中。由于L-Ox TM膜203包括梯形硅氢化合物结构，所以膜厚度和膜特性是稳定的，因此在制造过程中几乎不发生膜质量的变化。

95. 发明授权

US07229910B2 Method of producing a semiconductor device having a multi-layered insulation film 有权
标题翻译：制造具有多层绝缘膜的半导体器件的方法
公开(公告)号：US07229910B2
公开(公告)日：2007-06-12
申请号：US10135393
申请日：2002-05-01
申请人： Tatsuya Usami
发明人： Tatsuya Usami
IPC分类号： H01L21/4763
CPC分类号： H01L21/76897 , H01L21/02134 , H01L21/02137 , H01L21/02164 , H01L21/022 , H01L21/02274 , H01L21/02282 , H01L21/3122 , H01L21/3124 , H01L21/76801 , H01L21/76828 , H01L21/76829 , H01L21/76832 , H01L21/76835 , H01L23/5329 , H01L2924/0002 , H01L2924/12044 , H01L2924/00
摘要： The object of the present invention is to improve the interfacial adhesion between the film with low dielectric constant and protective film, without damaging the excellent dielectric, flatness and gap-filling characteristics of the organic material of low dielectric constant, and for that purpose there is provided a wiring structure with the copper film embedded in the insulation film of the wiring layer, wherein the insulation film of the wiring layer is of a multi-layered structure with the laminated methyl silisesquioxane (MSQ) film, methylated hydrogen silisesquioxane (MHSQ) film and silicon oxide film.
摘要翻译：本发明的目的是提高具有低介电常数的膜和保护膜之间的界面粘合性，而不损害低介电常数有机材料的优异的电介质，平坦度和间隙填充特性，并且为此目的提供了布线结构，其中铜膜嵌入在布线层的绝缘膜中，其中布线层的绝缘膜具有层叠的甲基silisquioxane（MSQ）膜，甲基化氢硅烷倍半硅氧烷（MHSQ）膜的多层结构和氧化硅膜。

96. 发明授权

US07217654B2 Semiconductor device and method of manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US07217654B2
公开(公告)日：2007-05-15
申请号：US10969429
申请日：2004-10-21
申请人： Seiji Nagahara , Kazutoshi Shiba , Nobuaki Hamanaka , Tatsuya Usami , Takashi Yokoyama
发明人： Seiji Nagahara , Kazutoshi Shiba , Nobuaki Hamanaka , Tatsuya Usami , Takashi Yokoyama
IPC分类号： H01L21/4763
CPC分类号： H01L21/02063 , H01L21/31116 , H01L21/31138 , H01L21/76807 , H01L21/76808 , H01L21/76811 , H01L21/76825 , H01L21/76828 , H01L21/76831
摘要： A method of manufacturing a semiconductor device having a damascene structure contains a process of forming a first interlayer insulating film (6) and a second interlayer insulating film (4) formed of a low dielectric-constant film on a substrate, forming via holes (9) by using a first resist pattern (1a) formed on the second interlayer insulating film, conducting an organic peeling treatment using organic peeling liquid containing amine components and then forming a second resist pattern (1b) on the second interlayer insulating film. After the wet treatment, before a second antireflection coating (2b) is coated so as to be located below the second resist pattern is coated, at least one of an annealing treatment, a plasma treatment, a UV treatment and an organic solvent treatment is carried out to remove amine components which inhibit the catalysis reaction of acid occurring in the resist at the light exposure, thereby preventing degradation of the resolution of the second resist pattern (1b).
摘要翻译：一种制造具有镶嵌结构的半导体器件的方法包括在衬底上形成第一层间绝缘膜（6）和由低介电常数膜形成的第二层间绝缘膜（4）的工艺，形成通孔（9 ）通过使用形成在第二层间绝缘膜上的第一抗蚀剂图案（1a），使用含有胺成分的有机剥离液进行有机剥离处理，然后在第二层间绝缘膜上形成第二抗蚀剂图案（1b）。在湿处理之后，涂覆第二抗反射涂层（2b）以便位于第二抗蚀图案下方的涂层，退火处理，等离子体处理，UV处理和有机溶剂处理中的至少一个是进行以除去抑制在曝光时在抗蚀剂中发生的酸的催化反应的胺成分，从而防止第二抗蚀剂图案（1b）的分辨率的劣化。

97. 发明申请

US20070096331A1 Semiconductor device and method of manufacturing the same 审中-公开
标题翻译：半导体装置及其制造方法
公开(公告)号：US20070096331A1
公开(公告)日：2007-05-03
申请号：US11640349
申请日：2006-12-18
申请人： Seiji Nagahara , Kazutoshi Shiba , Nobuaki Hamanaka , Tatsuya Usami , Takashi Yokoyama
发明人： Seiji Nagahara , Kazutoshi Shiba , Nobuaki Hamanaka , Tatsuya Usami , Takashi Yokoyama
IPC分类号： H01L23/48
CPC分类号： H01L21/02063 , H01L21/31116 , H01L21/31138 , H01L21/76807 , H01L21/76808 , H01L21/76811 , H01L21/76825 , H01L21/76828 , H01L21/76831
摘要： A method of manufacturing a semiconductor device having a damascene structure contains a process of forming a first interlayer insulating film and a second interlayer insulating film formed of a low dielectric constant film on a substrate, forming via holes by using a first resist pattern formed on the second interlayer insulating film, conducting an organic peeling treatment using organic peeling liquid containing amine components and then forming a second resist pattern on the second interlayer insulating film. After the wet treatment before a second antireflection coating is coated so as to be located below the second resist pattern is coated, at least one of an annealing treatment, a plasma treatment, a UV treatment and an organic solvent treatment is carried out to remove amine components which inhibit the catalysis reaction of acid occurring in the resist at the light exposure, thereby preventing degradation of the resolution of the second resist pattern.
摘要翻译：一种制造具有镶嵌结构的半导体器件的方法包括在基板上形成第一层间绝缘膜和由低介电常数膜形成的第二层间绝缘膜的工艺，通过使用形成在第一层上绝缘膜上的第一抗蚀剂图案形成通孔第二层间绝缘膜，使用含有胺成分的有机剥离液进行有机剥离处理，然后在第二层间绝缘膜上形成第二抗蚀剂图案。在第二抗反射涂层涂布第二抗蚀剂图案之下的湿处理之后，涂覆第二抗蚀图案，进行退火处理，等离子体处理，UV处理和有机溶剂处理中的至少一种以除去胺抑制在曝光时在抗蚀剂中发生的酸的催化反应的成分，从而防止第二抗蚀剂图案的分辨率的劣化。

98. 发明申请

US20070013069A1 Wiring structure and method for manufacturing the same 有权
标题翻译：接线结构及其制造方法
公开(公告)号：US20070013069A1
公开(公告)日：2007-01-18
申请号：US10558367
申请日：2004-05-28
申请人： Munehiro Tada , Yoshihiro Hayashi , Yoshimichi Harada , Fuminori Ito , Hiroto Ohtake , Tatsuya Usami
发明人： Munehiro Tada , Yoshihiro Hayashi , Yoshimichi Harada , Fuminori Ito , Hiroto Ohtake , Tatsuya Usami
IPC分类号： H01L23/52 , H01L23/48 , H01L29/40
CPC分类号： H01L23/53295 , H01L21/76802 , H01L21/76807 , H01L21/76831 , H01L21/76832 , H01L21/76835 , H01L23/53238 , H01L23/5329 , H01L2924/0002 , H01L2924/00
摘要： A multilayer wiring structure for connecting a semiconductor device is disclosed which is obtained by forming metal wirings on a substrate in which the semiconductor device is formed. The wiring structure free from such conventional problems that insulation between wirings next to each other is damaged or insulation resistance between wirings next to each other is deteriorated by generation of leakage current when fine metal wirings are formed in a porous insulating film. A method for producing such a wiring structure is also disclosed. In the metal wiring structure on the substrate in which the semiconductor device is formed, a insulating barrier layer (413) containing an organic matter is formed between an interlayer insulating film and a metal wiring. This insulating barrier layer reduces leakage current between wirings next to each other, thereby improving insulation reliability.
摘要翻译：公开了一种用于连接半导体器件的多层布线结构，其通过在其中形成半导体器件的基板上形成金属布线而获得。布线结构没有这样的常规问题，即在多孔绝缘膜中形成细金属布线时，通过产生漏电流而使彼此相邻的布线之间的绝缘损坏或彼此相邻的布线之间的绝缘电阻恶化。还公开了一种用于制造这种布线结构的方法。在形成了半导体器件的基板上的金属布线结构中，在层间绝缘膜和金属布线之间形成含有有机物质的绝缘阻挡层（413）。该绝缘阻挡层减少彼此相邻的布线之间的漏电流，从而提高绝缘可靠性。

99. 发明申请

US20060255466A1 Carbon containing silicon oxide film having high ashing tolerance and adhesion 失效
公开(公告)号：US20060255466A1
公开(公告)日：2006-11-16
申请号：US11477011
申请日：2006-06-28
申请人： Sadayuki Ohnishi , Kouichi Ohto , Tatsuya Usami , Noboru Morita , Kouji Arita , Ryouhei Kitao , Youichi Sasaki
发明人： Sadayuki Ohnishi , Kouichi Ohto , Tatsuya Usami , Noboru Morita , Kouji Arita , Ryouhei Kitao , Youichi Sasaki
IPC分类号： H01L23/52
CPC分类号： H01L21/02126 , C23C16/401 , H01L21/02137 , H01L21/02211 , H01L21/02274 , H01L21/02282 , H01L21/02304 , H01L21/02362 , H01L21/3122 , H01L21/31633 , H01L21/76801 , H01L2924/0002 , H01L2924/00
摘要： An insulating film used for an interlayer insulating film of a semiconductor device and having a low dielectric constant. The insulating film comprises a carbon containing silicon oxide (SiOCH) film which has Si—CH2 bond therein. The proportion of Si—CH2 bond (1360 cm−1) to Si—CH3 bond (1270 cm−1) in the insulating film is preferably in a range from 0.03 to 0.05 measured as a peak height ratio of FTIR spectrum. The insulating film according to the present invention has higher ashing tolerance and improved adhesion to SiO2 film, when compared with the conventional SiOCH film which only has CH3 group.

100. 发明申请

US20060216946A1 Method of fabricating a semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US20060216946A1
公开(公告)日：2006-09-28
申请号：US11156735
申请日：2005-06-21
申请人： Tatsuya Usami , Sadayuki Ohnishi , Masayuki Hiroi , Akira Matsumoto
发明人： Tatsuya Usami , Sadayuki Ohnishi , Masayuki Hiroi , Akira Matsumoto
IPC分类号： H01L21/473
CPC分类号： H01L21/31144 , H01L21/02164 , H01L21/02271 , H01L21/02274 , H01L21/31612
摘要： An intermediate film 222 in a three-layered resist film 225 is formed by the chemical vapor deposition process at a temperature not higher than 300° C., using Si(OR1)(OR2)(OR3)(OR4) , where each of R1, R2, R3 and R4 independently represents a carbon-containing group or a hydrogen atom, excluding the case where all of R1 to R4 are hydrogen atoms.
摘要翻译：在三层抗蚀剂膜225中的中间膜222通过化学气相沉积工艺在不高于300℃的温度下，使用Si（OR 2）（OR 2）（OR 3）（OR 4），其中R 1，R 2，R 2， R 3和R 4独立地代表含碳基团或氢原子，不包括所有R 1至R“ SUB> 4 是氢原子。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式