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91. 发明申请

US20090001441A1 Three dimensional quantum dot array 审中-公开
标题翻译：三维量子点阵列
公开(公告)号：US20090001441A1
公开(公告)日：2009-01-01
申请号：US11823758
申请日：2007-06-28
申请人： Been-Yih Jin , Brian S. Doyle , Jack T. Kavalieros , Robert S. Chau
发明人： Been-Yih Jin , Brian S. Doyle , Jack T. Kavalieros , Robert S. Chau
IPC分类号： H01L21/336 , H01L29/788
CPC分类号： H01L29/127 , B82Y10/00 , H01L21/8221 , H01L27/0688 , H01L27/115 , H01L27/11517 , H01L29/40114 , H01L29/42332
摘要： In one embodiment of the invention, oxidation of silicon in a silicon germanium/silicon lattice may convert a two dimensional array of silicon germanium pillars into a structured three dimensional quantum dot array. The array may be included in, for example, flash memory floating gate, optical detector, or quantum computing device.
摘要翻译：在本发明的一个实施例中，硅锗/硅晶格中的硅的氧化可以将硅锗柱的二维阵列转换成结构化的三维量子点阵列。阵列可以包括在例如闪存浮动栅极，光学检测器或量子计算设备中。

92. 发明授权

US07402856B2 Non-planar microelectronic device having isolation element to mitigate fringe effects and method to fabricate same 有权
标题翻译：具有隔离元件以减轻边缘效应的非平面微电子器件及其制造方法
公开(公告)号：US07402856B2
公开(公告)日：2008-07-22
申请号：US11299102
申请日：2005-12-09
申请人： Justin K. Brask , Jack T. Kavalieros , Brian S. Doyle , Robert S. Chau
发明人： Justin K. Brask , Jack T. Kavalieros , Brian S. Doyle , Robert S. Chau
IPC分类号： H01L29/94
CPC分类号： H01L29/7851 , H01L29/66795
摘要： A non-planar microelectronic device, a method of fabricating the device, and a system including the device. The non-planar microelectronic device comprises: a substrate body including a substrate base and a fin, the fin defining a device portion at a top region thereof; a gate dielectric layer extending at a predetermined height on two laterally opposing sidewalls of the fin, the predetermined height corresponding to a height of the device portion; a device isolation layer on the substrate body and having a thickness up to a lower limit of the device portion; a gate electrode on the device isolation layer and further extending on the gate dielectric layer; an isolation element extending on the two laterally opposing sidewalls of the fin up to a lower limit of the gate dielectric layer, the isolation element being adapted to reduce any fringe capacitance between the gate electrode and regions of the fin extending below the device portion.
摘要翻译：非平面微电子器件，制造器件的方法以及包括该器件的系统。所述非平面微电子器件包括：衬底主体，其包括衬底基座和鳍片，所述鳍片限定其顶部区域处的器件部分; 栅极电介质层，其在所述鳍片的两个横向相对的侧壁上以预定高度延伸，所述预定高度对应于所述器件部分的高度; 在所述衬底主体上的器件隔离层，并且具有至所述器件部分的下限的厚度; 器件隔离层上的栅电极，并进一步在栅介质层上延伸; 隔离元件，其在所述鳍片的两个横向相对的侧壁上延伸到所述栅极电介质层的下限，所述隔离元件适于减小所述栅电极与所述鳍片延伸到所述器件部分下方的区域之间的任何条纹电容。

93. 发明授权

US07354832B2 Tri-gate device with conformal PVD workfunction metal on its three-dimensional body and fabrication method thereof 有权
标题翻译：具有保形PVD功能金属的三栅极器件及其制造方法
公开(公告)号：US07354832B2
公开(公告)日：2008-04-08
申请号：US11418295
申请日：2006-05-03
申请人： Willy Rachmady , Brian S. Doyle , Jack T. Kavalieros , Uday Shah
发明人： Willy Rachmady , Brian S. Doyle , Jack T. Kavalieros , Uday Shah
IPC分类号： H01L21/336
CPC分类号： H01L29/78 , H01L29/4908 , H01L29/66795 , H01L29/785
摘要： A method of fabricating a tri-gate semiconductor device comprising a semiconductor body having an upper surface and side surfaces and a metal gate that has an approximately equal thickness on the upper and side surfaces. Embodiments of a tri-gate device with conformal physical vapor deposition workfunction metal on its three-dimensional body are described herein. Other embodiments may be described and claimed.
摘要翻译：一种制造三栅极半导体器件的方法，包括具有上表面和侧表面的半导体本体和在上表面和侧表面上具有大致相同厚度的金属栅极。本文描述了具有保形物理气相沉积功能金属的三栅极器件在其三维体上的实施例。可以描述和要求保护其他实施例。

94. 发明申请

US20080073723A1 Selective anisotropic wet etching of workfunction metal for semiconductor devices 失效
标题翻译：半导体器件功能金属的选择性各向异性湿蚀刻
公开(公告)号：US20080073723A1
公开(公告)日：2008-03-27
申请号：US11525765
申请日：2006-09-22
申请人： Willy Rachmady , Uday Shah , Jack T. Kavalieros , Brian S. Doyle
发明人： Willy Rachmady , Uday Shah , Jack T. Kavalieros , Brian S. Doyle
IPC分类号： H01L29/78 , H01L21/8234
CPC分类号： H01L21/823842 , H01L21/823821 , H01L27/092 , H01L27/0924 , H01L29/66795 , H01L29/785
摘要： Embodiments of an apparatus and methods for providing a workfunction metal gate electrode on a substrate with doped metal oxide semiconductor structures are generally described herein. Other embodiments may be described and claimed.
摘要翻译：在此通常描述用于在具有掺杂金属氧化物半导体结构的衬底上提供功函数金属栅电极的装置和方法的实施例。可以描述和要求保护其他实施例。

95. 发明授权

US06953719B2 Integrating n-type and p-type metal gate transistors 有权
公开(公告)号：US06953719B2
公开(公告)日：2005-10-11
申请号：US10851360
申请日：2004-05-20
申请人： Mark Doczy , Justin K. Brask , Steven J. Keating , Chris E. Barns , Brian S. Doyle , Michael L. McSwiney , Jack T. Kavalieros , John P. Barnak
发明人： Mark Doczy , Justin K. Brask , Steven J. Keating , Chris E. Barns , Brian S. Doyle , Michael L. McSwiney , Jack T. Kavalieros , John P. Barnak
IPC分类号： H01L21/3213 , H01L21/336 , H01L21/8238 , H01L29/49 , H01L29/78 , H01L21/3205 , H01L21/4763
CPC分类号： H01L29/66545 , H01L21/32134 , H01L21/32137 , H01L21/823842 , H01L29/495 , H01L29/4966 , H01L29/7833 , Y10S438/926
摘要： At least a p-type and n-type semiconductor device deposited upon a semiconductor wafer containing metal or metal alloy gates. More particularly, a complementary metal-oxide-semiconductor (CMOS) device is formed on a semiconductor wafer having n-type and p-type metal gates.

96. 发明授权

US08030163B2 Reducing external resistance of a multi-gate device using spacer processing techniques 有权
标题翻译：使用间隔物处理技术降低多栅极器件的外部电阻
公开(公告)号：US08030163B2
公开(公告)日：2011-10-04
申请号：US11964593
申请日：2007-12-26
申请人： Ravi Pillarisetty , Uday Shah , Brian S. Doyle , Jack T. Kavalieros
发明人： Ravi Pillarisetty , Uday Shah , Brian S. Doyle , Jack T. Kavalieros
IPC分类号： H01L21/336
CPC分类号： H01L29/66795 , H01L29/66545 , H01L29/785
摘要： A method includes depositing a sacrificial gate electrode to one or more multi-gate fins. The sacrificial gate electrode is patterned such that it is coupled to a gate region and substantially no sacrificial gate electrode is coupled to source and drain regions. A dielectric film is formed that is coupled to the source and drain regions. The sacrificial gate electrode is removed and a spacer gate dielectric is deposited to the gate region wherein substantially no spacer gate dielectric is deposited to the source and drain regions. The spacer gate dielectric is etched to completely remove the spacer gate dielectric from the gate region area that is to be coupled with a final gate electrode except a remaining pre-determined thickness of spacer gate dielectric that is to be coupled with the final gate electrode that remains coupled with the dielectric film.
摘要翻译：一种方法包括将牺牲栅电极沉积到一个或多个多栅极散热片上。牺牲栅电极被图案化，使得它被耦合到栅极区域，并且基本上没有牺牲栅极电极耦合到源极和漏极区域。形成了与源极和漏极区域耦合的电介质膜。牺牲栅极电极被去除，并且间隔栅极电介质沉积到栅极区域，其中基本上没有间隔栅极电介质沉积到源区和漏极区。蚀刻间隔栅极电介质以完全去除要与最终栅电极耦合的栅极区域的间隔栅极电介质，除了与最终栅电极耦合的间隔栅极电介质的剩余预定厚度之外，保持与电介质膜耦合。

97. 发明授权

US07821061B2 Silicon germanium and germanium multigate and nanowire structures for logic and multilevel memory applications 有权
标题翻译：用于逻辑和多级存储器应用的硅锗和锗多重和纳米线结构
公开(公告)号：US07821061B2
公开(公告)日：2010-10-26
申请号：US11729565
申请日：2007-03-29
申请人： Been-Yih Jin , Brian S. Doyle , Jack T. Kavalieros , Robert S. Chau
发明人： Been-Yih Jin , Brian S. Doyle , Jack T. Kavalieros , Robert S. Chau
IPC分类号： H01L21/00
CPC分类号： H01L21/02381 , B82Y10/00 , H01L21/02164 , H01L21/02236 , H01L21/0245 , H01L21/02507 , H01L21/02532 , H01L21/02603 , H01L21/30604 , H01L21/31658 , H01L21/76283 , H01L21/823807 , H01L29/0665 , H01L29/0673 , H01L29/0676 , H01L29/068 , H01L29/1054 , H01L29/165 , H01L29/42324 , H01L29/42392 , H01L29/66439 , H01L29/66795 , H01L29/66818 , H01L29/775 , H01L29/785 , H01L29/78696
摘要： A method to provide a transistor or memory cell structure. The method comprises: providing a substrate including a lower Si substrate and an insulating layer on the substrate; providing a first projection extending above the insulating layer, the first projection including an Si material and a Si1-xGex material; and exposing the first projection to preferential oxidation to yield a second projection including a center region comprising Ge/Si1-yGey and a covering region comprising SiO2 and enclosing the center region.
摘要翻译：一种提供晶体管或存储单元结构的方法。该方法包括：在衬底上提供包括下Si衬底和绝缘层的衬底; 提供在所述绝缘层上方延伸的第一突起，所述第一突起包括Si材料和Si1-xGex材料; 以及将所述第一突起暴露于优先氧化以产生包括包含Ge / Si1-yGey的中心区域和包含SiO 2并包围所述中心区域的覆盖区域的第二突起。

98. 发明授权

US07521775B2 Protection of three dimensional transistor structures during gate stack etch 有权
标题翻译：在栅堆叠蚀刻期间保护三维晶体管结构
公开(公告)号：US07521775B2
公开(公告)日：2009-04-21
申请号：US11452883
申请日：2006-06-13
申请人： Brian S. Doyle , Uday Shah , Been-Yih Jin , Jack T. Kavalieros
发明人： Brian S. Doyle , Uday Shah , Been-Yih Jin , Jack T. Kavalieros
IPC分类号： H01L29/06
CPC分类号： H01L29/7851 , H01L29/66795
摘要： Embodiments of the invention include apparatuses and methods relating to three dimensional transistors having high-k dielectrics and metal gates with fins protected by a hard mask layer on their top surface. In one embodiment, the hard mask layer includes an oxide.
摘要翻译：本发明的实施例包括与具有高k电介质的三维晶体管和金属栅极相关的装置和方法，其翅片由其顶表面上的硬掩模层保护。在一个实施例中，硬掩模层包括氧化物。

99. 发明授权

US07485536B2 Abrupt junction formation by atomic layer epitaxy of in situ delta doped dopant diffusion barriers 有权
标题翻译：通过原子层外延原位δ掺杂掺杂剂扩散阻挡层的突变结形成
公开(公告)号：US07485536B2
公开(公告)日：2009-02-03
申请号：US11326178
申请日：2005-12-30
申请人： Been-Yih Jin , Brian S. Doyle , Robert S. Chau , Jack T. Kavalieros
发明人： Been-Yih Jin , Brian S. Doyle , Robert S. Chau , Jack T. Kavalieros
IPC分类号： H01L21/335
CPC分类号： H01L29/0847 , H01L21/823807 , H01L21/823814 , H01L21/823878 , H01L29/165 , H01L29/66636 , H01L29/66795 , H01L29/7851
摘要： A method including forming a channel region between source and drain regions in a substrate, the channel region including a first dopant profile; and forming a barrier layer between the channel region and a well of the substrate, the barrier layer including a second dopant profile different from the first dopant profile. An apparatus including a gate electrode on a substrate; source and drain regions formed in the substrate and separated by a channel region; and a barrier layer between a well of the substrate and the channel region, the barrier layer including a dopant profile different than a dopant profile of the channel region and different than a dopant profile of the well. A system including a computing device including a microprocessor, the microprocessor including a plurality of transistor devices formed in a substrate, each of the plurality of transistor devices including a gate electrode on the substrate; source and drain regions formed in the substrate and separated by a channel region; and a barrier layer between a well of the substrate and the channel region.
摘要翻译：一种方法，包括在衬底中的源区和漏区之间形成沟道区，所述沟道区包括第一掺杂物分布; 以及在所述沟道区和所述衬底的阱之间形成阻挡层，所述阻挡层包括不同于所述第一掺杂剂分布的第二掺杂剂分布。一种在基板上包括栅电极的装置; 源极和漏极区域形成在衬底中并被沟道区域分离; 以及在衬底的阱和沟道区之间的阻挡层，阻挡层包括不同于沟道区的掺杂物分布并且不同于阱的掺杂剂分布的掺杂剂分布。一种包括包括微处理器的计算设备的系统，所述微处理器包括形成在衬底中的多个晶体管器件，所述多个晶体管器件中的每一个在所述衬底上包括栅电极; 源极和漏极区域形成在衬底中并被沟道区域分离; 以及衬底的阱和沟道区之间的阻挡层。

100. 发明申请

US20090004868A1 Amorphous silicon oxidation patterning 审中-公开
标题翻译：非晶硅氧化图案化
公开(公告)号：US20090004868A1
公开(公告)日：2009-01-01
申请号：US11824489
申请日：2007-06-29
申请人： Brian S. Doyle , Uday Shah , Jack T. Kavalieros
发明人： Brian S. Doyle , Uday Shah , Jack T. Kavalieros
IPC分类号： H01L21/311
CPC分类号： H01L21/3086 , H01L27/10861 , H01L28/90
摘要： In one embodiment, a method comprises forming a sacrificial amorphous silicon layer on a semiconductor substrate, forming a hardmask on the amorphous silicon layer, etching one or more lines in the sacrificial amorphous silicon layer, growing oxide structures on the amorphous silicon layer, and forming a trench in the semiconductor substrate between the oxide structures.
摘要翻译：在一个实施例中，一种方法包括在半导体衬底上形成牺牲非晶硅层，在非晶硅层上形成硬掩模，蚀刻牺牲非晶硅层中的一条或多条线，在非晶硅层上生长氧化物结构，以及形成氧化物结构之间的半导体衬底中的沟槽。

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