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91. 发明申请

US20140229741A1 Dual Composite Field Advanced Encryption Standard Memory Encryption Engine 审中-公开
标题翻译：双复合现场高级加密标准内存加密引擎
公开(公告)号：US20140229741A1
公开(公告)日：2014-08-14
申请号：US13993545
申请日：2011-12-30
申请人： Sanu K. Mathew , Shay Gueron , Ram K. Krishnamurthy
发明人： Sanu K. Mathew , Shay Gueron , Ram K. Krishnamurthy
IPC分类号： G06F21/72 , G06F21/60
CPC分类号： G06F21/72 , G06F21/60 , H04L9/0631 , H04L2209/122
摘要： A different set of polynomials may be selected for encryption and decryption accelerators. That is, different sets of polynomials are used for encryption and decryption, each set being chosen to use less area and deliver more power for a memory encryption engine. This is advantageous in some embodiments since memory read operations are typically more critical and latency sensitive than memory writes.
摘要翻译：可以为加密和解密加速器选择不同的多项式集合。也就是说，不同的多项式组用于加密和解密，每组被选择为使用较少的区域并为存储器加密引擎提供更多的功率。这在一些实施例中是有利的，因为存储器读取操作通常比存储器写入更为关键和延迟敏感。

92. 发明申请

US20140208435A1 SOFTWARE MODIFICATION FOR PARTIAL SECURE MEMORY PROCESSING 有权
标题翻译：用于部分安全存储处理的软件修改
公开(公告)号：US20140208435A1
公开(公告)日：2014-07-24
申请号：US13994411
申请日：2011-12-29
申请人： Moshe Maor , Shay Gueron
发明人： Moshe Maor , Shay Gueron
IPC分类号： G06F21/12
CPC分类号： G06F21/12 , G06F21/00 , G06F21/53 , G06F2221/2107 , H04W4/50 , H04W4/60
摘要： This disclosure is directed to software modification that may be used to prevent software piracy and prevent unauthorized modification of applications. In some embodiments, a software vendor may modify software prior to distribution to a user. The software vendor may extract cutouts from an application to create a modified application. The modified application and the cutouts may be downloaded by a user device. The user device may run the application using the modified application and by executing the cutouts in a secure execution environment that conceals the underlying code in the cutouts.
摘要翻译：本公开涉及可用于防止软件盗版并防止未授权修改应用的软件修改。在一些实施例中，软件供应商可以在分配给用户之前修改软件。软件供应商可以从应用程序中提取剪切以创建修改的应用程序。修改的应用程序和切口可以由用户设备下载。用户设备可以使用经修改的应用程序来运行应用程序，并且通过在隐藏在切口中的底层代码的安全执行环境中执行切口来运行该应用程序。

93. 发明授权

US08689078B2 Determining a message residue 有权
标题翻译：确定消息残差
公开(公告)号：US08689078B2
公开(公告)日：2014-04-01
申请号：US11777538
申请日：2007-07-13
申请人： Shay Gueron , Vinodh Gopal , Wajdi K. Feghali , Gilbert M. Wolrich
发明人： Shay Gueron , Vinodh Gopal , Wajdi K. Feghali , Gilbert M. Wolrich
IPC分类号： H03M13/00
CPC分类号： H03M13/091
摘要： A technique of determining a message residue includes accessing a message and simultaneously determining a set of modular remainders with respect to a polynomial for different respective segments of the message. The technique also includes determining a modular remainder with respect to the polynomial for the message based on the set of modular remainders and a set of constants determined prior to accessing the message. The modular remainder with respect to the polynomial for the message is stored in a memory.
摘要翻译：确定消息残差的技术包括访问消息并且同时确定关于消息的不同相应段的多项式的一组模块余数。该技术还包括基于模块余数的集合和在访问消息之前确定的一组常数来确定关于消息的多项式的模块余数。相对于消息的多项式的模数余数存储在存储器中。

94. 发明申请

US20130297664A1 NUMBER SQUARING COMPUTER-IMPLEMENTED METHOD AND APPARATUS 有权
标题翻译：数字平方计算机实现方法和装置
公开(公告)号：US20130297664A1
公开(公告)日：2013-11-07
申请号：US13996512
申请日：2011-09-06
申请人： Shay Gueron , Vlad Krasnov
发明人： Shay Gueron , Vlad Krasnov
IPC分类号： G06F5/01
CPC分类号： G06F5/01 , G06F7/552 , G06F2207/5523 , H04L9/302 , H04L2209/12 , H04L2209/80
摘要： Embodiments of the present disclosure describe computer-implemented methods, computer-readable media and computer system associated with big number squaring. A computer-implemented method to square a number x may include storing a t-digit vector representation of x in t b-bit registers of a processor. A 2t-digit intermediate vector may be generated and stored in 2t b-bit registers of the processor, using x stored in said t b-bit registers. A value stored in at least one of the t b-bit or 2t b-bit registers may be shifted to the left by n. n may be an integer at least equal to 1. At some point after the shifting, w, square of the number x, may be represented by the 2t-digit result vector stored in the 2t b-bit registers. Other embodiments may be described and/or claimed.
摘要翻译：本公开的实施例描述了与大数字平方相关联的计算机实现的方法，计算机可读介质和计算机系统。对数字x进行平方的计算机实现的方法可以包括将x的t位矢量表示存储在处理器的tb位寄存器中。可以使用存储在所述t b位寄存器中的x来生成2位数字中间向量并将其存储在处理器的2tb位寄存器中。存储在tb位或2tb位寄存器中的至少一个的值可以向左移位n。 n可以是至少等于1的整数。在移位之后的某个点，数字x的w，可以由存储在2t b位寄存器中的2t数字结果向量表示。可以描述和/或要求保护其他实施例。

95. 发明授权

US08538015B2 Flexible architecture and instruction for advanced encryption standard (AES) 有权
标题翻译：高级加密标准（AES）的灵活架构和指令
公开(公告)号：US08538015B2
公开(公告)日：2013-09-17
申请号：US11729199
申请日：2007-03-28
申请人： Shay Gueron , Wajdi K. Feghali , Vinodh Gopal , Makaram Raghunandan , Martin G. Dixon , Srinivas Chennupaty , Michael E. Kounavis
发明人： Shay Gueron , Wajdi K. Feghali , Vinodh Gopal , Makaram Raghunandan , Martin G. Dixon , Srinivas Chennupaty , Michael E. Kounavis
IPC分类号： G06F21/00
CPC分类号： H04L9/0631 , G06F3/0623 , G06F3/0665 , G06F3/0689 , G06F9/30007 , G06F9/30036 , G06F9/30047 , G06F9/30145 , G06F9/30178 , G06F9/3802 , G06F9/3818 , G06F9/3887 , G06F9/3895 , G06F12/0862 , G06F12/0875 , G06F12/1408 , G06F21/602 , G06F2212/1052 , G06F2212/402 , G06F2212/452 , G06F2212/454 , G06F2212/602 , G11C7/1072 , H04L9/0816 , H04L9/0861 , H04L2209/12 , H04L2209/24
摘要： A flexible instruction set for a general purpose processor is provided. The instruction set includes instructions to perform a “one round” pass for encryption or decryption and also includes instructions to perform key generation. An immediate may be used to indicate round number and key size for key generation for 128/192/256 bit keys. The flexible instruction set enables full use of pipelining capabilities because it does not require tracking of implicit registers.
摘要翻译：提供了一种用于通用处理器的灵活指令集。指令集包括执行用于加密或解密的“一轮”通行的指令，还包括执行密钥生成的指令。立即可以用于指示128/192/256位键的密钥生成的循环数和密钥大小。灵活的指令集可以充分利用流水线功能，因为它不需要跟踪隐式寄存器。

96. 发明申请

US20130202106A1 Performing AES Encryption Or Decryption In Multiple Modes With A Single Instruction 审中-公开
标题翻译：使用单个指令执行多种模式的AES加密或解密
公开(公告)号：US20130202106A1
公开(公告)日：2013-08-08
申请号：US13790748
申请日：2013-03-08
申请人： Martin Dixon , Srinivas Chennupaty , Shay Gueron
发明人： Martin Dixon , Srinivas Chennupaty , Shay Gueron
IPC分类号： H04L9/28
CPC分类号： H04L9/0631 , G06F9/30007 , H04L9/0637 , H04L9/28 , H04L2209/12
摘要： A machine-readable medium may have stored thereon an instruction, which when executed by a machine causes the machine to perform a method. The method may include combining a first operand of the instruction and a second operand of the instruction to produce a result. The result may be encrypted using a key in accordance with an Advanced Encryption Standard (AES) algorithm to produce an encrypted result. The method may also include placing the encrypted result in a location of the first operand of the instruction.
摘要翻译：机器可读介质可以在其上存储有指令，当由机器执行时，该指令使机器执行方法。该方法可以包括组合指令的第一操作数和指令的第二操作数以产生结果。可以使用根据高级加密标准（AES）算法的密钥来加密结果以产生加密结果。该方法还可以包括将加密结果放置在指令的第一操作数的位置。

97. 发明授权

US08464125B2 Instruction-set architecture for programmable cyclic redundancy check (CRC) computations 有权
标题翻译：用于可编程循环冗余校验（CRC）计算的指令集架构
公开(公告)号：US08464125B2
公开(公告)日：2013-06-11
申请号：US12653249
申请日：2009-12-10
申请人： Vinodh Gopal , Shay Gueron , Gilbert M. Wolrich , Wajdi K. Feghali , Kirk S. Yap , Bradley A. Burres
发明人： Vinodh Gopal , Shay Gueron , Gilbert M. Wolrich , Wajdi K. Feghali , Kirk S. Yap , Bradley A. Burres
IPC分类号： H03M13/00
CPC分类号： G06F9/30145 , G06F9/30018 , G06F11/1004 , H03M13/09 , H03M13/091
摘要： A method and apparatus to perform Cyclic Redundancy Check (CRC) operations on a data block using a plurality of different n-bit polynomials is provided. A flexible CRC instruction performs a CRC operation using a programmable n-bit polynomial. The n-bit polynomial is provided to the CRC instruction by storing the n-bit polynomial in one of two operands.
摘要翻译：提供了使用多个不同的n位多项式对数据块执行循环冗余校验（CRC）操作的方法和装置。灵活的CRC指令使用可编程的n位多项式来执行CRC操作。通过将n位多项式存储在两个操作数之一中，将n位多项式提供给CRC指令。

98. 发明授权

US08340280B2 Using a single instruction multiple data (SIMD) instruction to speed up galois counter mode (GCM) computations 有权
标题翻译：使用单指令多数据（SIMD）指令来加速伽罗瓦计数器模式（GCM）计算
公开(公告)号：US08340280B2
公开(公告)日：2012-12-25
申请号：US12157961
申请日：2008-06-13
申请人： Shay Gueron , Michael Kounavis
发明人： Shay Gueron , Michael Kounavis
IPC分类号： H04L29/06
CPC分类号： H04L9/0643 , H04L9/0637 , H04L2209/046 , H04L2209/12 , H04L2209/38
摘要： In one embodiment, an encryption operation may be performed by obtaining a product of a carry-less multiplication using multiple single instruction multiple data (SIMD) multiplication instructions each to execute on part of first and second operands responsive to an immediate datum associated with the corresponding instruction, and reducing the product modulo g to form a message authentication code of a block cipher mode. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，可以通过使用多个单指令多数据（SIMD）乘法指令获得无进位乘法的乘积来执行加密操作，每个指令在第一和第二操作数的一部分上响应于与相应的指令，并减少产品模数g以形成分组密码模式的消息认证码。描述和要求保护其他实施例。

99. 发明授权

US08209689B2 Live lock free priority scheme for memory transactions in transactional memory 有权
标题翻译：事务内存中的内存事务的实时锁定优先级方案
公开(公告)号：US08209689B2
公开(公告)日：2012-06-26
申请号：US11854175
申请日：2007-09-12
申请人： Shlomo Raikin , Shay Gueron , Gad Sheaffer
发明人： Shlomo Raikin , Shay Gueron , Gad Sheaffer
IPC分类号： G06F9/52 , G06F13/14 , G06F12/00 , G06F7/00 , G06F13/00
CPC分类号： G06F9/524 , G06F9/466
摘要： A method and apparatus for avoiding live-lock during transaction execution is herein described. Counting logic is utilized to track successfully committed transactions for each processing element. When a data conflict is detected between transactions on multiple processing elements, priority is provided to the processing element with the lower counting logic value. Furthermore, if the values are the same, then the processing element with the lower identification value is given priority, i.e. allowed to continue while the other transaction is aborted. To avoid live-lock between processing elements that both have predetermined counting logic values, such as maximum counting values, when one processing element reaches the predetermined counting value all counters are reset. In addition, a failure at maximum value (FMV) counter may be provided to count a number of aborts of a transaction when counting logic is at a maximum value. When the FMV counter is at a predetermined number of aborts the counting logic is reset to avoid live lock.
摘要翻译：这里描述了用于在事务执行期间避免实时锁定的方法和装置。计数逻辑用于跟踪每个处理元素的成功提交事务。当在多个处理元件之间的事务之间检测到数据冲突时，以较低的计数逻辑值提供给处理元件的优先级。此外，如果值相同，则具有较低识别值的处理元件被赋予优先级，即允许在其他事务被中止时继续。为了避免在具有预定的计数逻辑值（例如最大计数值）的处理元件之间的实时锁定，当一个处理元件达到预定计数值时，所有计数器都被重置。此外，当计数逻辑处于最大值时，可以提供在最大值（FMV）计数器上的故障来计数事务的中止次数。当FMV计数器处于预定数量的中止时，计数逻辑被复位以避免实时锁定。

100. 发明授权

US08209542B2 Methods and apparatus for authenticating components of processing systems 有权
标题翻译：用于认证处理系统组件的方法和装置
公开(公告)号：US08209542B2
公开(公告)日：2012-06-26
申请号：US11648511
申请日：2006-12-29
申请人： Mohan J. Kumar , Shay Gueron
发明人： Mohan J. Kumar , Shay Gueron
IPC分类号： G06F21/00
CPC分类号： G06F21/57 , G06F21/575 , G06F2221/2129
摘要： When a processing system boots, it may retrieve an encrypted version of a cryptographic key from nonvolatile memory to a processing unit, which may decrypt the cryptographic key. The processing system may also retrieve a predetermined authentication code for software of the processing system, and the processing system may use the cryptographic key to compute a current authentication code for the software. The processing system may then determine whether the software should be trusted, by comparing the predetermined authentication code with the current authentication code. In various embodiments, the processing unit may use a key stored in nonvolatile storage of the processing unit to decrypt the encrypted version of the cryptographic key, a hashed message authentication code (HMAC) may be used as the authentication code, and/or the software to be authenticated may be boot firmware, a virtual machine monitor (VMM), or other software. Other embodiments are described and claimed.
摘要翻译：当处理系统引导时，它可以从非易失性存储器检索加密密钥的加密版本到处理单元，该处理单元可以解密密码密钥。处理系统还可以检索用于处理系统的软件的预定认证码，并且处理系统可以使用密码密钥来计算软件的当前认证码。然后，处理系统可以通过将预定认证码与当前认证码进行比较来确定软件是否应该被信任。在各种实施例中，处理单元可以使用存储在处理单元的非易失性存储器中的密钥对加密密钥的加密版本进行解密，散列消息认证码（HMAC）可以用作认证码，和/或软件被认证可以是启动固件，虚拟机监视器（VMM）或其他软件。描述和要求保护其他实施例。

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