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91. 发明授权

US06352914B2 Interleaved signal trace routing 有权
标题翻译：交错信号跟踪路由
公开(公告)号：US06352914B2
公开(公告)日：2002-03-05
申请号：US09805872
申请日：2001-03-14
申请人： Zane A. Ball , Aviram Gutman , Lawrence T. Clark
发明人： Zane A. Ball , Aviram Gutman , Lawrence T. Clark
IPC分类号： H01L2144
CPC分类号： H01L23/49822 , H01L2224/16225 , H05K1/0219 , H05K1/0298 , H05K2201/09236 , H05K2201/09672
摘要： A multi-layer electronic device package includes first and second outer layers and at least one signal layer disposed between the outer layers. The signal layer includes signal traces and ground traces interleaved with the signal traces. A method of routing signal traces in an electronic device package includes the acts of disposing a plurality of signal traces in at least one substrate layer, and interleaving a plurality of ground traces with the signal traces.
摘要翻译：多层电子器件封装包括第一和第二外层以及设置在外层之间的至少一个信号层。信号层包括与信号迹线交错的信号迹线和接地迹线。在电子器件封装中路由信号迹线的方法包括在至少一个衬底层中设置多个信号迹线以及用信号迹线交织多个接地迹线的动作。

92. 发明授权

US06282139B1 Register file with improved noise immunity and aspect ratio 有权
标题翻译：注册文件具有改进的抗干扰性和宽高比
公开(公告)号：US06282139B1
公开(公告)日：2001-08-28
申请号：US09444538
申请日：1999-11-22
申请人： Lawrence T. Clark , E. J. N. Tsangaris
发明人： Lawrence T. Clark , E. J. N. Tsangaris
IPC分类号： G11C800
CPC分类号： G11C8/10
摘要： A register file with a plurality of memory cells arranged such that a single word line enable signal path is coupled to word pairs formed from the memory cells, and a logic circuit which is configured to enable separate access of each word of the word pairs.
摘要翻译：具有多个存储单元的寄存器文件，其被布置成使得单个字线使能信号路径被耦合到由所述存储单元形成的字对;以及逻辑电路，其被配置为使得单词对中的每个单词的单独访问。

93. 发明授权

US6166985A Integrated circuit low leakage power circuitry for use with an advanced CMOS process 有权
标题翻译：集成电路低泄漏电源电路，用于先进的CMOS工艺
公开(公告)号：US6166985A
公开(公告)日：2000-12-26
申请号：US302729
申请日：1999-04-30
申请人： Bart R. McDaniel , Lawrence T. Clark
发明人： Bart R. McDaniel , Lawrence T. Clark
IPC分类号： G11C11/407 , G11C11/412 , G11C11/413 , G11C11/417 , G11C11/418 , H03K19/00 , H03K19/0948 , G11C8/00
CPC分类号： H03K19/0016 , G11C11/412 , G11C11/417 , G11C11/418
摘要： In one embodiment, the present invention provides a circuit that includes a core circuit and a control circuit coupled to the core circuit. The control circuit reduces a leakage current in the core circuit when the core circuit is in a Sleep mode. The control circuit maintains a logic state of the core circuit when the core circuit is in a Drowsy mode.
摘要翻译：在一个实施例中，本发明提供一种包括核心电路和耦合到核心电路的控制电路的电路。当核心电路处于睡眠模式时，控制电路减小了核心电路中的漏电流。当核心电路处于睡眠模式时，控制电路保持核心电路的逻辑状态。

94. 发明授权

US6118482A Method and apparatus for electrical test of CMOS pixel sensor arrays 失效
标题翻译： CMOS像素传感器阵列的电气测试方法和装置
公开(公告)号：US6118482A
公开(公告)日：2000-09-12
申请号：US986499
申请日：1997-12-08
申请人： Lawrence T. Clark , Mark A. Beiley , Eric J. Hoffman
发明人： Lawrence T. Clark , Mark A. Beiley , Eric J. Hoffman
IPC分类号： H04N5/367 , H04N17/00 , H04N5/335
CPC分类号： H04N5/367 , H04N17/002
摘要： CMOS pixel sensors have been of interest as replacements for CCD's in imaging applications. Such devices promise lower power and simpler system level design through fewer power supply voltages and higher functional integration. It is difficult and cost ineffective to utilize images to test active pixel sensors. Here, a method and apparatus for electrical testing of CMOS pixel sensors is described which involves electrically writing a pattern into the CMOS pixel sensors for the detection of adjacent cell shorts or stuck at faults as well as verification of read-channel circuit functionality and performance. The invention provides for an electrical testing of CMOS pixel array that is simple, time efficient and cost effective for use in, for example, production.
摘要翻译：作为CCD成像应用中的替代品，CMOS像素传感器已经成为关注的焦点。这样的器件通过更少的电源电压和更高的功能集成来承诺更低的功率和更简单的系统级设计。利用图像测试有源像素传感器是困难和成本无效的。这里描述了用于CMOS像素传感器的电测试的方法和装置，其涉及将图案电学写入CMOS像素传感器，用于检测相邻单元短路或卡在故障以及读通道电路功能和性能的验证。本发明提供了CMOS像素阵列的电气测试，其简单，时间高效并且在例如生产中使用成本有效。

95. 发明授权

US5859450A Dark current reducing guard ring 失效
标题翻译：暗电流降低护环
公开(公告)号：US5859450A
公开(公告)日：1999-01-12
申请号：US941800
申请日：1997-09-30
申请人： Lawrence T. Clark , Mark A. Beiley
发明人： Lawrence T. Clark , Mark A. Beiley
IPC分类号： H01L27/14 , H01L27/146 , H01L31/062 , H01L31/10 , H01L31/113 , H01L27/148
CPC分类号： H01L31/113 , H01L27/1463 , H01L27/14643
摘要： A photodiode is provided. The photodiode includes an insulative region (IR) that permits passage of light therethrough. The photodiode also includes a substrate region of a first conductivity type and a well region of a second conductivity type. The well is formed within the substrate, beneath the IR. The well is demarcated from the substrate by a first surface. The photodiode further includes a heavily doped region (HDR) of the second conductivity type. The HDR is formed within the IR at a first position. The first surface meets the HDR at substantially the first position.
摘要翻译：提供光电二极管。光电二极管包括允许光通过其中的绝缘区域（IR）。光电二极管还包括第一导电类型的衬底区域和第二导电类型的阱区域。在衬底内形成阱，在IR之下。孔通过第一表面与基底划分。光电二极管还包括第二导电类型的重掺杂区域（HDR）。 HDR在第一位置的IR内形成。第一个表面在大体上的第一个位置与HDR相遇。

96. 发明授权

US5271040A Phase detector circuit 失效
标题翻译：相位检测电路
公开(公告)号：US5271040A
公开(公告)日：1993-12-14
申请号：US811092
申请日：1991-12-20
申请人： Lawrence T. Clark
发明人： Lawrence T. Clark
IPC分类号： H03D13/00 , H03L7/089 , H03D3/18
CPC分类号： H03L7/0891 , H03D13/002
摘要： A digital phase detector circuit is designed for particular application with a phase-locked loop voltage controlled oscillator system for synchronizing the MFM synchronization pulses on a floppy disk with the operation of the computer in which the disk is used. A classical Type 4 digital phase detector is employed, to which a bistable latch is added. The latch is set upon coincidence of reference and data pulses applied to the phase detector within a pre-established time interval or window. The output of the phase detector then is utilized only when the output of the latch indicates such coincidence; so that erroneous control signals are not supplied through the loop whenever data pulses fail to occur in adjacent time frames or windows.
摘要翻译：数字相位检测器电路设计用于具有用于使软盘上的MFM同步脉冲与其中使用盘的计算机的操作同步的锁相环压控振荡器系统的特定应用。采用经典的4型数字相位检测器，加入双稳态锁存器。在预先建立的时间间隔或窗口内，基准和数据脉冲一同被施加到相位检测器上设置锁存器。然后相位检测器的输出仅在锁存器的输出指示这样的重合时才被使用; 使得当相邻时间帧或窗口中的数据脉冲不能发生时，不通过循环提供错误的控制信号。

97. 发明授权

US09467144B2 Radiation hardened digital circuit 有权
标题翻译：辐射硬化数字电路
公开(公告)号：US09467144B2
公开(公告)日：2016-10-11
申请号：US14808348
申请日：2015-07-24
申请人： Lawrence T. Clark
发明人： Lawrence T. Clark
IPC分类号： H03K3/00 , H03K19/003 , H03K19/007
CPC分类号： H03K19/0033 , H03K19/0075
摘要： This disclosure relates generally to radiation hardened digital circuits. In one embodiment, a radiation hardened digital circuit includes a delay network and a first Muller C element. The delay network is configured to generate a first delayed clock signal from a global clock signal such that that the first delayed clock signal is delayed with respect to the global clock signal. The first Muller C element is configured to generate a first clock input signal and set the first clock input signal to one of a set of clock states in response to the first delayed clock signal and the global clock signal each being provided in a same one of the set of clock states and is configured to hold the first clock input signal otherwise. Thus, a radiation strike is prevented from causing a soft error in the first clock input signal.
摘要翻译：本公开一般涉及辐射硬化的数字电路。在一个实施例中，辐射硬化的数字电路包括延迟网络和第一Muller C元件。延迟网络被配置为从全局时钟信号产生第一延迟时钟信号，使得第一延迟时钟信号相对于全局时钟信号被延迟。第一Muller C元件被配置为产生第一时钟输入信号，并且响应于第一延迟时钟信号和全局时钟信号将第一时钟输入信号设置为一组时钟状态中的一个，每个时钟信号分别以一组时钟状态，并被配置为保持第一个时钟输入信号。因此，防止辐射打击在第一时钟输入信号中引起软错误。

98. 发明申请

US20150349775A1 Radiation Hardened By Design Digital Input/Output Circuits And Related Methods 有权
标题翻译：通过设计实现的辐射数字输入/输出电路及相关方法
公开(公告)号：US20150349775A1
公开(公告)日：2015-12-03
申请号：US12776188
申请日：2010-05-07
申请人： Lawrence T. Clark , Kyle E. Nielsen
发明人： Lawrence T. Clark , Kyle E. Nielsen
IPC分类号： H03K19/003 , H01L27/088 , H01L27/092 , H01L27/06 , H03K19/20 , H01L23/50 , H03K3/037 , H03K19/0175 , H03K19/00 , H01L27/02 , H01L23/00
CPC分类号： H03K19/23 , H01L23/50 , H01L24/03 , H01L24/05 , H01L27/0255 , H01L27/0629 , H01L27/088 , H01L27/092 , H01L2224/0401 , H01L2224/04042 , H01L2924/14 , H01L2924/1426 , H03K3/0377 , H03K19/0002 , H03K19/00338 , H03K19/00392 , H03K19/017509 , H03K19/20
摘要： Embodiments of radiation hardened by design digital input/output circuits are described herein. Other examples and related methods are also disclosed herein.
摘要翻译：本文描述了由设计数字输入/输出电路硬化的辐射的实施例。本文还公开了其它实例和相关方法。

99. 发明申请

US20140331197A1 SEQUENTIAL STATE ELEMENTS IN TRIPLE-MODE REDUNDANT (TMR) STATE MACHINES 有权
标题翻译：三态冗余（TMR）状态机中的顺序状态元素
公开(公告)号：US20140331197A1
公开(公告)日：2014-11-06
申请号：US14304155
申请日：2014-06-13
申请人： Lawrence T. Clark , Nathan D. Hindman , Dan Wheeler Patterson
发明人： Lawrence T. Clark , Nathan D. Hindman , Dan Wheeler Patterson
IPC分类号： G06F17/50
CPC分类号： G06F17/5072 , G06F17/505 , H03K19/00315
摘要： The disclosure relates generally to triple-redundant sequential state (TRSS) machines formed as integrated circuits on a semiconductor substrate, such as CMOS, and computerized methods and systems of designing the triple-redundant sequential state machines. Of particular focus in this disclosure are sequential state elements (SSEs) used to sample and hold bit states. The sampling and holding of bits states are synchronized by a clock signal thereby allowing for pipelining in the TRSS machines. In particular, the clock signal may oscillate between a first clock state and a second clock state to synchronize the operation of the SSE according to the timing provided by the clock states. The SSEs has a self-correcting mechanism to protect against radiation induced soft errors. The SSE may be provided in a pipeline circuit of a TRSS machine to receive and store a bit state of bit signal generated by combinational circuits within the pipeline circuit.
摘要翻译：本公开一般涉及形成为诸如CMOS的半导体衬底上的集成电路的三冗余顺序状态（TRSS）机器，以及设计三重冗余顺序状态机的计算机化方法和系统。本公开中特别关注的是用于采样和保持位状态的顺序状态元素（SSE）。位状态的采样和保持由时钟信号同步，从而允许在TRSS机器中流水线化。具体地，时钟信号可以在第一时钟状态和第二时钟状态之间振荡，以根据由时钟状态提供的定时使SSE的操作同步。 SSEs具有自我纠正机制，可防止辐射诱发的软错误。 SSE可以设置在TRSS机器的管线电路中，以接收和存储由管线电路内的组合电路产生的位信号的位状态。

100. 发明授权

US08847684B2 Analog circuits having improved transistors, and methods therefor 有权
标题翻译：具有改进的晶体管的模拟电路及其方法
公开(公告)号：US08847684B2
公开(公告)日：2014-09-30
申请号：US13770482
申请日：2013-02-19
申请人： Lawrence T. Clark , Scott E. Thompson
发明人： Lawrence T. Clark , Scott E. Thompson
IPC分类号： H03F3/45
CPC分类号： H03F3/45179 , H03F3/45 , H03F3/45071 , H03F3/45183 , H03F3/45273 , H03F2200/375 , H03F2203/45344 , H03F2203/45454 , H03F2203/45506 , H03F2203/45674 , H03F2203/45676
摘要： Circuits are disclosed that may include a plurality of transistors having controllable current paths coupled between at least a first and second node, the transistors configured to generate an analog electrical output signal in response to an analog input value; wherein at least one of the transistors has a deeply depleted channel formed below its gate that includes a substantially undoped channel region formed over a relatively highly doped screen layer formed over a doped body region.
摘要翻译：公开了可以包括多个具有耦合在至少第一和第二节点之间的可控电流路径的晶体管的晶体管，其被配置为响应于模拟输入值产生模拟电输出信号; 其中所述晶体管中的至少一个具有在其栅极下方形成的深耗尽沟道，其包括在掺杂体区域上形成的相对高掺杂的屏蔽层上形成的基本上未掺杂的沟道区。

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