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91. 发明授权

US06333555B1 Interconnect for semiconductor components and method of fabrication 失效
标题翻译：半导体元件的互连和制造方法
公开(公告)号：US06333555B1
公开(公告)日：2001-12-25
申请号：US09430832
申请日：1999-10-29
申请人： Warren M. Farnworth , Salman Akram
发明人： Warren M. Farnworth , Salman Akram
IPC分类号： H01L2348
CPC分类号： H01L23/49827 , H01L23/13 , H01L2224/114 , H01L2224/116 , H01L2224/16 , H01L2924/00014 , H01L2924/01046 , H01L2924/01078 , H01L2924/01087 , H01L2924/09701 , H01L2224/0401
摘要： An interconnect for electrically contacting semiconductor components such as bare dice, wafers and chip scale packages, is provided. The interconnect includes a rigid substrate and polymer contact members formed on the substrate. The polymer contact members are adapted to electrically engage contacts (e.g., bond pads, solder bumps) on the component. In one embodiment the polymer contact members are raised members with penetrating projections covered with conductive layers. In another embodiment the polymer contact members are indentations and penetrating projections covered with conductive layers. A method for fabricating the polymer contact members includes the steps of depositing, patterning and etching a thick film resist. These steps are followed by electrolessly depositing conductive layers on the contact members, and conductors in electrical communication with the conductive layers.
摘要翻译：提供了用于电接触诸如裸裸片，晶片和芯片级封装的半导体部件的互连。互连包括形成在基底上的刚性基底和聚合物接触构件。聚合物接触构件适于电连接部件上的触点（例如，接合焊盘，焊料凸块）。在一个实施例中，聚合物接触构件是具有被导电层覆盖的穿透突起的凸起构件。在另一个实施方案中，聚合物接触构件是用导电层覆盖的凹陷和穿透突起。制造聚合物接触构件的方法包括沉积，图案化和蚀刻厚膜抗蚀剂的步骤。这些步骤之后是在接触构件上无电沉积导电层，以及与导电层电连通的导体。

92. 发明授权

US06329828B1 Method and apparatus for capacitively testing a semiconductor die 失效
标题翻译：用于对半导体管芯进行电容测试的方法和装置
公开(公告)号：US06329828B1
公开(公告)日：2001-12-11
申请号：US09387649
申请日：1999-09-01
申请人： Warren M. Farnworth , Salman Akram
发明人： Warren M. Farnworth , Salman Akram
IPC分类号： G01R3102
CPC分类号： G01R31/312
摘要： An apparatus, process for forming an apparatus, and method for testing a semiconductor die having first and second die terminals. The apparatus includes a substrate having a coefficient of thermal expansion approximately equal to a thermal expansion coefficient of the die. The substrate includes first and second test terminals positioned on a surface of the substrate and positionable proximate to the die. The first test terminal is a conductive portion aligned with and spaced apart from a conductive portion of the first die terminal when the substrate is positioned proximate to the die. The first test terminal is coupleable to a variable power source current to generate a variable signal at the first test terminal and capacitively generate a corresponding signal at the first die terminal. The second test terminal is aligned with the second die terminal when the conductive portion of the first test terminal is aligned with the first die terminal.
摘要翻译：一种用于形成装置的装置，方法以及用于测试具有第一和第二管芯端子的半导体管芯的方法。该装置包括具有近似等于模具的热膨胀系数的热膨胀系数的基板。衬底包括位于衬底的表面上的第一和第二测试端子，并且可靠近模具定位。第一测试端子是当基板定位成靠近模具时与第一模具端子的导电部分对准并间隔开的导电部分。第一测试端子可耦合到可变电源电流，以在第一测试端子处产生可变信号，并在第一模具端子处电容地产生相应的信号。当第一测试端子的导电部分与第一裸片端子对准时，第二测试端子与第二裸片端子对齐。

93. 发明授权

US06261854B1 Interconnect with pressure sensing mechanism for testing semiconductor wafers 有权
标题翻译：与用于测试半导体晶圆的压力感测机构相互连接
公开(公告)号：US06261854B1
公开(公告)日：2001-07-17
申请号：US09224924
申请日：1999-01-04
申请人： Salman Akram , Warren M. Farnworth
发明人： Salman Akram , Warren M. Farnworth
IPC分类号： G01R3126
CPC分类号： G01R31/2891 , G01R1/06711 , G01R1/06738 , G01R1/07314 , G01R31/2863
摘要： An interconnect for testing semiconductor wafers, and a method and system for testing wafers using the interconnect are provided. The interconnect includes a substrate with contact members configured to establish temporary electrical communication with contact locations (e.g., bond pads, test pads) on the wafer. For flat contact locations (e.g., thin film bond pads), the contact members comprise raised members with penetrating projections. For bumped contact locations (e.g., solder bumps), the contact members comprise indentations with a conductive layer. The interconnect also includes a pressure sensing mechanism for monitoring and controlling contact forces between the interconnect and wafer. In an illustrative embodiment the pressure sensing mechanism comprises a piezoresistive or piezoelectric layer and resistance measuring device.
摘要翻译：提供了用于测试半导体晶片的互连，以及用于使用互连测试晶片的方法和系统。互连包括具有接触构件的衬底，其被配置为建立与晶片上的接触位置（例如，接合焊盘，测试焊盘）的临时电连通。对于平坦接触位置（例如，薄膜接合垫），接触构件包括具有穿透突起的凸起构件。对于凸起的接触位置（例如，焊料凸块），接触构件包括具有导电层的凹陷。互连还包括用于监测和控制互连和晶片之间的接触力的压力感测机构。在说明性实施例中，压力感测机构包括压阻或压电层和电阻测量装置。

94. 发明授权

US06222280B1 Test interconnect for semiconductor components having bumped and planar contacts 有权
公开(公告)号：US06222280B1
公开(公告)日：2001-04-24
申请号：US09274138
申请日：1999-03-22
申请人： Warren M. Farnworth , Salman Akram
发明人： Warren M. Farnworth , Salman Akram
IPC分类号： H01L2348
CPC分类号： G01R1/06733 , G01R1/0408 , G01R1/07314 , H01L2924/0002 , H05K1/11 , H05K3/325 , H01L2924/00
摘要： An interconnect for testing semiconductor components having both bumped contacts, and planar contacts, is provided. The interconnect includes: a substrate, first contacts on the substrate for electrically engaging the bumped contacts, and second contacts on the substrate for electrically engaging the planar contacts. In illustrative embodiments the first contacts include recesses in the substrate covered with a conductive layer, or recesses formed in a compliant layer on the substrate, or conductive polymer donuts sized and shaped to retain the bumped contacts. In illustrative embodiments the second contacts include etched pillars having penetrating projections, or conductive polymer bumps having penetrating particles, or flat topped projections having a compliant layer thereon. The interconnect can be used to construct a die level test carrier for testing components in singulated form, or to construct a wafer level test carrier for testing components in wafer or panel form.

95. 发明授权

US06208157B1 Method for testing semiconductor components 有权
标题翻译：半导体元件测试方法
公开(公告)号：US06208157B1
公开(公告)日：2001-03-27
申请号：US09298769
申请日：1999-04-23
申请人： Salman Akram , David R. Hembree , Warren M. Farnworth , Derek Gochnour , Alan G. Wood , John O. Jacobson
发明人： Salman Akram , David R. Hembree , Warren M. Farnworth , Derek Gochnour , Alan G. Wood , John O. Jacobson
IPC分类号： G01R3102
CPC分类号： G01R1/0466 , G01R1/0433 , G01R1/0483
摘要： A system and method for testing semiconductor components are provided. The system includes: a test board, sockets mounted to the test board in electrical communication with test circuitry, and carriers mounted to the sockets for housing the components. The carriers include bases, and interconnects mounted thereon, having contact members configured to make temporary electrical connections with contacts on the components. In addition, the contact members on the interconnects can be shaped to perform an alignment function, and to prevent excessive deformation of the contacts on the components. The sockets include camming members and electrical connectors configured to electrically contact the carriers with a zero insertion force. During a test procedure, the bases and interconnects can remain mounted to the sockets on the test board, as the components are aligned and placed in electrical contact with the interconnects. However, different bases and interconnects can be mounted to the sockets for testing different types of components.
摘要翻译：提供了一种用于测试半导体部件的系统和方法。该系统包括：测试板，安装在与测试电路电气通信的测试板上的插座，以及安装在插座上用于容纳组件的载体。载体包括底座和安装在其上的互连件，其具有被配置为与部件上的触点进行临时电连接的接触构件。此外，互连上的接触构件可以成形为执行对准功能，并且防止部件上的触点的过度变形。插座包括凸轮构件和被配置为以零插入力电接触托架的电连接器。在测试过程中，基板和互连件可以保持安装到测试板上的插座上，因为组件对齐并放置成与互连件电接触。然而，可以将不同的基座和互连件安装到插座以测试不同类型的部件。

96. 发明授权

US6165817A Method of bonding a flexible polymer tape to a substrate to reduce stresses on the electrical connections 有权
标题翻译：将柔性聚合物带粘合到基底上以减少电连接上的应力的方法
公开(公告)号：US6165817A
公开(公告)日：2000-12-26
申请号：US398213
申请日：1999-09-17
申请人： Salman Akram , Warren M. Farnworth
发明人： Salman Akram , Warren M. Farnworth
IPC分类号： H01L23/31 , H01L25/10 , H05K3/30 , H05K3/34 , H05K3/36 , H01L21/48
CPC分类号： H05K3/305 , H01L23/3107 , H01L25/105 , H01L2224/05571 , H01L2224/05573 , H01L2224/16225 , H01L2225/1023 , H01L2225/1058 , H01L2225/1094 , H01L2924/00014 , H01L2924/01079 , H01L2924/12044 , H01L2924/15331 , H05K3/3436 , H05K3/363 , H05K2201/10689 , Y02P70/613 , H01L2224/05599
摘要： The present invention is directed to a semiconductor package and its method of manufacture. Conductors mounted on a flexible polymer tape are used to connect a semiconductor chip to a substrate. The flexible polymer tape can be folded back under the chip to reduce the size necessary for mounting the assembly to almost that of the chip itself. The polymer tape also provides flexibility to reduce stresses on the electrically connections caused by thermal expansion and compression. Additionally, the present invention allows for the stacking of semiconductor chips on top of one another, reducing signal propagation delays between them.
摘要翻译：本发明涉及半导体封装及其制造方法。安装在柔性聚合物胶带上的导体用于将半导体芯片连接到基板。柔性聚合物带可以折叠在芯片下方，以减小将组件安装到芯片本身几乎所需的尺寸。聚合物胶带还提供柔性，以减少由热膨胀和压缩引起的电连接上的应力。此外，本发明允许将半导体芯片堆叠在一起，减少它们之间的信号传播延迟。

97. 发明授权

US6150717A Direct die contact (DDC) semiconductor package 失效
标题翻译：直接裸片接触（DDC）半导体封装
公开(公告)号：US6150717A
公开(公告)日：2000-11-21
申请号：US98197
申请日：1998-06-16
申请人： Alan G. Wood , Warren M. Farnworth , Ford Grigg , Salman Akram
发明人： Alan G. Wood , Warren M. Farnworth , Ford Grigg , Salman Akram
IPC分类号： H01L21/60 , H01L23/485 , H01L23/48
CPC分类号： H01L24/81 , H01L24/11 , H01L24/13 , H01L2224/05001 , H01L2224/05022 , H01L2224/05026 , H01L2224/05571 , H01L2224/10165 , H01L2224/13099 , H01L2224/131 , H01L2224/1319 , H01L2224/16237 , H01L2224/81136 , H01L2224/8114 , H01L2224/81191 , H01L2224/81192 , H01L2224/81193 , H01L2224/81365 , H01L2224/81801 , H01L2924/0001 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01011 , H01L2924/01013 , H01L2924/01015 , H01L2924/01024 , H01L2924/01029 , H01L2924/0103 , H01L2924/01033 , H01L2924/01046 , H01L2924/01049 , H01L2924/0105 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01087 , H01L2924/01322 , H01L2924/014 , H01L2924/14 , H01L2924/15153 , H01L2924/1517
摘要： A semiconductor package and method for fabricating the package are provided. The package includes a housing having individual channels, each adapted to retain a semiconductor die in electrical communication with electrical connectors. The dice can include solder bumps, formed on electrodes, using electroless deposition and wave soldering. For fabricating the package, the dice can be inserted into the channels, with the electrical connectors on the housing proximate to the solder bumps on the dice. The solder bumps can then be reflowed to form bonded connections with the electrical connectors. In an alternate embodiment, conductive adhesive bumps, rather than solder bumps, are formed on the dice to provide compliant connections with the electrical connectors on the housing. In addition, the conductive adhesive bumps can be cured while in contact with the electrical connectors to form bonded connections. Other alternate embodiments include a chip scale package, a temporary package for testing bare dice, and a multi chip module.
摘要翻译：提供一种用于制造封装的半导体封装和方法。封装包括具有单独通道的壳体，每个通道适于保持与电连接器电连通的半导体管芯。骰子可以包括使用无电沉积和波峰焊在电极上形成的焊料凸块。为了制造封装，可以将骰子插入通道中，外壳上的电连接器靠近骰子上的焊料凸块。然后可以将焊料凸起回流以与电连接器形成粘合连接。在替代实施例中，导电粘合剂凸块而不是焊料凸块形成在芯片上，以提供与壳体上的电连接器的柔性连接。此外，导电粘合剂凸块可以在与电连接器接触的同时固化，以形成接合连接。其他替代实施例包括芯片级封装，用于测试裸裸片的临时封装以及多芯片模块。

98. 发明授权

US6124634A Micromachined chip scale package 有权
标题翻译：微加工芯片级封装
公开(公告)号：US6124634A
公开(公告)日：2000-09-26
申请号：US156300
申请日：1998-09-17
申请人： Salman Akram , David R. Hembree , Warren M. Farnworth
发明人： Salman Akram , David R. Hembree , Warren M. Farnworth
IPC分类号： H01L21/60 , H01L23/485 , H01L23/58 , H01L23/04 , H01L29/40
CPC分类号： H01L23/13 , H01L24/11 , H01L24/13 , H01L2224/0231 , H01L2224/0401 , H01L2224/1148 , H01L2224/13099 , H01L2224/131 , H01L2224/1319 , H01L2224/13339 , H01L2224/16237 , H01L2924/0001 , H01L2924/00013 , H01L2924/01005 , H01L2924/01013 , H01L2924/01015 , H01L2924/01022 , H01L2924/01024 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/01046 , H01L2924/01047 , H01L2924/01074 , H01L2924/01075 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01322 , H01L2924/014 , H01L2924/10329 , H01L2924/14 , H01L2924/15787 , H01L2924/19041 , H01L2924/19043
摘要： A chip scale package comprised of a semiconductor die having a silicon blank laminated to its active surface. The bond pads of the die are accessed through apertures micromachined through the blank. The package may be employed with wire bonds, or solder or other conductive bumps may be placed in the blank apertures for flip-chip applications. Further, the package may be employed to reroute external connections of the die to other locations, such as a centralized ball grid array or in an edge-connect arrangement for direct or discrete die connect (DDC) to a carrier. It is preferred that the chip scale package be formed at the wafer level, as one of a multitude of packages so formed with a wafer-level blank, and that the entire wafer be burned-in and tested to identify the known good die (KGD) before the wafer laminate is separated into individual packages.
摘要翻译：芯片级封装由半导体管芯组成，半导体管芯具有层压在其有源表面上的硅片。模具的接合焊盘通过微机械加工通过坯件的孔进入。该封装可以与引线接合使用，或者可以将焊料或其它导电凸块放置在用于倒装芯片应用的空白孔中。此外，可以使用封装将管芯的外部连接重新路由到其他位置，例如集中式球栅阵列或用于直接或离散管芯连接（DDC）到载体的边缘连接装置。优选的是，芯片级封装形成在晶片级，作为如此形成的多个封装之一，其形成有晶片级坯料，并且整个晶片被烧入并测试以识别已知的良好裸片（KGD ），然后将晶片层压板分离成单个包装。

99. 发明授权

US6114240A Method for fabricating semiconductor components using focused laser beam 有权
标题翻译：使用聚焦激光束制造半导体元件的方法
公开(公告)号：US6114240A
公开(公告)日：2000-09-05
申请号：US250289
申请日：1999-02-12
申请人： Salman Akram , Warren M. Farnworth , Alan G. Wood
发明人： Salman Akram , Warren M. Farnworth , Alan G. Wood
IPC分类号： H01L21/48 , H01L21/60 , H01L21/768 , H01L23/13 , H01L23/498 , H01L23/538 , H01L25/10 , H05K1/03 , H05K1/11 , H05K3/00 , H01L21/44
CPC分类号： H05K1/112 , H01L21/486 , H01L21/76898 , H01L23/13 , H01L23/49827 , H01L23/5389 , H01L25/105 , H01L2224/05001 , H01L2224/05023 , H01L2224/05624 , H01L2224/05639 , H01L2224/05644 , H01L2224/05647 , H01L2224/05655 , H01L2224/05664 , H01L2224/05666 , H01L2224/05669 , H01L2224/0568 , H01L2224/05681 , H01L2224/05684 , H01L2224/16237 , H01L2224/82039 , H01L2225/1005 , H01L2924/01004 , H01L2924/01006 , H01L2924/01009 , H01L2924/01013 , H01L2924/0102 , H01L2924/01022 , H01L2924/01027 , H01L2924/01029 , H01L2924/01032 , H01L2924/01033 , H01L2924/01039 , H01L2924/01042 , H01L2924/01046 , H01L2924/01047 , H01L2924/0105 , H01L2924/01073 , H01L2924/01074 , H01L2924/01077 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01087 , H01L2924/014 , H01L2924/09701 , H01L2924/12042 , H01L2924/14 , H01L2924/15311 , H01L2924/15331 , H05K1/0306 , H05K2201/09472 , H05K2201/0959 , H05K2201/09827 , H05K2201/09845 , H05K2201/10674 , H05K2201/10734 , H05K3/0029 , H05K3/0032
摘要： A method for fabricating semiconductor components, such as packages, interconnects and test carriers, is provided. The method includes laser machining conductive vias for interconnecting contacts on the component, using a laser beam that is focused to produce a desired via geometry. The vias can include enlarged end portions to facilitate deposition of a conductive material during formation of the vias, and to provide an increased surface area for forming the contacts. For example, by focusing the laser beam at a midpoint of a substrate of the component, an hour glass via geometry is provided. Alternately, the laser beam can be focused at an exit point, or at an entry point of the substrate, to provide converging or diverging via geometries. The method can also include forming contact pins on the conductive vias by bonding and shaping metal wires using a wire bonding process, or a welding process.
摘要翻译：提供了一种制造诸如封装，互连和测试载体的半导体部件的方法。该方法包括激光加工用于使部件上的触点互连的导电通孔，使用聚焦以产生所需通孔几何形状的激光束。通孔可以包括扩大的端部，以便于在形成通孔期间沉积导电材料，并且提供用于形成触点的增加的表面积。例如，通过将激光束聚焦在部件的基板的中点处，提供了小时玻璃通孔几何形状。或者，激光束可以在出口点处或在基板的入口处聚焦，以提供会聚或发散的几何形状。该方法还可以包括通过使用引线接合工艺或焊接工艺接合和成形金属线来在导电通孔上形成接触引脚。

100. 发明授权

US6091252A Method, apparatus and system for testing bumped semiconductor components 有权
标题翻译：用于测试碰撞半导体元件的方法，装置和系统
公开(公告)号：US6091252A
公开(公告)日：2000-07-18
申请号：US312381
申请日：1999-05-14
申请人： Salman Akram , Warren M. Farnworth , Alan G. Wood , David R. Hembree
发明人： Salman Akram , Warren M. Farnworth , Alan G. Wood , David R. Hembree
IPC分类号： G01R1/04 , G01R1/067 , G01R1/073 , G01R31/28 , G01R1/06 , G01R31/26
CPC分类号： G01R1/0466
摘要： A method, apparatus and system for establishing temporary electrical communication with semiconductor components having contact bumps are provided. The apparatus includes an interconnect having patterns of contact members adapted to electrically contact the contact bumps. Each contact member includes an array of one or more electrically conductive projections in electrical communication with an associated conductor. The projections form contact members for retaining individual contact bumps on the semiconductor components. The projections can be pillars having angled faces covered with a conductive layer. Alternately the projections can be a material deposited on the substrate, or can be microbumps formed on multi layered tape bonded to the substrate. The interconnect can be employed in a wafer level test system for testing dice contained on a wafer, or in a die level test system for testing bare bumped dice or bumped chip scale packages.
摘要翻译：提供了一种用于与具有接触凸块的半导体部件建立临时电连通的方法，装置和系统。该装置包括具有适于电接触接触凸点的接触构件图案的互连。每个接触构件包括与相关导体电连通的一个或多个导电突起的阵列。突起形成接触构件，用于保持半导体部件上的各个接触凸块。突起可以是具有覆盖有导电层的成角度表面的柱。替代地，突起可以是沉积在基底上的材料，或者可以是在结合到基底的多层带上形成的微胶囊。互连可以用于晶片级测试系统中，用于测试包含在晶片上的骰子，或者在用于测试裸露骰子或凸起的芯片级封装的芯片级测试系统中。

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