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91. 发明授权

US10128261B2 Cobalt-containing conductive layers for control gate electrodes in a memory structure 有权
公开(公告)号：US10128261B2
公开(公告)日：2018-11-13
申请号：US14613956
申请日：2015-02-04
申请人： SANDISK TECHNOLOGIES INC.
发明人： Raghuveer S. Makala , Rahul Sharangpani , Sateesh Koka , Genta Mizuno , Naoki Takeguchi , Senaka Krishna Kanakamedala , George Matamis , Yao-Sheng Lee , Johann Alsmeier
IPC分类号： H01L27/115 , H01L27/11582 , H01L27/11556 , H01L29/49 , H01L21/28 , H01L27/11563 , H01L27/11578 , H01L29/66 , H01L29/788 , H01L29/792 , H01L21/3213 , H01L21/768 , H01L27/11519 , H01L27/11524 , H01L27/11565 , H01L27/1157 , H01L27/11568
摘要： A memory film and a semiconductor channel can be formed within each memory opening that extends through a stack including an alternating plurality of insulator layers and sacrificial material layers. After formation of backside recesses through removal of the sacrificial material layers selective to the insulator layers, a metallic barrier material portion can be formed in each backside recess. A cobalt portion can be formed in each backside recess. Each backside recess can be filled with a cobalt portion alone, or can be filled with a combination of a cobalt portion and a metallic material portion including a material other than cobalt.

92. 发明授权

US09825051B2 Three dimensional NAND device containing fluorine doped layer and method of making thereof 有权
公开(公告)号：US09825051B2
公开(公告)日：2017-11-21
申请号：US14521050
申请日：2014-10-22
申请人： SanDisk Technologies, Inc.
发明人： Peter Rabkin , Jayavel Pachamuthu , Johann Alsmeier
IPC分类号： H01L27/115 , H01L27/11582 , H01L21/28 , H01L27/11524 , H01L27/11556 , H01L27/1157 , H01L29/167 , H01L29/423 , H01L29/51 , H01L29/788 , H01L21/02
CPC分类号： H01L27/11582 , H01L21/02131 , H01L21/0214 , H01L21/0217 , H01L21/02178 , H01L21/02274 , H01L21/0228 , H01L21/02321 , H01L21/02326 , H01L21/02337 , H01L21/0234 , H01L21/28282 , H01L27/11524 , H01L27/11556 , H01L27/1157 , H01L29/167 , H01L29/42364 , H01L29/51 , H01L29/518 , H01L29/7883
摘要： A method of making a monolithic three dimensional NAND string comprising forming a stack of alternating layers of a first material and a second material different from the first material over a substrate, forming an at least one front side opening in the stack and forming at least a portion of a memory film in the at least one front side opening. The method also includes forming a semiconductor channel in the at least one front side opening and doping at least one of the memory film and the semiconductor channel with fluorine in-situ during deposition or by annealing in a fluorine containing atmosphere.

93. 发明申请

US20170278571A1 THREE DIMENSIONAL NAND MEMORY DEVICE WITH COMMON BIT LINE FOR MULTIPLE NAND STRINGS IN EACH MEMORY BLOCK 审中-公开
公开(公告)号：US20170278571A1
公开(公告)日：2017-09-28
申请号：US15078555
申请日：2016-03-23
申请人： SANDISK TECHNOLOGIES INC.
发明人： Murshed Chowdhury , Jin Liu , Yanli Zhang , Andrew Lin , Raghuveer S. Makala , Johann Alsmeier
IPC分类号： G11C16/04 , G11C16/26 , G11C16/10
CPC分类号： G11C16/0483 , G11C16/10 , G11C16/26 , H01L27/11524 , H01L27/11556 , H01L27/1157 , H01L27/11582
摘要： Two vertical NAND strings can share a common bit line by providing two pairs of drain select transistors. Channels of each vertical NAND string containing an adjoining pair of drain select transistors are incorporated into a respective vertical semiconductor channel, which is adjoined to a respective drain region which is connected to the common bit line. The drain select transistors have mismatched threshold voltages at each level such that each vertical NAND string includes a level at which a respective drain select transistor has a higher threshold voltage than a counterpart drain select transistor for the other vertical NAND string at the same level. By turning on three drain select transistors out of four, only one vertical NAND string can be activated while the common bit line is biased at a suitable bias voltage. A programming operation or a read operation can be performed only on the activated NAND string.

94. 发明授权

US09754667B2 Three-dimensional NAND non-volatile memory and DRAM memory devices on a single substrate 有权
公开(公告)号：US09754667B2
公开(公告)日：2017-09-05
申请号：US14935188
申请日：2015-11-06
申请人： SANDISK TECHNOLOGIES INC.
发明人： Johann Alsmeier
IPC分类号： G11C14/00 , G11C16/04 , H01L27/108 , H01L27/11551 , H01L27/11578 , H01L27/11524 , H01L27/11556 , H01L27/1157 , H01L27/11582
CPC分类号： G11C14/0018 , G11C16/0483 , H01L27/10805 , H01L27/10844 , H01L27/10847 , H01L27/10891 , H01L27/11524 , H01L27/11551 , H01L27/11556 , H01L27/1157 , H01L27/11578 , H01L27/11582
摘要： A three-dimensional NAND stacked non-volatile memory array and a DRAM memory array are provided. The three-dimensional NAND stacked non-volatile memory array and the DRAM memory array are integrated on a single substrate.

95. 发明授权

US09716101B2 Forming 3D memory cells after word line replacement 有权
公开(公告)号：US09716101B2
公开(公告)日：2017-07-25
申请号：US14928385
申请日：2015-10-30
申请人： SanDisk Technologies Inc.
发明人： Zhenyu Lu , Hiro Kinoshita , Daxin Mao , Johann Alsmeier , Wenguang Shi , Yingda Dong , Henry Chien , Kensuke Yamaguchi , Xiaolong Hu
IPC分类号： H01L27/115 , H01L27/1157 , H01L27/11582 , H01L27/11575
CPC分类号： H01L27/1157 , H01L27/11575 , H01L27/11582
摘要： Techniques for forming 3D memory arrays are disclosed. Memory openings are filled with a sacrificial material, such as silicon or nitride. Afterwards, a replacement technique is used to remove nitride from an ONON stack and replace it with a conductive material such as tungsten. Afterwards, memory cell films are formed in the memory openings. The conductive material serves as control gates of the memory cells. The control gate will not suffer from corner rounding. ONON shrinkage is avoided, which will prevent control gate shrinkage. Block oxide between the charge storage region and control gate may be deposited after control gate replacement, so the uniformity is good. Block oxide may be deposited after control gate replacement, so TiN adjacent to control gates can be thicker to prevent fluorine attacking the insulator between adjacent control gates. Therefore, control gate to control gate shorting is prevented.

96. 发明授权

US09679906B2 Three-dimensional memory devices containing memory block bridges 有权
公开(公告)号：US09679906B2
公开(公告)日：2017-06-13
申请号：US14823274
申请日：2015-08-11
申请人： SANDISK TECHNOLOGIES INC.
发明人： Zhenyu Lu , Johann Alsmeier , Daxin Mao , Wenguang Shi , Sateesh Koka , Raghuveer S. Makala , George Matamis , Yao-Sheng Lee , Chun Ge
IPC分类号： H01L27/115 , H01L27/1157 , H01L27/11582 , H01L27/11524 , H01L27/11556
CPC分类号： H01L27/1157 , H01L27/11519 , H01L27/11524 , H01L27/11548 , H01L27/11556 , H01L27/11565 , H01L27/11575 , H01L27/11582
摘要： A monolithic three-dimensional memory device includes a first memory block containing a plurality of memory sub-blocks located on a substrate. Each memory sub-block includes a set of memory stack structures and a portion of alternating layers laterally surrounding the set of memory stack structures. The alternating layers include insulating layers and electrically conductive layers. A first portion of a neighboring pair of memory sub-blocks is laterally spaced from each other along a first horizontal direction by a backside contact via structure. A subset of the alternating layers contiguously extends between a second portion of the neighboring pair of memory sub-blocks through a gap in a bridge region between two portions of the backside contact via structure that are laterally spaced apart along a second horizontal direction to provide a connecting portion between the neighboring pair of memory sub-blocks.

97. 发明授权

US09627395B2 Enhanced channel mobility three-dimensional memory structure and method of making thereof 有权
公开(公告)号：US09627395B2
公开(公告)日：2017-04-18
申请号：US14619691
申请日：2015-02-11
申请人： SANDISK TECHNOLOGIES INC.
发明人： Yanli Zhang , Raghuveer S. Makala , Johann Alsmeier
IPC分类号： H01L27/115 , H01L21/324 , H01L21/768 , H01L21/28 , H01L23/522 , H01L29/788 , H01L27/11556
CPC分类号： H01L27/11556 , H01L21/28273 , H01L21/76802 , H01L21/76877 , H01L27/11524 , H01L27/1157 , H01L27/11582 , H01L29/7883
摘要： A stack including an alternating plurality of first material layers and second material layers is provided. A memory opening is formed and at least a contiguous semiconductor material portion including a semiconductor channel is formed therein. The contiguous semiconductor material portion includes an amorphous or polycrystalline semiconductor material. A metallic material portion is provided at a bottom surface of the semiconductor channel, at a top surface of the semiconductor channel, or on portions of an outer sidewall surface of the semiconductor channel. An anneal is performed to induce diffusion of a metal from the metallic material portion through the semiconductor channel, thereby inducing conversion of the amorphous or polycrystalline semiconductor material into a crystalline semiconductor material. The crystalline semiconductor material has a relatively large grain size due to the catalytic crystallization process, and can provide enhanced charge carrier mobility.

98. 发明授权

US09620514B2 3D semicircular vertical NAND string with self aligned floating gate or charge trap cell memory cells and methods of fabricating and operating the same 有权
公开(公告)号：US09620514B2
公开(公告)日：2017-04-11
申请号：US14748575
申请日：2015-06-24
申请人： SANDISK TECHNOLOGIES INC.
发明人： James K. Kai , Yanli Zhang , Henry Chien , Johann Alsmeier
IPC分类号： H01L27/115 , H01L27/11556 , H01L27/11582 , H01L27/11565 , H01L27/11519 , G11C16/04 , H01L29/66 , H01L27/11524 , H01L27/1157 , G11C16/14
CPC分类号： H01L27/11556 , G11C16/0408 , G11C16/0483 , G11C16/14 , H01L27/11519 , H01L27/11524 , H01L27/11565 , H01L27/1157 , H01L27/11582 , H01L29/66666 , H01L29/66825 , H01L29/7827
摘要： A memory device includes a plurality of memory cells arranged in a string substantially perpendicular to the major surface of the substrate in a plurality of device levels, at least one first select gate electrode located between the major surface of the substrate and the plurality of memory cells, at least one second select gate electrode located above the plurality of memory cells, a semiconductor channel having a portion that extends vertically along a direction perpendicular to the major surface, a first memory film contacting a first side of the semiconductor channel, and a second memory film contacting a second side of the semiconductor channel. The second memory film is electrically isolated from the first memory film, and is located at a same level as the first memory film.

99. 发明授权

US09589981B2 Passive devices for integration with three-dimensional memory devices 有权
标题翻译：用于与三维存储器件集成的无源器件
公开(公告)号：US09589981B2
公开(公告)日：2017-03-07
申请号：US14739354
申请日：2015-06-15
申请人： SanDisk Technologies, Inc.
发明人： Masatoshi Nishikawa , Ryoichi Honma , Toru Miwa , Hiroaki Koketsu , Johann Alsmeier
IPC分类号： H01L27/115 , H01L23/522 , H01L23/528 , H01L49/02 , H01L21/265 , H01L21/768 , H01L21/3205
CPC分类号： H01L27/11582 , H01L21/26513 , H01L21/32055 , H01L21/76802 , H01L21/76877 , H01L23/5226 , H01L23/528 , H01L27/0688 , H01L27/11531 , H01L27/11556 , H01L27/11565 , H01L27/1157 , H01L27/11573 , H01L27/11575 , H01L28/20
摘要： A three dimensional memory device includes a memory device region containing a plurality of non-volatile memory devices, a peripheral device region containing active driver circuit devices, and a stepped surface region between the peripheral device region and the memory device region containing a plurality of passive driver circuit devices.
摘要翻译：三维存储器件包括存储器件区域，该存储器件区域包含多个非易失性存储器件，包含有源驱动器电路器件的外围器件区域以及外围器件区域和存储器器件区域之间的阶梯表面区域，该区域包含多个被动驱动电路设备。

100. 发明授权

US09576971B2 Three-dimensional memory structure having a back gate electrode 有权
标题翻译：具有背栅电极的三维存储结构
公开(公告)号：US09576971B2
公开(公告)日：2017-02-21
申请号：US14564526
申请日：2014-12-09
申请人： SanDisk Technologies, Inc.
发明人： Yanli Zhang , Johann Alsmeier , Yingda Dong , Akira Matsudaira
IPC分类号： H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： H01L27/11524 , H01L27/11556 , H01L27/1157 , H01L27/11582 , H01L29/7883 , H01L29/792 , H01L29/7926 , H01L2924/0002 , H01L2924/00
摘要： A memory stack structure includes a cavity including a back gate electrode, a back gate dielectric, a semiconductor channel, and at least one charge storage element. In one embodiment, a line trench can be filled with a memory film layer, and a plurality of semiconductor channels can straddle the line trench. The back gate electrode can extend along the lengthwise direction of the line trench. In another embodiment, an isolated memory opening overlying a patterned conductive layer can be filled with a memory film, and the back gate electrode can be formed within a semiconductor channel and on the patterned conductive layer. A dielectric cap portion electrically isolates the back gate electrode from a drain region. The back gate electrode can be employed to bias the semiconductor channel, and to enable sensing of multinary bits corresponding to different amounts of electrical charges stored in a memory cell.
摘要翻译：存储器堆叠结构包括包括背栅电极，背栅电介质，半导体沟道和至少一个电荷存储元件的空腔。在一个实施例中，可以用存储膜层填充线沟槽，并且多个半导体沟道可以跨越线沟槽。背栅电极可以沿着线沟槽的长度方向延伸。在另一个实施例中，覆盖图案化导电层的隔离存储器开口可以用存储膜填充，并且背栅电极可以形成在半导体沟道内和图案化导电层上。绝缘帽部分将背栅极电极与漏极区域电隔离。背栅电极可用于偏置半导体通道，并且能够感测对应于存储在存储单元中的不同电荷量的多位。

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