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91. 发明授权

US06686298B1 Methods of forming structures over semiconductor substrates, and methods of forming transistors associated with semiconductor substrates 有权
标题翻译：在半导体衬底上形成结构的方法，以及形成与半导体衬底相关的晶体管的方法
公开(公告)号：US06686298B1
公开(公告)日：2004-02-03
申请号：US09602089
申请日：2000-06-22
申请人： Kevin L. Beaman , John T. Moore
发明人： Kevin L. Beaman , John T. Moore
IPC分类号： H01L2131
CPC分类号： H01L21/823842 , H01L21/823857 , H01L27/105 , H01L27/1052 , H01L27/11546 , Y10S257/90
摘要： The invention includes a method of forming a structure over a semiconductor substrate. A silicon dioxide containing layer is formed across at least some of the substrate. Nitrogen is formed within the silicon dioxide containing layer. Substantially all of the nitrogen within the silicon dioxide is at least 10 Å above the substrate. After the nitrogen is formed within the silicon dioxide layer, conductively doped silicon is formed on the silicon dioxide layer.
摘要翻译：本发明包括在半导体衬底上形成结构的方法。在至少一些基底上形成含二氧化硅层。在含二氧化硅层内形成氮。二氧化硅内的基本上所有的氮基本上都在衬底之上至少10埃。在二氧化硅层内形成氮之后，在二氧化硅层上形成导电掺杂的硅。

92. 发明授权

US06660657B1 Methods of incorporating nitrogen into silicon-oxide-containing layers 有权
标题翻译：将氮掺入含氧化硅的层中的方法
公开(公告)号：US06660657B1
公开(公告)日：2003-12-09
申请号：US09633556
申请日：2000-08-07
申请人： Gurtej S. Sandhu , John T. Moore , Neal R. Rueger
发明人： Gurtej S. Sandhu , John T. Moore , Neal R. Rueger
IPC分类号： H01L2131
CPC分类号： H01L21/02332 , H01L21/0234 , H01L21/265 , H01L21/28061 , H01L21/28167 , H01L21/28185 , H01L21/28202 , H01L21/3144 , H01L29/513 , H01L29/518 , H01L29/6659 , H01L29/7833
摘要： The invention encompasses a method of incorporating nitrogen into a silicon-oxide-containing layer. The silicon-oxide-containing layer is exposed to a nitrogen-containing plasma to introduce nitrogen into the layer. The nitrogen is subsequently thermally annealed within the layer to bond at least some of the nitrogen to silicon within the layer. The invention also encompasses a method of forming a transistor. A gate oxide layer is formed over a semiconductive substrate. The gate oxide layer comprises silicon dioxide. The gate oxide layer is exposed to a nitrogen-containing plasma to introduce nitrogen into the layer, and the layer is maintained at less than or equal to 400° C. during the exposing. Subsequently, the nitrogen within the layer is thermally annealed to bond at least a majority of the nitrogen to silicon. At least one conductive layer is formed over the gate oxide layer. Source/drain regions are formed within the semiconductive substrate, and are gatedly connected to one another by the at least one conductive layer. The invention also encompasses transistor structures.
摘要翻译：本发明包括将氮掺入含氧化硅的层中的方法。将含氧化硅的层暴露于含氮等离子体中以将氮引入层中。氮气随后在层内热退火以将至少一些氮与硅结合在层内。本发明还包括形成晶体管的方法。在半导体衬底上形成栅氧化层。栅氧化层包括二氧化硅。将栅极氧化层暴露于含氮等离子体中以将氮引入层中，并且在暴露期间该层保持在小于或等于400℃。随后，层内的氮被热退火以将至少大部分氮与硅结合。在栅极氧化物层上形成至少一个导电层。源极/漏极区域形成在半导体衬底内，并且通过至少一个导电层彼此门控连接。本发明还包括晶体管结构。

93. 发明授权

US06639243B2 DRAM cell constructions 有权
标题翻译： DRAM单元结构
公开(公告)号：US06639243B2
公开(公告)日：2003-10-28
申请号：US10012233
申请日：2001-12-05
申请人： Fernando Gonzalez , Kevin L. Beaman , John T. Moore , Ron Weimer
发明人： Fernando Gonzalez , Kevin L. Beaman , John T. Moore , Ron Weimer
IPC分类号： H01L27108
CPC分类号： H01L27/10858 , H01L27/1082 , H01L27/1203 , H01L28/91 , Y10S257/906
摘要： The invention includes a method of forming a DRAM cell. A first substrate is formed to include first DRAM sub-structures separated from one another by an insulative material. A second semiconductor substrate having a monocrystalline material is bonded to the first substrate. After the bonding, second DRAM sub-structures are formed in electrical connection with the first DRAM sub-structures. The invention also includes a semiconductor structure which has a capacitor structure, and a first substrate defined to encompass the capacitor structure. The semiconductor structure further includes a monocrystalline silicon substrate bonded to the first substrate and over the capacitor structure. Additionally, the semiconductor structure includes a transistor gate on the monocrystalline silicon substrate and operatively connected with the capacitor structure to define a DRAM cell.
摘要翻译：本发明包括形成DRAM单元的方法。第一衬底被形成为包括通过绝缘材料彼此分离的第一DRAM子结构。具有单晶材料的第二半导体衬底被结合到第一衬底。在接合之后，第二DRAM子结构形成为与第一DRAM子结构电连接。本发明还包括具有电容器结构的半导体结构以及限定为包围电容器结构的第一衬底。半导体结构还包括结合到第一衬底和电容器结构上的单晶硅衬底。另外，半导体结构包括在单晶硅衬底上的晶体管栅极，并且与电容器结构可操作地连接以限定DRAM单元。

94. 发明授权

US06635530B2 Methods of forming gated semiconductor assemblies 失效
标题翻译：形成门控半导体组件的方法
公开(公告)号：US06635530B2
公开(公告)日：2003-10-21
申请号：US09057148
申请日：1998-04-07
申请人： Mark A. Helm , Mark Fischer , John T. Moore , Scott Jeffrey DeBoer
发明人： Mark A. Helm , Mark Fischer , John T. Moore , Scott Jeffrey DeBoer
IPC分类号： H01L21336
CPC分类号： H01L29/7881 , H01L21/28273 , H01L29/511
摘要： The invention includes a method of forming a gated semiconductor assembly. A first transistor gate layer is formed over a substrate. A silicon nitride layer is formed over the first transistor gate layer. The silicon nitride layer comprises a first portion and a second portion elevationally displaced above the first portion. The first portion has less electrical resistance than the second portion and a different stoichiometric composition than the second portion. The first portion is physically against the second portion. A second transistor gate layer is formed over the silicon nitride layer.
摘要翻译：本发明包括一种形成门控半导体组件的方法。在衬底上形成第一晶体管栅极层。在第一晶体管栅极层上形成氮化硅层。氮化硅层包括第一部分和在第一部分上方向上移位的第二部分。第一部分具有比第二部分更少的电阻和不同于第二部分的化学计量组成。第一部分物理地抵靠第二部分。在氮化硅层上形成第二晶体管栅极层。

95. 发明授权

US06462402B2 Microelectronic substrate comprised of etch stop layer, stiffening layer, and endpointing layer 有权
标题翻译：微电子衬底由蚀刻停止层，加强层和终点层组成
公开(公告)号：US06462402B2
公开(公告)日：2002-10-08
申请号：US09778318
申请日：2001-02-06
申请人： John T. Moore
发明人： John T. Moore
IPC分类号： H01L21304
CPC分类号： B24B37/013 , B24B49/16 , H01L21/31053 , Y10S257/915
摘要： A method and apparatus for endpointing a planarization process of a microelectronic substrate. In one embodiment, the microelectronic substrate can include a semiconductor base, a first material, such as an oxide, disposed on the base, a second material, such as a nitride, disposed on the first material to stiffen the first material, and an endpointing material, such as polysilicon, disposed on the second material. The endpointing material can have a hardness and/or a fracture resistance that is less than a hardness and/or a fracture resistance of the stiffening material and, in one embodiment, can have a coefficient of friction that is different than surrounding material of the microelectronic substrate so as to be detected when exposed to a planarizing medium.
摘要翻译：一种用于终点微电子衬底的平坦化处理的方法和装置。在一个实施例中，微电子衬底可以包括设置在基底上的半导体基底，第一材料，例如氧化物，设置在第一材料上以加固第一材料的第二材料，例如氮化物，以及终点材料，例如多晶硅，设置在第二材料上。端点材料可以具有小于硬化材料的硬度和/或耐断裂性的硬度和/或抗断裂性，并且在一个实施例中，可以具有与微电子的周围材料不同的摩擦系数以便当暴露于平坦化介质时被检测。

96. 发明授权

US06429151B1 Semiconductor wafer assemblies comprising silicon nitride, methods of forming silicon nitride, and methods of reducing stress on semiconductive wafers 有权
标题翻译：包括氮化硅的半导体晶片组件，形成氮化硅的方法以及减少半导体晶片上的应力的方法
公开(公告)号：US06429151B1
公开(公告)日：2002-08-06
申请号：US09619468
申请日：2000-07-19
申请人： John T. Moore , Scott J. DeBoer , Mark Fischer
发明人： John T. Moore , Scott J. DeBoer , Mark Fischer
IPC分类号： H01L2131
CPC分类号： H01L21/3185 , H01L21/32 , H01L21/76202
摘要： In one aspect, the invention includes a method of semiconductive wafer processing comprising forming a silicon nitride layer over a surface of a semiconductive wafer, the silicon nitride layer comprising at least two portions, one of said at least two portions generating a compressive force against the other of the at least two portions, and the other of the at least two portions generating a tensile force against the one of the at least two portions. In another aspect, the invention includes a method of reducing stress on semiconductive wafer, the semiconductive wafer having a pair of opposing surfaces and having more silicon nitride over one of the opposing surfaces than over the other of the opposing surfaces, the method comprising providing the silicon nitride over the one of the opposing surfaces to comprise a first portion, a second portion and a third portion, the first, second and third portions being elevationally displaced relative to one another, the second portion being between the first and third portions, the second portion having a greater stoichiometric amount of silicon than the first and third portions, the semiconductive wafer being subjected to less stress than if the silicon nitride over the one of the opposing surfaces had a constant stoichiometric amount of silicon throughout its thickness. In yet other aspects, the invention includes semiconductive wafer assemblies.
摘要翻译：在一个方面，本发明包括半导体晶片处理方法，包括在半导体晶片的表面上形成氮化硅层，所述氮化硅层包括至少两个部分，所述至少两个部分中的一个产生抵抗所述至少两个部分中的另一个，并且所述至少两个部分中的另一部分产生相对于所述至少两个部分中的一个部分的张力。在另一方面，本发明包括减少半导体晶片上的应力的方法，该半导体晶片具有一对相对的表面，并且在相对表面的一个之上具有比另一个相对表面更多的氮化硅，该方法包括提供所述相对表面中的一个上的氮化硅包括第一部分，第二部分和第三部分，所述第一部分，第二部分和第三部分相对于彼此正向移位，所述第二部分位于第一部分和第三部分之间，第二部分具有比第一和第三部分更大的化学计算量的硅，与相对表面上的一个相反的表面上的氮化硅在整个厚度上具有恒定的化学计量的硅时，半导体晶片受到的应力较小。在另一方面，本发明包括半导体晶片组件。

97. 发明授权

US06420268B2 Methods of forming materials within openings, and methods of forming isolation regions 有权
公开(公告)号：US06420268B2
公开(公告)日：2002-07-16
申请号：US09910340
申请日：2001-07-20
申请人： John T. Moore , Guy T. Blalock
发明人： John T. Moore , Guy T. Blalock
IPC分类号： H01L21302
CPC分类号： H01L21/76235 , H01L21/31053
摘要： In one aspect, the invention includes a method of forming a material within an opening, comprising: a) forming an etch-stop layer over a substrate, the etch-stop layer having an opening extending therethrough to expose a portion of the underlying substrate and comprising an upper corner at a periphery of the opening, the upper corner having a corner angle with a first degree of sharpness; b) reducing the sharpness of the corner angle to a second degree; c) after reducing the sharpness, forming a layer of material within the opening and over the etch-stop layer; and d) planarizing the material with a method selective for the material relative to the etch-stop layer to remove the material from over the etch-stop layer while leaving the material within the opening.

98. 发明授权

US06391710B1 Methods of forming capacitors 有权
标题翻译：形成电容器的方法
公开(公告)号：US06391710B1
公开(公告)日：2002-05-21
申请号：US09602832
申请日：2000-06-23
申请人： John T. Moore , Guy T. Blalock , Scott Jeffrey DeBoer
发明人： John T. Moore , Guy T. Blalock , Scott Jeffrey DeBoer
IPC分类号： H01L218242
CPC分类号： H01L28/40 , H01L21/31116 , H01L21/3146 , Y10S438/924 , Y10S438/97
摘要： In one aspect, the invention includes an etching process, comprising: a) providing a first material over a substrate, the first material comprising from about 2% to about 20% carbon (by weight); b) providing a second material over the first material; and c) etching the second material at a faster rate than the first material. In another aspect, the invention includes a capacitor forming method, comprising: a) forming a wordline over a substrate; b) defining a node proximate the wordline; c.) forming an etch stop layer over the wordline, the etch stop layer comprising carbon; d) forming an insulative layer over the etch stop layer; e) etching through the insulative layer to the etch stop layer to form an opening through the insulative layer; and e) forming a capacitor construction comprising a storage node, dielectric layer and second electrode, at least a portion of the capacitor construction being within the opening. In yet another aspect, the invention includes a semiconductive material assembly, comprising: a) a semiconductive substrate; and b) a layer over the semiconductive substrate, the layer comprising silicon, nitrogen and carbon.
摘要翻译：一方面，本发明包括蚀刻工艺，其包括：a）在衬底上提供第一材料，所述第一材料包含约2％至约20％的碳（重量）; b）在第一材料上提供第二材料; 以及c）以比所述第一材料更快的速率蚀刻所述第二材料。另一方面，本发明包括电容器形成方法，包括：a）在衬底上形成字线; b）定义靠近字线的节点; c）在所述字线上形成蚀刻停止层，所述蚀刻停止层包含碳; d）在所述蚀刻停止层上形成绝缘层; e）通过绝缘层蚀刻到蚀刻停止层以形成穿过绝缘层的开口; 以及e）形成包括存储节点，电介质层和第二电极的电容器结构，所述电容器结构的至少一部分在所述开口内。在另一方面，本发明包括半导体材料组件，其包括：a）半导体衬底; 以及b）半导体衬底上的层，该层包含硅，氮和碳。

99. 发明授权

US06271153B1 Semiconductor processing method and trench isolation method 有权
公开(公告)号：US06271153B1
公开(公告)日：2001-08-07
申请号：US09603848
申请日：2000-06-26
申请人： John T. Moore
发明人： John T. Moore
IPC分类号： H01L21469
CPC分类号： H01L21/76224 , H01L21/3221
摘要： The invention includes semiconductor processing methods, including trench isolation. In one implementation, an oxide layer is deposited over a substrate. The deposited oxide layer is exposed to a chlorine containing gas effective to getter metals outwardly therefrom. In one implementation, a dielectric layer, for example silicon dioxide, is plasma enhanced chemical vapor deposited over a substrate within a chamber comprising an internal metal surface under conditions effective to incorporate metal from the chamber surface within the dielectric layer. The dielectric layer is then exposed to a chlorine containing gas effective to getter at least some of said metal outwardly therefrom. In one implementation, a trench isolation method comprises forming a series of isolation trenches into a semiconductive substrate. Silicon dioxide is chemical vapor deposited to within the trenches, with the silicon dioxide comprising metal impurity therein. The silicon dioxide within the trenches is densified using an atmosphere comprising chlorine which is effective to remove metal impurity from the silicon dioxide. In one implementation, some dielectric isolation material is chemical vapor deposited to within the trenches. After the chemical vapor deposition, the substrate is exposed to oxidation conditions effective to oxidize the trench sidewalls, with most preferably there having been no dedicated trench sidewall oxidation step conducted prior to the chemical vapor depositing.

100. 发明授权

US06184571B2 Method and apparatus for endpointing planarization of a microelectronic substrate 有权
公开(公告)号：US06184571B2
公开(公告)日：2001-02-06
申请号：US09182111
申请日：1998-10-27
申请人： John T. Moore
发明人： John T. Moore
IPC分类号： H01L2906
CPC分类号： B24B37/013 , B24B49/16 , H01L21/31053 , Y10S257/915
摘要： A method and apparatus for endpointing a planarization process of a microelectronic substrate. In one embodiment, the microelectronic substrate can include a semiconductor base, a first material, such as an oxide, disposed on the base, a second material, such as a nitride, disposed on the first material to stiffen the first material, and an endpointing material, such as polysilicon, disposed on the second material. The endpointing material can have a hardness and/or a fracture resistance that is less than a hardness and/or a fracture resistance of the stiffening material and, in one embodiment, can have a coefficient of friction that is different than surrounding material of the microelectronic substrate so as to be detected when exposed to a planarizing medium.

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