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91. 发明授权

US07715243B2 Storage device employing a flash memory 失效
标题翻译：采用闪存的存储设备
公开(公告)号：US07715243B2
公开(公告)日：2010-05-11
申请号：US12000696
申请日：2007-12-17
申请人： Hajime Yamagami , Kouichi Terada , Yoshihiro Hayashi , Takashi Tsunehiro , Kunihiro Katayama , Kenichi Kaki , Takeshi Furuno
发明人： Hajime Yamagami , Kouichi Terada , Yoshihiro Hayashi , Takashi Tsunehiro , Kunihiro Katayama , Kenichi Kaki , Takeshi Furuno
IPC分类号： G11C7/10
CPC分类号： G11C29/765 , G06F3/0601 , G06F3/0616 , G06F3/0619 , G06F3/064 , G06F3/0659 , G06F3/0679 , G06F12/0246 , G06F2003/0694 , G06F2212/2022 , G11C16/102 , G11C16/349
摘要： A semiconductor disk wherein a flash memory into which data is rewritten in block unit is employed as a storage medium, the semiconductor disk including a data memory in which file data are stored, a substitutive memory which substitutes for blocks of errors in the data memory, an error memory in which error information of the data memory are stored, and a memory controller which reads data out of, writes data into and erases data from the data memory, the substitutive memory and the error memory. Since the write errors of the flash memory can be remedied, the service life of the semiconductor disk can be increased.
摘要翻译：采用其中以块为单位重写数据的闪存的半导体盘作为存储介质，该半导体盘包括存储有文件数据的数据存储器，代替数据存储器中的错误块的替换存储器，存储有数据存储器的错误信息的错误存储器，以及从数据存储器，替代存储器和错误存储器读取数据并将数据写入数据存储器，替代存储器和错误存储器的数据的存储器控制器。由于可以补救闪速存储器的写入错误，所以可以提高半导体盘的使用寿命。

92. 发明授权

US07549086B2 Memory card and its initial setting method 有权
标题翻译：存储卡及其初始设定方法
公开(公告)号：US07549086B2
公开(公告)日：2009-06-16
申请号：US11877500
申请日：2007-10-23
申请人： Hidefumi Oodate , Atsushi Shiraishi , Shigeo Kurakata , Kunihiro Katayama , Motoki Kanamori
发明人： Hidefumi Oodate , Atsushi Shiraishi , Shigeo Kurakata , Kunihiro Katayama , Motoki Kanamori
IPC分类号： G06F11/00
CPC分类号： G11C16/20
摘要： In the initial setting of a memory card 1, the flash check data FD stored in a flash memory 2 is read out, this data FD is compared with the operation check data FD11 stored previously in the ROM, the write check data FD12 stored in the ROM 4a is written, if a fault is not detected, to the flash memory 2, and this data is read again and is compared with the write check data. FD12 of the ROM 4a. When any fault is not detected in comparison of these data, the CPU determines that the flash memory 2 is normal. Moreover, if a fault is detected in the comparison of data, the CPU sets the reset process fault data to a register 5a to set a controller 3 to the sleep mode. When the command CMD is received during this period, data comparison is executed again.
摘要翻译：在存储卡1的初始设置中，读出存储在闪速存储器2中的闪存检查数据FD，将该数据FD与先前存储在ROM中的操作检查数据FD11进行比较，存储在存储卡1中的写入检查数据FD12 如果没有检测到故障，ROM 4a被写入闪速存储器2，并且该数据被再次读取并且与写检查数据进行比较。 ROM 4a的FD12。当比较这些数据时没有检测到任何故障时，CPU确定闪存2正常。此外，如果在比较数据中检测到故障，则CPU将复位处理故障数据设置为寄存器5a，以将控制器3设置为睡眠模式。当在此期间接收到命令CMD时，再次执行数据比较。

93. 发明申请

US20080301817A1 MEMORY CARD 有权
标题翻译：存储卡
公开(公告)号：US20080301817A1
公开(公告)日：2008-12-04
申请号：US12182123
申请日：2008-07-29
申请人： Satoshi Yoshida , Kunihiro Katayama , Akira Kanehire , Masaharu Ukeda
发明人： Satoshi Yoshida , Kunihiro Katayama , Akira Kanehire , Masaharu Ukeda
IPC分类号： G06F21/00
CPC分类号： G06F21/78 , G06F21/31 , G06F2221/2143
摘要： In order to protect the user security data, provided is a memory card capable of preventing the data leakage to a third party not having the access authority by imposing the limitation on the number of password authentications and automatically erasing the data. In a system comprised of a multimedia card and a host machine electrically connected to the multimedia card and controlling the operations of the multimedia card, a retry counter for storing the number of password authentication failures is provided and the upper limit of the number of failures is registered in a register. When passwords are repeatedly entered once, twice, . . . and n times and the retry counter which counts the entries reaches the upper limit of the number of failures, the data is automatically erased so as not to leave the data in the flash memory.
摘要翻译：为了保护用户安全数据，提供了一种能够通过对密码认证数量进行限制并自动擦除数据来防止数据泄漏给不具有访问权限的第三方的存储卡。在由多媒体卡和与多媒体卡电连接并控制多媒体卡的操作的主机构成的系统中，提供用于存储密码认证失败次数的重试计数器，故障次数的上限为注册登记。当密码重复输入一次，两次，。。。并且n次，对条目进行计数的重试计数器达到故障次数的上限，数据被自动擦除，以便不将数据留在闪存中。

94. 发明授权

US07343445B2 Non-volatile memory card and transfer interruption means 有权
标题翻译：非易失性存储卡和传输中断手段
公开(公告)号：US07343445B2
公开(公告)日：2008-03-11
申请号：US11541543
申请日：2006-10-03
申请人： Kunihiro Katayama , Motoki Kanamori , Atsushi Shikata , Hidefumi Oodate , Atsushi Shiraishi
发明人： Kunihiro Katayama , Motoki Kanamori , Atsushi Shikata , Hidefumi Oodate , Atsushi Shiraishi
IPC分类号： G06F12/00
CPC分类号： G06K19/07 , G11C16/102
摘要： A memory card is provided with a transfer control circuit, a write control circuit and a judging circuit. The transfer control circuit outputs a transfer flag signal during the data transfer. The write control circuit outputs an internal busy signal during the data write operation. The judging circuit outputs a transfer interruption signal when a card selection signal of the host is negated during the input of the transfer flat signal and also outputs a suspension signal when the card selection signal is negated during the input of the internal busy signal. A CPU invalidates the data being transfer to interrupt the transfer process upon reception of the transfer interruption signal and completes, upon reception of the suspension signal, the process being executed and stays in the waiting condition. Consequently, even when the timing signal not conforming to the standards is transferred, the host can select the optimum processing operation from the internal processing conditions and thereby execute the selected operation.
摘要翻译：存储卡设置有传送控制电路，写入控制电路和判断电路。传送控制电路在数据传送期间输出传送标志信号。写入控制电路在数据写入操作期间输出内部忙信号。当输入传送平面信号期间主机的卡选择信号被否定时，判断电路输出传送中断信号，并且当在内部忙信号的输入期间卡选择信号被否定时，输出暂停信号。 CPU在接收到传送中断信号时使传送数据中断传输处理，并且在接收到暂停信号时完成正在执行的处理并处于等待状态。因此，即使当不符合标准的定时信号被传送时，主机也可以从内部处理条件中选择最佳处理操作，从而执行所选择的操作。

95. 发明授权

US07305589B2 Memory card and its initial setting method 有权
标题翻译：存储卡及其初始设定方法
公开(公告)号：US07305589B2
公开(公告)日：2007-12-04
申请号：US10484043
申请日：2002-05-08
申请人： Hidefumi Oodate , Atsushi Shiraishi , Shigeo Kurakata , Kunihiro Katayama , Motoki Kanamori
发明人： Hidefumi Oodate , Atsushi Shiraishi , Shigeo Kurakata , Kunihiro Katayama , Motoki Kanamori
IPC分类号： G06F11/00
CPC分类号： G11C16/20
摘要： In the initial setting of a memory card 1, the flash check data FD stored in a flash memory 2 is read out, this data FD is compared with the operation check data FD11 stored previously in the ROM, the write check data FD12 stored in the ROM 4a is written, if a fault is not detected, to the flash memory 2, and this data is read again and is compared with the write check data FD12 of the ROM 4a. When any fault is not detected in comparison of these data, the CPU determines that the flash memory 2 is normal. Moreover, if a fault is detected in the comparison of data, the CPU sets the reset process fault data to a register 5a to set a controller 3 to the sleep mode. When the command CMD is received during this period, data comparison is executed again.
摘要翻译：在存储卡1的初始设置中，读出存储在闪速存储器2中的闪存检查数据FD，该数据FD与先前存储在ROM中的操作检查数据FD1＆lt; 1＆gt; 存储在ROM4a中的写入检查数据FD1＆lt; 2＆gt;如果没有检测到故障则被写入闪速存储器2，并且再次读取该数据并与写入检查进行比较 ROM4a的数据FD1 <2> 。当比较这些数据时没有检测到任何故障时，CPU确定闪存2正常。此外，如果在数据比较中检测到故障，则CPU将复位过程故障数据设置为寄存器5a以将控制器3设置为睡眠模式。当在此期间接收到命令CMD时，再次执行数据比较。

96. 发明申请

US20070070694A1 Storage device employing a flash memory 失效
公开(公告)号：US20070070694A1
公开(公告)日：2007-03-29
申请号：US11599308
申请日：2006-11-15
申请人： Hajime Yamagami , Kouichi Terada , Yoshihiro Hayashi , Takashi Tsunehiro , Kunihiro Katayama , Kenichi Kaki , Takeshi Furuno
发明人： Hajime Yamagami , Kouichi Terada , Yoshihiro Hayashi , Takashi Tsunehiro , Kunihiro Katayama , Kenichi Kaki , Takeshi Furuno
IPC分类号： G11C14/00
CPC分类号： G11C29/765 , G06F3/0601 , G06F3/0616 , G06F3/0619 , G06F3/064 , G06F3/0659 , G06F3/0679 , G06F12/0246 , G06F2003/0694 , G06F2212/2022 , G11C16/102 , G11C16/349
摘要： A semiconductor disk wherein a flash memory into which data is rewritten in block unit is employed as a storage medium, the semiconductor disk including a data memory in which file data are stored, a substitutive memory which substitutes for blocks of errors in the data memory, an error memory in which error information of the data memory are stored, and a memory controller which reads data out of, writes data into and erases data from the data memory, the substitutive memory and the error memory. Since the write errors of the flash memory can be remedied, the service life of the semiconductor disk can be increased.

97. 发明授权

US07133961B2 Non-volatile memory card and transfer interruption means 有权
标题翻译：非易失性存储卡和传输中断手段
公开(公告)号：US07133961B2
公开(公告)日：2006-11-07
申请号：US10195400
申请日：2002-07-16
申请人： Kunihiro Katayama , Motoki Kanamori , Atsushi Shikata , Hidefumi Oodate , Atsushi Shiraishi
发明人： Kunihiro Katayama , Motoki Kanamori , Atsushi Shikata , Hidefumi Oodate , Atsushi Shiraishi
IPC分类号： G06F12/00
CPC分类号： G06K19/07 , G11C16/102
摘要： A memory card is provided with a transfer control circuit, a write control circuit and a judging circuit. The transfer control circuit outputs a transfer flag signal during the data transfer. The write control circuit outputs an internal busy signal during the data write operation. The judging circuit outputs a transfer interruption signal when a card selection signal of the host is negated during the input of the transfer flat signal and also outputs a suspension signal when the card selection signal is negated during the input of the internal busy signal. A CPU invalidates the data being transfer to interrupt the transfer process upon reception of the transfer interruption signal and completes, upon reception of the suspension signal, the process being executed and stays in the waiting condition. Consequently, even when the timing signal not conforming to the standards is transferred, the host can select the optimum processing operation from the internal processing conditions and thereby execute the selected operation.
摘要翻译：存储卡设置有传送控制电路，写入控制电路和判断电路。传送控制电路在数据传送期间输出传送标志信号。写入控制电路在数据写入操作期间输出内部忙信号。当输入传送平面信号期间主机的卡选择信号被否定时，判断电路输出传送中断信号，并且当在内部忙信号的输入期间卡选择信号被否定时，输出暂停信号。 CPU在接收到传送中断信号时使传送数据中断传输处理，并且在接收到暂停信号时完成正在执行的处理并处于等待状态。因此，即使当不符合标准的定时信号被传送时，主机也可以从内部处理条件中选择最佳处理操作，从而执行所选择的操作。

98. 发明申请

US20050162900A1 Storage device employing a flash memory 失效
公开(公告)号：US20050162900A1
公开(公告)日：2005-07-28
申请号：US11085508
申请日：2005-03-22
申请人： Hajime Yamagami , Kouichi Terada , Yoshihiro Hayashi , Takashi Tsunehiro , Kunihiro Katayama , Kenichi Kaki , Takeshi Furuno
发明人： Hajime Yamagami , Kouichi Terada , Yoshihiro Hayashi , Takashi Tsunehiro , Kunihiro Katayama , Kenichi Kaki , Takeshi Furuno
IPC分类号： G06F3/06 , G06F12/02 , G11C16/10 , G11C29/00 , G11C11/00
CPC分类号： G11C29/765 , G06F3/0601 , G06F3/0616 , G06F3/0619 , G06F3/064 , G06F3/0659 , G06F3/0679 , G06F12/0246 , G06F2003/0694 , G06F2212/2022 , G11C16/102 , G11C16/349
摘要： A semiconductor disk wherein a flash memory into which data is rewritten in block unit is employed as a storage medium, the semiconductor disk including a data memory in which file data are stored, a substitutive memory which substitutes for blocks of errors in the data memory, an error memory in which error information of the data memory are stored, and a memory controller which reads data out of, writes data into and erases data from the data memory, the substitutive memory and the error memory. Since the write errors of the flash memory can be remedied, the service life of the semiconductor disk can be increased.

99. 发明授权

US06728826B2 Semiconductor storage device in which commands are sequentially fed to a plurality of flash memories to continuously write data 失效
标题翻译：半导体存储装置，其中命令被顺序地馈送到多个闪存以连续地写入数据
公开(公告)号：US06728826B2
公开(公告)日：2004-04-27
申请号：US10387478
申请日：2003-03-14
申请人： Kenichi Kaki , Kunihiro Katayama , Takashi Tsunehiro
发明人： Kenichi Kaki , Kunihiro Katayama , Takashi Tsunehiro
IPC分类号： G06F1300
CPC分类号： G06F3/0688 , G06F3/061 , G06F3/0611 , G06F3/0613 , G06F3/0652 , G06F3/0656 , G06F3/0659 , G06F3/0679 , G11C16/102 , G11C16/32
摘要： A semiconductor storage apparatus such as a disk pack in which a controller sends a second write command or instruction while a write operation for a first write command or instruction is being carried out. The storage apparatus includes a plurality of flash memories which operate slower in writing data thereinto than the reading data therefrom, a write buffer memory in which data are temporarily held, a processor which controls the data writing operation and which transfers and analyzes commands and statuses, an address controller which generates physical addresses, a circuit which generates a writing supply voltage Vpp for the flash memories, a memory address bus, and a data bus. The semiconductor disk pack is connected to a standard bus in a personal computer or the like. The processor writes the data of one word into a desired one of the flash memories, and it continuously writes the data of one word into an accessible one of the other flash memories during a latency which extends until the desired flash memory becomes capable of writing the next data of one word thereinto.
摘要翻译：一种半导体存储装置，例如在执行用于第一写入命令或指令的写入操作时控制器发送第二写入命令或指令的盘组件。存储装置包括多个闪存，其写入数据比其读取数据慢，其中临时保存数据的写入缓冲存储器，控制数据写入操作并且传送和分析命令和状态的处理器，生成物理地址的地址控制器，产生闪速存储器的写入电源电压Vpp的电路，存储器地址总线和数据总线。半导体磁盘组件连接到个人计算机等中的标准总线。处理器将一个字的数据写入所需的一个闪速存储器中，并且在延迟期间持续地将一个字的数据写入可访问的另一个闪存中，直到期望的闪速存储器能够写入其中一个字的下一个数据。

100. 发明授权

US06421279B1 Flash memory control method and apparatus processing system therewith 有权
标题翻译：闪存控制方法和装置处理系统
公开(公告)号：US06421279B1
公开(公告)日：2002-07-16
申请号：US09927493
申请日：2001-08-13
申请人： Tsunehiro Tobita , Jun Kitahara , Takashi Tsunehiro , Kunihiro Katayama , Ryuichi Hattori , Yukihiro Seki , Hajime Yamagami , Takashi Totsuka , Takeshi Wada , Yosio Takaya , Manabu Saito , Kenichi Kaki , Takao Okubo , Takashi Kikuchi , Masamichi Kishi , Takeshi Suzuki , Shigeru Kadowaki
发明人： Tsunehiro Tobita , Jun Kitahara , Takashi Tsunehiro , Kunihiro Katayama , Ryuichi Hattori , Yukihiro Seki , Hajime Yamagami , Takashi Totsuka , Takeshi Wada , Yosio Takaya , Manabu Saito , Kenichi Kaki , Takao Okubo , Takashi Kikuchi , Masamichi Kishi , Takeshi Suzuki , Shigeru Kadowaki
IPC分类号： G11C800
CPC分类号： G11C29/765 , G06F3/0601 , G06F3/0613 , G06F3/0616 , G06F3/064 , G06F3/0644 , G06F3/0656 , G06F3/0679 , G06F3/068 , G06F11/1433 , G06F11/1441 , G06F12/08 , G06F12/0802 , G06F12/0866 , G06F2003/0694 , G06F2212/2022 , G06F2212/312 , G11C29/789 , G11C29/82
摘要： A semiconductor file system features a first nonvolatile memory electrically erasable, a second nonvolatile memory not electrically erasable, a volatile memory, a controller, and a control section which controls the controller wherein a physical address corresponding to a logical address specified from an external system is accessed. The first nonvolatile memory stores data for the external system to perform operations, first management information indicating correspondence between physical and logical addresses, and second management information indicating a state of the first nonvolatile memory. The second nonvolatile memory previously stores interface information. The controller determines a physical sector address. The control section is for controlling input/output of data from/to the external system and for temporarily storing write data into the first nonvolatile memory from the external system in the volatile memory and then transferring the write data from the volatile memory to the first nonvolatile memory.
摘要翻译：半导体文件系统具有电可擦除的第一非易失性存储器，不电可擦除的第二非易失性存储器，易失性存储器，控制器和控制部分，其控制控制器，其中对应于从外部系统指定的逻辑地址的物理地址是访问。第一非易失性存储器存储用于执行操作的外部系统的数据，指示物理和逻辑地址之间的对应关系的第一管理信息以及指示第一非易失性存储器的状态的第二管理信息。第二非易失性存储器先前存储接口信息。控制器确定物理扇区地址。控制部分用于控制来自/外部系统的数据的输入/输出，并用于从易失性存储器中的外部系统暂时将写数据存储到第一非易失性存储器中，然后将写入数据从易失性存储器传送到第一非易失性存储器记忆。

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