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91. 发明申请

US20120200346A1 Through-Hole-Vias In Multi-Layer Printed Circuit Boards 有权
公开(公告)号：US20120200346A1
公开(公告)日：2012-08-09
申请号：US13448787
申请日：2012-04-17
申请人： Moises Cases , Tae Hong Kim , Rohan U. Mandrekar , Nusrat I. Sherali
发明人： Moises Cases , Tae Hong Kim , Rohan U. Mandrekar , Nusrat I. Sherali
IPC分类号： H02J3/10 , H05K3/00
CPC分类号： H05K3/0094 , H05K1/0234 , H05K1/0242 , H05K1/0251 , H05K1/09 , H05K1/167 , H05K3/0047 , H05K3/244 , H05K3/429 , H05K2201/0391 , Y10T29/49126 , Y10T29/4913 , Y10T29/49155 , Y10T29/49165 , Y10T156/1057 , Y10T428/12528
摘要： Example multi-layer printed circuit boards (‘PCBs’) are described as well as methods of making and using such PCBs that include layers of laminate; at least one via hole traversing the layers of laminate, and a via conductor contained within the via hole, the via conductor comprising a used portion and an unused portion, the via conductor comprising copper coated with a metal having a conductivity lower than the conductivity of copper.

92. 发明申请

US20100073893A1 MINIMIZING PLATING STUB REFLECTIONS IN A CHIP PACKAGE USING CAPACITANCE 有权
标题翻译：使用电容最小化芯片包装中的镀层反射
公开(公告)号：US20100073893A1
公开(公告)日：2010-03-25
申请号：US12237444
申请日：2008-09-25
申请人： Bhyrav Murthy Mutnury , Moises Cases , Nanju Na , Tae Hong Kim
发明人： Bhyrav Murthy Mutnury , Moises Cases , Nanju Na , Tae Hong Kim
IPC分类号： H05K7/00 , H01L21/00
CPC分类号： H01L21/4853 , C25D5/02 , H01L24/73 , H01L2224/32225 , H01L2224/48227 , H01L2224/73265 , H01L2924/14 , H01L2924/15311 , H05K1/0231 , H05K1/162 , H05K3/242 , H05K2203/049 , H01L2924/00012 , H01L2924/00
摘要： Embodiments of the present invention are directed to shifting the resonant frequency in a high-frequency chip package away from an operational frequency by connecting a capacitance between an open-ended plating stub and ground. One embodiment provides a multi-layer substrate for interfacing a chip with a printed circuit board. A first outer layer provides a chip mounting location. A signal interconnect is spaced from the chip mounting location, and a signal trace extends from near the chip mounting location to the signal interconnect. A chip mounted at the chip mounting location may be connected to the signal trace by wirebonding. A plating stub extends from the signal interconnect, such as to a periphery of the substrate. A capacitor is used to capacitively couple the plating stub to a ground layer.
摘要翻译：本发明的实施例涉及通过连接开放式电镀短截线和接地之间的电容来将高频芯片封装中的谐振频率从工作频率移开。一个实施例提供了用于将芯片与印刷电路板接口的多层基板。第一外层提供了芯片安装位置。信号互连与芯片安装位置间隔开，并且信号迹线从芯片安装位置附近延伸到信号互连。安装在芯片安装位置的芯片可以通过引线键合连接到信号迹线。电镀短截线从信号互连延伸到衬底的周围。电容器用于将电镀端子电容耦合到接地层。

93. 发明申请

US20090144256A1 Workflow control in a resource hierarchy 审中-公开
标题翻译：资源层次结构中的工作流控制
公开(公告)号：US20090144256A1
公开(公告)日：2009-06-04
申请号：US11947382
申请日：2007-11-29
申请人： Moises Cases , Candice Leontine Coletrane , Daniel N. de Araujo , Bhyrav Murthy Mutnury , William Gabriel Pagan
发明人： Moises Cases , Candice Leontine Coletrane , Daniel N. de Araujo , Bhyrav Murthy Mutnury , William Gabriel Pagan
IPC分类号： G06F7/06
CPC分类号： G06Q10/06 , G06F16/24578
摘要： Illustrative embodiments provide a computer implemented method, an apparatus and a computer program product for workflow management control in a resource hierarchy. In one embodiment, the computer implemented method comprises, receiving data, from a plurality of target data sources, into a collection, and synthesizing the received data in the collection to establish a resource hierarchy. The collection is then queried, using criteria in a request for a resource from a requester to provide a selected resource from the collection, forming a response, the selected resource of the response being a best fit result, and returning the response to the requester.
摘要翻译：说明性实施例提供了一种用于在资源层级中进行工作流管理控制的计算机实现的方法，装置和计算机程序产品。在一个实施例中，计算机实现的方法包括从多个目标数据源接收数据到一个集合中，并且在该集合中合成所接收的数据以建立资源层次。然后，使用来自请求者的资源的请求中的标准来查询集合，以从集合提供所选择的资源，形成响应，所选择的响应资源是最佳拟合结果，并将响应返回给请求者。

94. 发明申请

US20070208463A1 Learning a predicted voltage to supply an electronic device based on dynamic voltage variation 审中-公开
标题翻译：基于动态电压变化学习预测电压以供应电子设备
公开(公告)号：US20070208463A1
公开(公告)日：2007-09-06
申请号：US11366881
申请日：2006-03-02
申请人： Gerald Bartley , Moises Cases , Daniel de Araujo , Mark Maxson
发明人： Gerald Bartley , Moises Cases , Daniel de Araujo , Mark Maxson
IPC分类号： G05D11/00
CPC分类号： G06F1/26
摘要： In an embodiment, a predicted voltage to supply to an electronic device is learned based on a dynamic voltage variation that occurs at the electronic device. The dynamic voltage variation occurs in response to the electronic device processing a functional event, and the predicted voltage is supplied to the electronic device in response to observing the functional event on a bus that is connected to the electronic device. In response to observing the dynamic voltage variation, the predicted voltage that is associated with the functional event is modified based on the dynamic voltage variation. Then, on the next occurrence of the functional event, the predicted voltage is supplied to the electronic device. In this way, voltage transients at the electronic device are controlled.
摘要翻译：在一个实施例中，基于在电子设备处发生的动态电压变化来学习向电子设备提供的预测电压。响应于电子设备处理功能事件而发生动态电压变化，并且响应于观察连接到电子设备的总线上的功能事件，将预测电压提供给电子设备。响应观察动态电压变化，基于动态电压变化修改与功能事件相关联的预测电压。然后，在下一次发生功能事件时，向电子设备提供预测电压。以这种方式，控制电子设备处的电压瞬变。

95. 发明授权

US5867010A Circuit and method for voltage level translation utilizing a bias generator 失效
标题翻译：使用偏置发生器进行电压转换的电路和方法
公开(公告)号：US5867010A
公开(公告)日：1999-02-02
申请号：US870285
申请日：1997-06-06
申请人： Fahd Hinedi , Moises Cases , Satyajit Dutta , Robert Heath Dennard
发明人： Fahd Hinedi , Moises Cases , Satyajit Dutta , Robert Heath Dennard
IPC分类号： G05F1/46 , G05F1/56
CPC分类号： G05F1/465
摘要： Circuit and method aspects for translating acceptable voltage levels from an external device to acceptable voltage levels of an internal device are provided. These aspects include coupling an input receiver between the external device and the internal device, the input receiver including a clamp device, and coupling a bias generator to the input receiver at the clamp device, wherein the bias generator ensures proper translation of a high level input signal from the external device by the input receiver. The bias generator further ensures that a predetermined maximum device voltage of the clamp device is not exceeded.
摘要翻译：提供了用于将外部设备的可接受电压电平转换为内部设备的可接受电压电平的电路和方法方面。这些方面包括在外部设备和内部设备之间耦合输入接收器，输入接收器包括钳位器件，以及将偏置发生器耦合到钳位器件处的输入接收器，其中偏置发生器确保高电平输入由外部设备通过输入接收器发出的信号。偏置发生器还确保不超过钳位装置的预定最大器件电压。

96. 发明授权

US5621902A Computer system having a bridge between two buses with a direct memory access controller and an alternative memory access controller 失效
标题翻译：计算机系统在具有直接存储器访问控制器的两条总线与备用存储器访问控制器之间具有桥接
公开(公告)号：US5621902A
公开(公告)日：1997-04-15
申请号：US351195
申请日：1994-11-30
申请人： Moises Cases , Richard G. Hofmann , Lance M. Venarchick
发明人： Moises Cases , Richard G. Hofmann , Lance M. Venarchick
IPC分类号： G06F13/40 , H01J13/00
CPC分类号： G06F13/4027
摘要： A computer system having a peripheral controller interconnect (PCI) bus and an industry standard architecture (ISA), with ISA compatible devices coupled to the ISA bus, is provided with a first bridge coupled between the PCI and ISA buses. The first bridge has a first direct memory access (DMA) control circuit for controlling DMA transfers with the ISA devices. In order to achieve expanded compatibility with other types of devices, the system is also provided with an expansion bus, such as a Microchannel bus, with Microchannel compatible devices coupled to the Microchannel bus. A second bridge is coupled between the PCI and the Microchannel buses. This second bridge has a second DMA control circuit that controls DMA transfers with the ISA devices and with the Microchannel devices. Software disables the first DMA control circuit such that only the second DMA control circuit controls DMA transfers within the computer system.
摘要翻译：具有连接到ISA总线的具有ISA兼容设备的外围控制器互连（PCI）总线和工业标准架构（ISA）的计算机系统具有耦合在PCI总线与ISA总线之间的第一桥接器。第一个桥具有用于控制与ISA设备的DMA传输的第一个直接存储器访问（DMA）控制电路。为了实现与其他类型设备的扩展兼容性，该系统还提供有扩展总线，例如微通道总线，其具有耦合到微通道总线的微通道兼容设备。第二个桥耦合在PCI和微通道总线之间。该第二个桥具有第二个DMA控制电路，用于控制与ISA设备和Microchannel设备的DMA传输。软件禁用第一DMA控制电路，使得仅第二DMA控制电路控制计算机系统内的DMA传输。

97. 发明授权

US4120035A Electrically reprogrammable transversal filter using charge coupled devices 失效
标题翻译：使用电荷耦合器件的电可重编程横向滤波器
公开(公告)号：US4120035A
公开(公告)日：1978-10-10
申请号：US825123
申请日：1977-08-16
申请人： Moises Cases , Fung Yuel Chang , Barry Jay Rubin
发明人： Moises Cases , Fung Yuel Chang , Barry Jay Rubin
IPC分类号： G06G7/16 , G11C27/04 , H01L21/339 , H01L29/76 , H01L29/762 , H03H15/02 , H03K5/159
CPC分类号： G11C27/04 , G06G7/16 , H01L29/76 , H03H15/02 , H03H2015/026
摘要： A charge coupled device analog multiplier is used to weigh the sampled and delayed signals for a transversal filter. The digital filter coefficients for the analog multiplier can be electrically programmed and therefore dynamic time-varying systems, such as matched filters, can be designed with reduced circuit complexity. The digital filter includes means for sampling without destroying an analog signal at various points and providing voltages proportional to each sampled signal. The voltages are separately applied to a charge coupled device analog multiplier which accepts the voltages and provides means for multiplying the digital filter coefficient by the analog voltage. The multiplied sample signal is then dumped into a means for summing all of the weighted sample signals to produce an analog signal modified by the digital filter coefficients.
摘要翻译：电荷耦合器件模拟乘法器用于对横向滤波器的采样和延迟信号进行称重。模拟乘法器的数字滤波器系数可以进行电气编程，因此可以设计具有降低的电路复杂度的动态时变系统，例如匹配滤波器。数字滤波器包括用于采样的装置，而不破坏各个点处的模拟信号并提供与每个采样信号成比例的电压。电压分别施加到接收电压的电荷耦合器件模拟乘法器，并提供将数字滤波器系数乘以模拟电压的装置。然后将相乘的采样信号转储成用于对所有加权采样信号求和的装置，以产生由数字滤波器系数修改的模拟信号。

98. 发明申请

US20120193135A1 Through-Hole-Vias In Multi-Layer Printed Circuit Boards 有权
标题翻译：多层印刷电路板中的通孔
公开(公告)号：US20120193135A1
公开(公告)日：2012-08-02
申请号：US13446727
申请日：2012-04-13
申请人： Moises Cases , Tae Hong Kim , Rohan U. Mandrekar , Nusrat I. Sherali
发明人： Moises Cases , Tae Hong Kim , Rohan U. Mandrekar , Nusrat I. Sherali
IPC分类号： H05K1/11
CPC分类号： H05K3/0094 , H05K1/0234 , H05K1/0242 , H05K1/0251 , H05K1/09 , H05K1/167 , H05K3/0047 , H05K3/244 , H05K3/429 , H05K2201/0391 , Y10T29/49126 , Y10T29/4913 , Y10T29/49155 , Y10T29/49165 , Y10T156/1057 , Y10T428/12528
摘要： Example multi-layer printed circuit boards (‘PCBs’) are described as well as methods of making and using such PCBs that include layers of laminate; at least one via hole traversing the layers of laminate, and a via conductor contained within the via hole, the via conductor comprising a used portion and an unused portion, the via conductor comprising copper coated with a metal having a conductivity lower than the conductivity of copper.
摘要翻译：描述了例如多层印刷电路板（“PCB”），以及制造和使用这种包括层压层的PCB的方法; 穿过层压体层的至少一个通孔，以及包含在通孔内的通孔导体，所述通孔导体包括使用部分和未使用部分，所述通孔导体包括涂覆有电导率低于铜。

99. 发明授权

US07987110B2 Managing organizational resources 失效
标题翻译：管理组织资源
公开(公告)号：US07987110B2
公开(公告)日：2011-07-26
申请号：US11828111
申请日：2007-07-25
申请人： Moises Cases , Candice Leontine Coletrane , Bhyrav Murthy Mutnury , Scott Lee Winters
发明人： Moises Cases , Candice Leontine Coletrane , Bhyrav Murthy Mutnury , Scott Lee Winters
IPC分类号： G06Q10/00
CPC分类号： G06Q30/02 , G06Q10/06311 , G06Q10/06315 , G06Q50/01
摘要： A computer implemented method, apparatus, and computer program product for managing organizational resources. The process combines social group data with management information data to form social network data, wherein social group data is derived from interactions among a plurality of users of a social group. The process analyzes the social network data to identify associations among the plurality of users, and generates a multidimensional social network model using the associations among the plurality of users. Thereafter, the process presents a set of recommendations for allocation of the organizational resources, wherein the set of recommendations are derived from the social network model.
摘要翻译：一种用于管理组织资源的计算机实现的方法，装置和计算机程序产品。该过程将社会群体数据与管理信息数据组合以形成社交网络数据，其中社交群组数据源自社交群体的多个用户之间的交互。该过程分析社交网络数据以识别多个用户之间的关联，并且使用多个用户之间的关联来生成多维社交网络模型。此后，该过程提出了一组关于组织资源分配的建议，其中一组建议源于社交网络模型。

100. 发明授权

US07701222B2 Method for validating printed circuit board materials for high speed applications 失效
标题翻译：用于高速应用的印刷电路板材料的验证方法
公开(公告)号：US07701222B2
公开(公告)日：2010-04-20
申请号：US11875001
申请日：2007-10-19
申请人： Moises Cases , Bradley Donald Herrman , Kent Barclay Howieson , Erdem Matoglu , Bhyrav Murthy Mutnury , Pravin Patel , Nam Huu Pham , Caleb James Wesley
发明人： Moises Cases , Bradley Donald Herrman , Kent Barclay Howieson , Erdem Matoglu , Bhyrav Murthy Mutnury , Pravin Patel , Nam Huu Pham , Caleb James Wesley
IPC分类号： G01K3/00 , G01J5/00 , G01K17/00 , G01R27/32
CPC分类号： G01N25/72 , G01J5/0096 , G01R31/2818 , G01R31/2837 , G01R31/309
摘要： A method for testing a printed circuit board to determining the dielectric loss associated with the circuit board material relative to a standard. Dielectric losses in the material generate heat when a high frequency electronic signal, such as a microwave frequency signal, is communicated through a microstrip that is embedded within the printed circuit board. The temperature or spectrum at the surface of printed circuit board is measured and compared against the temperature or spectrum of the standard to determine whether the material under test is acceptable. While various temperature measurement devices may be used, the temperature is preferably measured without contacting the surface, such as using an infrared radiation probe.
摘要翻译：一种用于测试印刷电路板以确定与电路板材料相关的介电损耗相对于标准的方法。当诸如微波频率信号的高频电子信号通过嵌入在印刷电路板内的微带传输时，材料中的介电损耗产生热量。测量印刷电路板表面的温度或光谱，并与标准品的温度或光谱进行比较，以确定被测材料是否可接受。尽管可以使用各种温度测量装置，但是优选地在不接触表面的情况下测量温度，例如使用红外辐射探针。

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