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91. 发明授权

US5439838A Method of thinning for EEPROM tunneling oxide device 失效
标题翻译： EEPROM隧道氧化器件的稀化方法
公开(公告)号：US5439838A
公开(公告)日：1995-08-08
申请号：US305559
申请日：1994-09-14
申请人： Ming-Tzong Yang
发明人： Ming-Tzong Yang
IPC分类号： H01L21/8247 , H01L21/266
CPC分类号： H01L27/11521 , H01L27/11524
摘要： A method of forming an EEPROM memory cell on a semiconductor substrate, comprises forming a first dielectric layer on the substrate, a gate electrode of a select transistor and a first layer of a floating gate electrode of an EEPROM device on the dielectric layer, ion implanted source/drain regions in the substrate adjacent to the gate electrode and the first layer of the floating gate electrode proximate to at least the periphery of the gate electrode and the first layer of the floating gate electrode. The central region of the ion implanted regions is between the gate electrode and the first layer of the floating gate electrode. A tunneling oxide layer is formed above the central region using the electrodes to form the boundaries of the tunneling oxide layer, a second layer of the floating gate electrode in contact with the first layer of the floating gate electrode and in contact with the upper surface of the tunneling oxide layer, additional dielectric material over the upper surface of the device, and a control gate electrode deposited upon the surface of the additional dielectric material.
摘要翻译：一种在半导体衬底上形成EEPROM存储单元的方法，包括在衬底上形成第一电介质层，在电介质层上形成选择晶体管的栅电极和EEPROM器件的浮置栅电极的第一层，离子注入邻近栅电极的衬底中的源极/漏极区域和靠近栅电极的周边和浮栅电极的第一层的浮置栅电极的第一层。离子注入区域的中心区域位于栅电极和浮栅电极的第一层之间。使用电极在中心区域上方形成隧道氧化物层，以形成隧道氧化物层的边界，浮置栅电极的第二层与浮栅电极的第一层接触并与隧道氧化物层，在器件的上表面上的附加电介质材料，以及沉积在附加电介质材料的表面上的控制栅电极。

92. 发明授权

US5364808A Method of making a buried bit line DRAM cell 失效
标题翻译：埋地位线DRAM单元
公开(公告)号：US5364808A
公开(公告)日：1994-11-15
申请号：US192364
申请日：1994-02-07
申请人： Ming-Tzong Yang , Chen-Chiu Hsue , Gary Hong
发明人： Ming-Tzong Yang , Chen-Chiu Hsue , Gary Hong
IPC分类号： H01L21/8242 , H01L27/108 , H01L21/266
CPC分类号： H01L27/10852 , H01L27/10808
摘要： Ions of dopant are implanted into predetermined locations in a doped semiconductor substrate in sufficient concentration to form a buried conductor regions. A thick dielectric layer overlies the surface of the doped substrate. A first polysilicon layer is formed and patterned on the silicon dioxide layer by a mask and etching to form conductor lines, covered by a dielectric. A second polysilicon layer is formed on the second dielectric layer and patterned to form a first capacitor plate. A third dielectric layer is formed on the surface of the second polysilicon layer. A third polysilicon layer is formed on the third dielectric layer and patterned to form a top capacitor plate. A layer of BPSG is deposited upon the third layer of polysilicon.
摘要翻译：掺杂剂的离子以足够的浓度注入掺杂半导体衬底中的预定位置以形成掩埋导体区域。厚电介质层覆盖在掺杂衬底的表面上。通过掩模和蚀刻在二氧化硅层上形成并图案化第一多晶硅层以形成由电介质覆盖的导体线。在第二电介质层上形成第二多晶硅层并构图以形成第一电容器板。在第二多晶硅层的表面上形成第三电介质层。在第三电介质层上形成第三多晶硅层并构图以形成顶部电容器板。 BPSG层沉积在第三层多晶硅上。

93. 发明授权

US5350700A Method of fabricating bipolar transistors with buried collector region 失效
标题翻译：制造具有埋地集电极区域的双极晶体管的方法
公开(公告)号：US5350700A
公开(公告)日：1994-09-27
申请号：US160243
申请日：1993-12-02
申请人： Ming-Tzong Yang , Chung-Cheng Wu
发明人： Ming-Tzong Yang , Chung-Cheng Wu
IPC分类号： H01L21/331 , H01L21/74 , H01L21/265
CPC分类号： H01L29/66272 , H01L21/74
摘要： A method of fabricating a bipolar transistor with a buried subcollector by forming a collector layer and a base layer in a semiconductor substrate. A polysilicon layer is deposited over the base layer and spaced emitter and base contact regions formed in the base layer. A mask is formed over the emitter and base contact regions and the substrate anisotropically etched to form pedestals with vertical sidewalls. A masking layer is formed on the vertical sidewalls, and a large angle ion implant used to introduce ions beneath the collector layer, thereby forming a subcollector region.
摘要翻译：一种通过在半导体衬底中形成集电极层和基极层来制造具有掩埋子集电极的双极晶体管的方法。在基底层上沉积多晶硅层，并且在基底层中形成间隔开的发射极和基极接触区域。在发射极和基极接触区域上形成掩模，并且各向异性蚀刻衬底以形成具有垂直侧壁的基座。掩模层形成在垂直侧壁上，并且大角度离子注入用于将离子引入集电极层下面，从而形成子集电极区域。

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