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91. 发明申请

US20070262975A1 Timing generating circuit, display apparatus, and portable terminal 有权
标题翻译：定时发生电路，显示装置和便携式终端
公开(公告)号：US20070262975A1
公开(公告)日：2007-11-15
申请号：US11880699
申请日：2007-07-24
申请人： Yoshitoshi Kida , Yoshiharu Nakajima , Toshikazu Maekawa
发明人： Yoshitoshi Kida , Yoshiharu Nakajima , Toshikazu Maekawa
IPC分类号： G06F3/038
CPC分类号： G06F1/3203 , G06F1/324 , G09G3/3648 , G09G3/3677 , G09G3/3688 , G09G2300/0408 , G09G2300/08 , G09G2310/0267 , G09G2310/027 , G09G2330/021 , Y02D10/126
摘要： A timing generating circuit with low power consumption and a small layout area, a display apparatus including the timing generating circuit as one peripheral driving circuit, and a portable terminal including the display apparatus as a display output section are provided. In the timing generating circuit, which is formed on an insulating substrate and generates output pulses SRFF1out to SRFFnout having different frequencies based on a master clock MCK, a clock generating circuit (11) generates an operating clock having a lower frequency than the master clock MCK frequency. Then, a counter section (12) operates based on this operating clock and successively outputs shifted pulses S/R1out to S/Rmount from shift registers (121-1) to (121-m). An output pulse generating section (13) generates output pulses SF1out to SFnout based on combinations of the shifted pulses S/R1out to S/Rmount.
摘要翻译：具有低功耗和小布局区域的定时发生电路，包括作为一个外围驱动电路的定时发生电路的显示装置和包括作为显示输出部分的显示装置的便携式终端。在定时发生电路中，形成在绝缘衬底上并基于主时钟MCK产生具有不同频率的输出脉冲SRFF1至SRFFnout，时钟发生电路（11）产生频率低于主器件的工作时钟时钟MCK频率。然后，基于该工作时钟，计数部（12）进行动作，从移位寄存器（121-1）〜（121-m）依次输出移位脉冲S / R 1〜S / Rmount。输出脉冲生成部（13）根据移位脉冲S / R 1 out〜S / R mount的组合，生成输出脉冲SF1〜SFnout。

92. 发明授权

US07209104B2 Display apparatus and portable terminal which uses D/A conversion circuit 有权
标题翻译：显示装置和使用D / A转换电路的便携式终端
公开(公告)号：US07209104B2
公开(公告)日：2007-04-24
申请号：US10442351
申请日：2003-05-21
申请人： Yoshiharu Nakajima , Yoshitoshi Kida
发明人： Yoshiharu Nakajima , Yoshitoshi Kida
IPC分类号： G09G3/36
CPC分类号： G09G3/3688 , G09G3/3648 , G09G3/3696 , G09G2310/0254 , G09G2310/027 , G09G2320/02
摘要： A black-level reference-voltage generation circuit is disposed in a vicinity of an input-and-output pad section, and a power-supply line for the black-level reference-voltage generation circuit is connected to a power-supply line for a reference-voltage generation circuit for the other gradation levels at a position in a vicinity of the input-and-output pad section. With this, the resistance of the wiring resistor of the power-supply line of the black-level reference-voltage generation circuit is made as low as it can be ignored. As a result, a voltage drop caused by the wiring resistor of a black-level reference voltage is eliminated.
摘要翻译：黑电平基准电压产生电路设置在输入输出焊盘部分附近，黑电平基准电压产生电路的电源线连接到电源线参考电压产生电路，用于在输入和输出焊盘部分附近的位置处的其它灰度级。由此，黑电平基准电压产生电路的电源线的布线电阻的电阻可以忽略不计。结果，消除了由黑电平参考电压引起的布线电阻的电压降。

93. 发明申请

US20070052649A1 Liquid crystal display device and mobile terminal 有权
标题翻译：液晶显示装置和移动终端
公开(公告)号：US20070052649A1
公开(公告)日：2007-03-08
申请号：US10559074
申请日：2004-06-04
申请人： Yoshiharu Nakajima , Yoshitoshi Kida
发明人： Yoshiharu Nakajima , Yoshitoshi Kida
IPC分类号： G09G3/36
CPC分类号： G09G3/3655 , G09G3/3614 , G09G2300/0408 , G09G2300/0876 , G09G2310/06 , G09G2320/0204 , G09G2320/06
摘要： A liquid crystal display is provided that allows miniaturization, cost lowering, thickness reduction, and saving of unnecessary spaces of the device, and enhancement of the reliability of the device. If a variable resistor is used to set the DC potential of a VCOM potential, miniaturization of a liquid crystal display is precluded since the size of the variable resistor is large. A DA converter (20) is used instead of a conventional variable resistor as a unit for setting (adjusting) the DC potential of a VCOM potential (counter electrode voltage), and the DA converter (20) is formed on the same glass substrate (11) by using the same process as those of a display area part (12), to thereby achieve miniaturization of the liquid crystal display.
摘要翻译：提供了允许小型化，降低成本，减小厚度并节省设备不必要空间并提高设备可靠性的液晶显示器。如果使用可变电阻器来设置VCOM电位的DC电位，则由于可变电阻器的尺寸大，所以不排除液晶显示器的小型化。使用DA转换器（20）代替传统的可变电阻器作为用于设置（调整）VCOM电位的DC电位（对电极电压）的单元，并且DA转换器（20）形成在同一玻璃基板（ 11）通过使用与显示区域部分（12）相同的处理，从而实现液晶显示器的小型化。

94. 发明授权

US07126376B2 Logic circuit, timing generation circuit, display device, and portable terminal 有权
标题翻译：逻辑电路，定时生成电路，显示装置和便携式终端
公开(公告)号：US07126376B2
公开(公告)日：2006-10-24
申请号：US10485374
申请日：2003-05-30
申请人： Yoshitoshi Kida , Yoshiharu Nakajima , Toshikazu Maekawa
发明人： Yoshitoshi Kida , Yoshiharu Nakajima , Toshikazu Maekawa
IPC分类号： H03K19/173 , H03K3/037
CPC分类号： G09G3/20 , G09G3/3648 , G09G5/18 , G09G2300/0408 , G09G2310/0289 , G09G2310/08
摘要： When a buffer is formed by using transistors having large element characteristic variations, the deviation of the timing between the input clock pulse and the reset pulse is likely to occur. When the deviation of the timing becomes larger, a malfunction is caused to occur, and an operation margin becomes smaller with respect to the variations of the element characteristics. In a timing generation circuit, which is formed on an insulating substrate and which has two TFFs (12, 13), for generating a dot clock DCK and a horizontal clock HCK whose frequencies are different in synchronization with a master clock MCK which is input external to the substrate, separate reset pulses drst and hrst are generated at a pulse generation circuit 15 with respect to the two TFFs (12, 13), and a resetting operation is performed at separate timings. Thus, a large operation margin can be ensured even when each circuit is formed by using TFTs having large element characteristic variations and a rough process rule.
摘要翻译：当通过使用具有大的元件特性变化的晶体管形成缓冲器时，可能会发生输入时钟脉冲与复位脉冲之间的定时偏差。当定时的偏差变大时，会发生故障，相对于元件特性的变化，操作余量变小。在形成在绝缘基板上并具有两个TFF（12,13）的定时产生电路中，用于产生点时钟DCK和频率与输入外部的主时钟MCK同步的频率不同的水平时钟HCK 在相对于两个TFF（12,13）的脉冲发生电路15处产生分离的复位脉冲drst和hrst，并且在单独的定时执行复位操作。因此，即使当通过使用具有大的元件特性变化的TFT和粗略的处理规则形成每个电路时，也可以确保大的操作余量。

95. 发明申请

US20060012557A1 Data processing circuit, display apparatus, and portable terminal 有权
标题翻译：数据处理电路，显示装置和便携终端
公开(公告)号：US20060012557A1
公开(公告)日：2006-01-19
申请号：US11207352
申请日：2005-08-19
申请人： Yoshiharu Nakajima , Yoshitoshi Kida , Hiroaki Ichikawa
发明人： Yoshiharu Nakajima , Yoshitoshi Kida , Hiroaki Ichikawa
IPC分类号： G09G3/36
CPC分类号： G09G3/3688 , G02F1/13394 , G09G2300/0408 , G09G2300/0417 , G09G2310/027 , G09G2310/0281 , G09G2310/0289 , G09G2310/0294 , G09G2330/021
摘要： When a data processing circuit is formed on an insulating substrate by using TFTs, it is difficult to process a data signal having a high data rate, such as digital display data, at a high speed. In a data processing circuit formed on an insulating substrate by using TFTs, a data signal having a small voltage amplitude input in series is increased in level to a data signal having a large voltage amplitude by a level shift circuit (11), the serial data signal having the large voltage amplitude is converted to parallel data signals by a serial-parallel conversion circuit (12), and then, the parallel data signals are reduced in level to data signals having a small voltage amplitude by level shift circuits (13A and 13B). Therefore, high-speed processing can be applied to digital data signals at a low power consumption.
摘要翻译：当通过使用TFT在绝缘基板上形成数据处理电路时，难以高速处理诸如数字显示数据的数据速率高的数据信号。在通过使用TFT形成在绝缘基板上的数据处理电路中，串联输入的电压振幅小的数据信号通过电平移位电路（11）增加到电压振幅较大的数据信号，串行数据具有大电压幅度的信号通过串行 - 并行转换电路（12）被转换为并行数据信号，然后并行数据信号通过电平移位电路（13A和 13 B）。因此，可以以低功耗将高速处理应用于数字数据信号。

96. 发明授权

US06894674B2 Timing generation circuit for display apparatus and display apparatus incorporating the same 有权
标题翻译：显示装置的定时发生电路及其结合的显示装置
公开(公告)号：US06894674B2
公开(公告)日：2005-05-17
申请号：US10182600
申请日：2001-12-06
申请人： Yoshiharu Nakajima , Yasuhito Maki , Toshikazu Maekawa
发明人： Yoshiharu Nakajima , Yasuhito Maki , Toshikazu Maekawa
IPC分类号： G09G3/20 , G09G3/30 , G09G3/36 , G09G5/00
CPC分类号： G09G3/2011 , G09G3/30 , G09G3/3677 , G09G3/3688 , G09G3/3696 , G09G2300/0408 , G09G2300/08 , G09G2310/027 , G09G2310/0294 , G09G2310/06
摘要： A timing generation circuit (15) is formed integrally on the same glass substrate (11) together with a display area section (12) similarly to an H driver (13U) and a V driver (14), and timing pulses to be used by the H driver (13U) and the V driver (14) are produced based on timing data produced by a shift register (31U) of the H driver (13U) and a shift register (14A) of the V driver (14). The invention thereby provides a timing generation circuit which can contribute to miniaturization and reduction of the cost of the set and a display apparatus of the active matrix type in which the timing generation circuit is incorporated.
摘要翻译：与H驱动器（13U）和V驱动器（14）类似，定时产生电路（15）与显示区域部分（12）一体地形成在同一玻璃基板（11）上，并且使用定时脉冲基于H驱动器（13U）的移位寄存器（31U）和V驱动器（13U）的移位寄存器（14A）产生的定时数据，由H驱动器（13U）和V驱动器（14）（14）。因此，本发明提供了一种定时生成电路，其可以有助于小型化和降低该组件的成本以及其中结合有定时产生电路的有源矩阵型的显示装置。

97. 发明申请

US20050024313A1 Data processing circuit, display device, and mobile terminal 有权
标题翻译：数据处理电路，显示设备和移动终端
公开(公告)号：US20050024313A1
公开(公告)日：2005-02-03
申请号：US10485293
申请日：2003-05-28
申请人： Yoshiharu Nakajima , Yoshitoshi Kida , Hiroaki Ichikawa
发明人： Yoshiharu Nakajima , Yoshitoshi Kida , Hiroaki Ichikawa
IPC分类号： G02F1/1343 , G02F1/133 , G02F1/1339 , G09G3/20 , G09G3/36
CPC分类号： G09G3/3688 , G02F1/13394 , G09G2300/0408 , G09G2300/0417 , G09G2310/027 , G09G2310/0281 , G09G2310/0289 , G09G2310/0294 , G09G2330/021
摘要： When a data processing circuit is formed on an insulating substrate by using TFTs, it is difficult to process a data signal having a high data rate, such as digital display data, at a high speed. In a data processing circuit formed on an insulating substrate by using TFTs, a data signal having a small voltage amplitude input in series is increased in level to a data signal having a large voltage amplitude by a level shift circuit (11), the serial data signal having the large voltage amplitude is converted to parallel data signals by a serial-parallel conversion circuit (12), and then, the parallel data signals are reduced in level to data signals having a small voltage amplitude by level shift circuits (13A and 13B). Therefore, high-speed processing can be applied to digital data signals at a low power consumption.
摘要翻译：当通过使用TFT在绝缘基板上形成数据处理电路时，难以高速处理诸如数字显示数据的数据速率高的数据信号。在通过使用TFT形成在绝缘基板上的数据处理电路中，串联输入的电压振幅小的数据信号通过电平移位电路（11）增加到电压振幅较大的数据信号，串行数据具有大电压幅度的信号通过串并转换电路（12）被转换为并行数据信号，然后并行数据信号被电平移位电路（13A和13B）降低到电压振幅较小的数据信号）。因此，可以以低功耗将高速处理应用于数字数据信号。

98. 发明授权

US06795050B1 Liquid crystal display device 有权
标题翻译：液晶显示装置
公开(公告)号：US06795050B1
公开(公告)日：2004-09-21
申请号：US09383923
申请日：1999-08-26
申请人： Masumitsu Ino , Toshikazu Maekawa , Yoshiharu Nakajima , Hiroaki Ichikawa
发明人： Masumitsu Ino , Toshikazu Maekawa , Yoshiharu Nakajima , Hiroaki Ichikawa
IPC分类号： G09G336
CPC分类号： G09G3/3688 , G09G3/3614 , G09G3/3648 , G09G2310/0297 , G09G2320/0209
摘要： An active-matrix-type liquid crystal display device supplies signal potentials to signal lines of a liquid crystal display panel according to a time-division drive method using time-division switches. The low-level potential of select pulses to be supplied from a select pulse generating circuit to CMOS analog switches of the time-division switches is set to be lower than the low-level potential of a signal potential output from a horizontal drive circuit. With this arrangement, even if the signal potential of a non-selected signal line is decreased due to the crosstalk of a signal potential from a selected signal line to the non-selected signal line, the generation of insufficient contrast and non-uniformity of the luminance in the horizontal direction can be prevented. As a consequence, a high image quality is maintained.
摘要翻译：根据使用时分开关的时分驱动方法，有源矩阵型液晶显示装置向液晶显示面板的信号线提供信号电位。将从选择脉冲发生电路提供的选择脉冲的低电平电位设置为低于从水平驱动电路输出的信号电位的低电位电位。利用这种布置，即使由于从所选择的信号线到未选择的信号线的信号电位的串扰，未被选择的信号线的信号电位降低，产生不足的对比度和不均匀性可以防止水平方向的亮度。因此，保持高图像质量。

99. 发明授权

US06791539B2 Display, method for driving the same, and portable terminal 有权
标题翻译：显示，驱动方法和便携式终端
公开(公告)号：US06791539B2
公开(公告)日：2004-09-14
申请号：US09980251
申请日：2002-04-17
申请人： Yoshiharu Nakajima , Toshikazu Maekawa
发明人： Yoshiharu Nakajima , Toshikazu Maekawa
IPC分类号： G09G336
CPC分类号： G09G3/3688 , G09G2310/027 , G09G2310/0281 , G09G2310/0289 , G09G2310/0294 , G09G2310/04 , G09G2310/08 , G09G2330/021 , G09G2330/022
摘要： This invention provides a liquid crystal display device having a partial screen display mode, in which a latch control circuit (17) first stores white data or black data as color data of one line to latch circuits (121), (131) at the beginning of an image non-display period and then repeatedly reads out and outputs the color data to respective column lines in a display area (11) until the display period ends, thereby stopping the operation to write data to the latch circuits (121), (131) substantially during the entire image non-display period.
摘要翻译：本发明提供一种具有部分屏幕显示模式的液晶显示装置，其中锁存器控制电路（17）首先将白色数据或黑色数据作为一行的彩色数据存储在开始时的锁存电路（121），（131）的图像非显示时段，然后重复读出并将颜色数据输出到显示区域（11）中的各个列线直到显示周期结束，从而停止向锁存电路（121）写入数据的操作（ 131）基本上在整个图像非显示期间。

100. 发明授权

US06459395B1 Digital-to-analog converter and display unit with such digital-to-analog converter 有权
标题翻译：数模转换器和具有这种数模转换器的显示单元
公开(公告)号：US06459395B1
公开(公告)日：2002-10-01
申请号：US09697726
申请日：2000-10-27
申请人： Yoshitoshi Kida , Yoshiharu Nakajima , Toshikazu Maekawa
发明人： Yoshitoshi Kida , Yoshiharu Nakajima , Toshikazu Maekawa
IPC分类号： H03M166
CPC分类号： G09G3/3696 , G09G3/3655 , G09G3/3688 , G09G2300/0408 , G09G2310/027 , H03M1/765
摘要： In a reference-voltage-selection-type D/A converter, the channel widths of transistors of MOS switches of gradation selecting units are weighted depending on the selected gradation. Specifically, the channel width of the MOS switches Qn11, Qn12 is represented by W0, the channel width of the MOS switches Qn13, Qp11 is represented by W1, the channel width of the MOS switches Qp12, Qn14 is represented by W2, and the channel width of the MOS switches Qp13, Qp14 is represented by W3. The channel width W3 is set to a size corresponding to the maximum capacitance of a column line, and the other channel widths W0, W1, W2 are set to satisfy the relationship: W0
摘要翻译：在参考电压选择型D / A转换器中，灰度选择单元的MOS开关的晶体管的沟道宽度根据所选择的灰度进行加权。具体地，MOS开关Qn11，Qn12的沟道宽度由W0表示，MOS开关Qn13，Qp11的沟道宽度由W1表示，MOS开关Qp12，Qn14的沟道宽度由W2表示，沟道 MOS开关Qp13，Qp14的宽度由W3表示。通道宽度W3被设置为与列线的最大电容相对应的尺寸，并且另一个通道宽度W0，W1，W2被设置为满足关系：W0

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