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91. 发明授权

US06839828B2 SIMD datapath coupled to scalar/vector/address/conditional data register file with selective subpath scalar processing mode 失效
标题翻译： SIMD数据路径耦合到具有选择性子路径标量处理模式的标量/向量/地址/条件数据寄存器文件
公开(公告)号：US06839828B2
公开(公告)日：2005-01-04
申请号：US09929805
申请日：2001-08-14
申请人： Michael Karl Gschwind , Harm Peter Hofstee , Martin Edward Hopkins
发明人： Michael Karl Gschwind , Harm Peter Hofstee , Martin Edward Hopkins
IPC分类号： G06F9/00 , G06F9/30 , G06F9/312 , G06F9/38 , G06F15/80
CPC分类号： G06F9/30043 , G06F9/30036 , G06F9/30109 , G06F9/3012 , G06F9/3885 , G06F9/3887
摘要： There is provided a processor designed to operate in a plurality of modes for processing vector and scalar instructions. Register files are each for storing scalar and vector data and address information. A parallel vector unit, coupled to the register files, includes functional units configurable to operate in a vector operation mode and a scalar operation mode. The vector unit includes an apparatus for tightly coupling the functional units to perform an operation specified by a current instruction. Under a vector operation mode, the vector unit performs, in parallel, a single vector operation on a plurality of data elements. The operations performed on the plurality of data elements are each performed by a different functional unit of the vector unit. Under a scalar operation mode, the vector unit performs a scalar operation on a data element received from the register files in a functional unit within the vector unit.
摘要翻译：提供了设计成以多种模式操作以用于处理向量和标量指令的处理器。寄存器文件分别用于存储标量和矢量数据和地址信息。耦合到寄存器文件的并行向量单元包括可配置为在向量操作模式和标量操作模式下操作的功能单元。向量单元包括用于紧密耦合功能单元以执行由当前指令指定的操作的装置。在向量操作模式下，向量单元并行地执行对多个数据元素的单向量操作。对多个数据元素执行的操作各自由矢量单元的不同功能单元执行。在标量运算模式下，矢量单元对从矢量单元内的功能单元中的寄存器文件接收到的数据元素执行标量运算。

92. 发明授权

US06820142B2 Token based DMA 有权
标题翻译：基于令牌的DMA
公开(公告)号：US06820142B2
公开(公告)日：2004-11-16
申请号：US09736356
申请日：2000-12-14
申请人： Harm Peter Hofstee , Ravi Nair , John-David Wellman
发明人： Harm Peter Hofstee , Ravi Nair , John-David Wellman
IPC分类号： G06F1328
CPC分类号： G06F13/28
摘要： A method and system for accessing a shared memory in a deterministic schedule. In one embodiment, a system comprises a plurality of processing elements and a system I/O controller where each processing element and system I/O controller comprises a DMA controller. The system further comprises a shared memory coupled to each of the plurality of processing elements where the shared memory comprises a master controller. The master controller may then issue tokens to DMA controllers to grant the right for the associated processing elements and system I/O controller to access the shared memory at deterministic points in time. Each token issued by the master controller grants access to the shared memory for a particular duration of time at a unique deterministic point in time. A processing element or system I/O controller may access the shared memory upon the associated DMA controller relinquishing to the master controller the token that grants the right to access the shared memory at that particular time. The master controller may then reissue the relinquished token back to the DMA controller associated with the processing element or system I/O controller that accessed the shared memory if at a future designated time, e.g., 128 ns from the completion of the access to the shared memory, there does not exist a higher prioritized request, e.g., refresh the shared memory, to access the shared memory at that future designated time. The reissued token grants the right to access the shared memory at the future designated time.
摘要翻译：一种用于以确定性时间表访问共享存储器的方法和系统。在一个实施例中，系统包括多个处理元件和系统I / O控制器，其中每个处理元件和系统I / O控制器包括DMA控制器。该系统还包括耦合到多个处理元件中的每一个的共享存储器，其中共享存储器包括主控制器。然后，主控制器可以向DMA控制器发出令牌，以授予相关处理元件和系统I / O控制器在确定性时间点访问共享存储器的权利。由主控制器发出的每个令牌在一个特定的持续时间内在一个唯一的确定性时间点上授予对共享存储器的访问权限。处理元件或系统I / O控制器可以在关联的DMA控制器放弃主控制器时访问共享存储器，该令牌授权在特定时间访问共享存储器的权限。然后，如果在将来的指定时间（例如，从完成对共享的访问的完成）128ns，则主控制器然后可以将释放的令牌重新发送到与访问共享存储器的处理元件或系统I / O控制器相关联的DMA控制器存储器中，不存在更高优先级的请求，例如刷新共享存储器，以便在将来指定的时间访问共享存储器。重新签发的令牌授予在未来指定时间访问共享内存的权利。

93. 发明授权

US06728872B1 Method and apparatus for verifying that instructions are pipelined in correct architectural sequence 失效
标题翻译：用于验证指令以正确的架构顺序流水线的方法和装置
公开(公告)号：US06728872B1
公开(公告)日：2004-04-27
申请号：US09498931
申请日：2000-02-04
申请人： Brian King Flacks , Harm Peter Hofstee
发明人： Brian King Flacks , Harm Peter Hofstee
IPC分类号： G06F940
CPC分类号： G06F9/3802 , G06F9/3865 , G06F11/28
摘要： A method and apparatus for enabling the correct architectural sequencing of fetched instructions prior to allowing the instructions to complete in the processor pipeline to reduce the occurrence of pipeline breaks. A branch processing unit (BPU) is designed to perform sequence checks for the addresses of all instructions fetched into the pipeline (i.e., both in-line and branch instructions) by the instruction fetch unit (IFU). A first instruction is fetched. The address of the next instruction in the architectural sequence is computed and stored within the BPU. The next instruction is fetched and its address is compared to the next instruction address stored in BPU to determine if it is the correct address. If the next instruction address matches that of the architectural sequence, the instruction is permitted to “live” (i.e., continue through to completion). When the address does not match, the instruction is killed (i.e., not allowed to complete) and a new instruction is fetched by the IFU.
摘要翻译：一种方法和装置，用于在允许指令在处理器流水线中完成以减少流水线断裂的发生之前使获取的指令的正确结构排序。分支处理单元（BPU）被设计为执行由指令获取单元（IFU）获取到流水线中的所有指令的地址（即，在线和分支指令）的地址的序列检查。获取第一条指令。计算结构序列中下一条指令的地址并存储在BPU中。获取下一条指令，并将其地址与存储在BPU中的下一条指令地址进行比较，以确定其是否为正确的地址。如果下一个指令地址与架构序列的匹配，则该指令被允许“存活”（即继续完成）。当地址不匹配时，指令被杀死（即不允许完成），并且IFU提取新的指令。

94. 发明授权

US06708267B1 System and method in a pipelined processor for generating a single cycle pipeline stall 失效
标题翻译：流水线处理器中的系统和方法，用于生成单循环流水线停顿
公开(公告)号：US06708267B1
公开(公告)日：2004-03-16
申请号：US09498088
申请日：2000-02-04
申请人： Brian King Flacks , Harm Peter Hofstee , Osamu Takahashi
发明人： Brian King Flacks , Harm Peter Hofstee , Osamu Takahashi
IPC分类号： G06F930
CPC分类号： G06F9/3861 , G06F9/3838 , G06F9/3842 , G06F9/3867
摘要： A pipelined processor and method are disclosed for speculatively determining dependencies. The processor processes a plurality of instructions in order. A speculative detection circuit which takes multiple clock cycles to operate determines whether a dependency exists. The speculative detection circuit inserts a single-cycle pipeline stall only in response to a determination that a speculative dependency exists.
摘要翻译：公开了流水线处理器和方法，用于推测确定依赖性。处理器按顺序处理多个指令。采用多个时钟周期进行操作的推测检测电路确定是否存在依赖关系。推测检测电路仅在响应于存在推测依赖性的确定时插入单周期流水线停顿。

95. 发明授权

US06598153B1 Processor and method that accelerate evaluation of pairs of condition-setting and branch instructions 有权
标题翻译：加速评估条件设置和分支指令对的处理器和方法
公开(公告)号：US06598153B1
公开(公告)日：2003-07-22
申请号：US09458407
申请日：1999-12-10
申请人： Brian King Flachs , Harm Peter Hofstee , Kevin John Nowka
发明人： Brian King Flachs , Harm Peter Hofstee , Kevin John Nowka
IPC分类号： G06F938
CPC分类号： G06F9/30094 , G06F9/3842
摘要： A processor that promotes accelerated resolution of conditional branch instructions includes an instruction sequencer that fetches a plurality of instructions and a detector that detects, among the plurality of fetched instructions, a condition-setting instruction and a conditional branch instruction that depends upon the condition-setting instruction. The processor further includes a decoder that decodes the conditional branch instruction to produce a decoded condition type and an execution unit. In response to the detection of the condition-setting instruction and the conditional branch instruction, the execution unit resolves the conditional branch instruction by evaluating the condition-setting instruction and the decoded condition type in a single operation. Because the condition code bits are not computed or stored as an intermediate result as in prior art processors, branch resolution is accelerated.
摘要翻译：促进条件分支指令的加速分辨率的处理器包括取指定多个指令的指令定序器和检测器，其在多个取指令中检测条件设置指令和依赖于条件设置的条件转移指令指令。处理器还包括解码器，其解码条件分支指令以产生解码条件类型和执行单元。响应于条件设置指令和条件转移指令的检测，执行单元通过在单个操作中评估条件设置指令和解码条件类型来解析条件转移指令。由于条件码比特不像现有技术的处理器那样计算或存储为中间结果，所以分支分辨率被加速。

96. 发明授权

US06587941B1 Processor with improved history file mechanism for restoring processor state after an exception 失效
标题翻译：具有改进的历史文件机制的处理器，用于在异常之后恢复处理器状态
公开(公告)号：US06587941B1
公开(公告)日：2003-07-01
申请号：US09498089
申请日：2000-02-04
申请人： Brian King Flacks , Harm Peter Hofstee , Osamu Takahashi
发明人： Brian King Flacks , Harm Peter Hofstee , Osamu Takahashi
IPC分类号： G06F930
CPC分类号： G06F9/3836 , G06F9/3828 , G06F9/383 , G06F9/3832 , G06F9/384 , G06F9/3855 , G06F9/3857 , G06F9/3863
摘要： A pipelined processor and method are disclosed including an improved history file unit. The pipelined processor processes a plurality of instructions in order. A register file is included which includes a different read port coupled to each register field in an instruction buffer for reading data from the register file. A history file unit is included and is coupled to each of the read ports of the register file for receiving a copy of all data read from the register file.
摘要翻译：公开了一种流水线处理器和方法，其包括改进的历史文件单元。流水线处理器按顺序处理多个指令。包括寄存器文件，其包括耦合到用于从寄存器文件读取数据的指令缓冲器中的每个寄存器字段的不同读取端口。包括历史文件单元并且耦合到寄存器文件的每个读取端口，用于接收从寄存器文件读取的所有数据的副本。

97. 发明授权

US06335650B1 Method and apparatus for adjusting time delays in circuits with multiple operating supply voltages 有权
标题翻译：用于调整具有多个工作电源电压的电路中的时间延迟的方法和装置
公开(公告)号：US06335650B1
公开(公告)日：2002-01-01
申请号：US09670829
申请日：2000-09-28
申请人： David William Boerstler , Harm Peter Hofstee , Hung Cai Ngo , Kevin John Nowka
发明人： David William Boerstler , Harm Peter Hofstee , Hung Cai Ngo , Kevin John Nowka
IPC分类号： H03H1126
CPC分类号： H03K5/133 , H03K19/00384 , H03K19/018585 , H03K2005/0013
摘要： A method and apparatus for adjusting time delays in circuits with multiple operating supply voltages are disclosed. A voltage level detector and a delay means are coupled to a critical timing circuit of an integrated circuit capable of operating at multiple supply voltages. The voltage level detector detects a supply voltage at which the integrated circuit is operating. When the operating supply voltage of the integrated circuit changes from a first voltage level to a second voltage level, the voltage level detector sends a signal to the delay means and to a current enhancement circuit such that the delay means and current enhancement circuit can automatically modify the delay of the switching time of an output signal from the critical timing circuit.
摘要翻译：公开了一种用于调整具有多个工作电源电压的电路中的时间延迟的方法和装置。电压电平检测器和延迟装置耦合到能够在多个电源电压下工作的集成电路的关键定时电路。电压电平检测器检测集成电路正在工作的电源电压。当集成电路的工作电源电压从第一电压电平变化到第二电压电平时，电压电平检测器向延迟装置和当前增强电路发送信号，使得延迟装置和电流增强电路可以自动修改来自关键定时电路的输出信号的切换时间的延迟。

98. 发明授权

US06268660B1 Silicon packaging with through wafer interconnects 有权
标题翻译：通过晶圆互连的硅封装
公开(公告)号：US06268660B1
公开(公告)日：2001-07-31
申请号：US09263032
申请日：1999-03-05
申请人： Sang Hoo Dhong , Harm Peter Hofstee , Michael Jay Shapiro
发明人： Sang Hoo Dhong , Harm Peter Hofstee , Michael Jay Shapiro
IPC分类号： H01L2348
CPC分类号： H01L23/5384 , H01L23/481 , H01L2224/16 , H01L2924/01322 , H01L2924/10253 , H01L2924/00
摘要： A package for integrated circuit chips. The package contains a silicon substrate having a top surface and a bottom surface. The package also contains a first means for electrically connecting the integrated circuits to the substrate attached to the top surface of the substrate. A multilevel wiring is located at the top surface and is coupled to the first connecting means and serves as a communication link among a plurality of the first connecting means to enable multi-chip processing. A via containing means for coupling the multilevel wiring at the top surface to the bottom surface runs through the substrate from the bottom surface to the top surface. A second means is also present for connecting the coupling means at the bottom surface of the substrate with external components.
摘要翻译：集成电路芯片封装。该封装包含具有顶表面和底表面的硅衬底。封装还包含用于将集成电路电连接到附接到衬底顶表面的衬底的第一装置。多层布线位于顶表面并且耦合到第一连接装置，并且用作多个第一连接装置之间的通信链路，以实现多芯片处理。用于将上表面的多层布线耦合到底表面的通孔容纳装置从底表面到顶表面穿过基底。还存在用于将基板的底表面处的耦合装置与外部部件连接的第二装置。

99. 发明授权

US6038659A Method for using read-only memory to generate controls for microprocessor 失效
标题翻译：使用只读存储器生成微处理器控制的方法
公开(公告)号：US6038659A
公开(公告)日：2000-03-14
申请号：US968120
申请日：1997-11-12
申请人： Sang Hoo Dhong , Harm Peter Hofstee , David Meltzer , Joel Abraham Silberman
发明人： Sang Hoo Dhong , Harm Peter Hofstee , David Meltzer , Joel Abraham Silberman
IPC分类号： G06F9/30 , G06F9/318
CPC分类号： G06F9/382 , G06F9/30145 , G06F9/30196
摘要： A circuit for generating control signals used in a microprocessor has a storage array, such as a read-only memory (ROM) array, which contains a plurality of predefined logic patterns. An entry of the ROM array is selected, such as by the use of an address decoder, to choose a specific pattern, and the specific pattern is then modified based on a dynamic signal to generate an output control signal. The microprocessor may further predecode a base instruction using operation and operand source bits to yield a predecoded instruction having an address field whose value corresponds to the specific pattern. The dynamic signal can be based on whether an operand should be forwarded from a microprocessor component, and the specific pattern is then equivalent to a value for control signals required to execute an instruction when assuming that the operand should not be forwarded. Special control states can also be implemented, such as stall, halt, or scan data, through the use of particular code points in the ROM.
摘要翻译：用于产生在微处理器中使用的控制信号的电路具有存储阵列，诸如只读存储器（ROM）阵列，其包含多个预定逻辑模式。选择ROM阵列的入口，例如通过使用地址解码器来选择特定模式，然后基于动态信号修改特定模式以产生输出控制信号。微处理器可以进一步使用操作和源位来对基本指令进行预解码，以产生具有对应于特定模式的地址字段的预解码指令。动态信号可以基于操作数是否应该从微处理器组件转发，并且特定模式然后等于假设不应该转发操作数时执行指令所需的控制信号的值。还可以通过使用ROM中的特定代码点来实现特殊控制状态，例如停止，停止或扫描数据。

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