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91. 发明申请

US20100017766A1 Semiconductor Device Layout Including Cell Layout Having Restricted Gate Electrode Level Layout with Linear Shaped Gate Electrode Layout Features Defined with Minimum End-to-End Spacing and At Least Eight Transistors 有权
标题翻译：包括具有限制门极电极布局的单元格布局的半导体器件布局线性形栅极电极布局特征定义为最小端到端间隔和至少八个晶体管
公开(公告)号：US20100017766A1
公开(公告)日：2010-01-21
申请号：US12567528
申请日：2009-09-25
申请人： Scott T. Becker , Michael C. Smayling
发明人： Scott T. Becker , Michael C. Smayling
IPC分类号： G06F17/50
CPC分类号： H01L27/11807 , G06F17/5068 , G06F17/5072 , H01L21/28123 , H01L21/823871 , H01L23/5226 , H01L23/5283 , H01L27/0207 , H01L27/088 , H01L27/092 , H01L29/42372 , H01L29/42376 , H01L2027/11812 , H01L2027/11814 , H01L2027/11855 , H01L2027/11861 , H01L2027/11862 , H01L2027/11864 , H01L2027/11866 , H01L2027/11875 , H01L2027/11887 , H01L2027/11888 , H01L2924/0002 , H01L2924/00
摘要： A restricted layout region includes a diffusion level layout including diffusion region layout shapes that define at least one p-type diffusion region and at least one n-type diffusion region separated by a central inactive region. A gate electrode level layout is defined above the substrate portion to include linear-shaped layout features placed to extend in only a first parallel direction. Adjacent linear-shaped layout features that share a common line of extent in the first parallel direction are separated from each other by an end-to-end spacing that is substantially equal across the gate electrode level layout and that is minimized to an extent allowed by a semiconductor device manufacturing capability. A total number of PMOS and NMOS transistor devices in the restricted layout region is greater than or equal to eight. The restricted layout region corresponds to an entire gate electrode level of a cell layout.
摘要翻译：限制布局区域包括扩散级布局，其包括限定至少一个p型扩散区域的扩散区域布局形状和由中心非活性区域分隔开的至少一个n型扩散区域。栅电极层布局被限定在衬底部分上方，以包括仅在第一平行方向上延伸的线性布局特征。在第一并行方向上共享共同的范围的相邻线性布局特征通过栅电极级布局基本上相等的端到端间隔相互分开，并且被最小化到由半导体器件制造能力。限制布局区域中的PMOS和NMOS晶体管器件的总数大于或等于8。限制布局区域对应于单元布局的整个栅电极层。

92. 发明申请

US20100012986A1 Cell of Semiconductor Device Having Gate Electrode Conductive Structures Formed from Rectangular Shaped Gate Electrode Layout Features and Equal Number of PMOS and NMOS Transistors 有权
标题翻译：具有由矩形形栅极电极形成的栅电极导电结构的半导体器件的单元布局特性和等量的PMOS和NMOS晶体管
公开(公告)号：US20100012986A1
公开(公告)日：2010-01-21
申请号：US12571998
申请日：2009-10-01
申请人： Scott T. Becker , Michael C. Smayling
发明人： Scott T. Becker , Michael C. Smayling
IPC分类号： H01L27/088
CPC分类号： H01L27/11807 , G06F17/5068 , G06F17/5072 , H01L21/28123 , H01L21/823871 , H01L23/5226 , H01L23/5283 , H01L27/0207 , H01L27/088 , H01L27/092 , H01L29/42372 , H01L29/42376 , H01L2027/11812 , H01L2027/11814 , H01L2027/11855 , H01L2027/11861 , H01L2027/11862 , H01L2027/11864 , H01L2027/11866 , H01L2027/11875 , H01L2027/11887 , H01L2027/11888 , H01L2924/0002 , H01L2924/00
摘要： A cell of a semiconductor device includes a substrate portion formed to include a plurality of diffusion regions, including at least one p-type diffusion region and at least one n-type diffusion region separated from each other by one or more non-active regions. The cell includes a gate electrode level including a number of conductive features defined to extend in only a first parallel direction. Each of the conductive features within the gate electrode level is fabricated from a respective originating rectangular-shaped layout feature. Some of the conductive features form respective PMOS and/or NMOS transistor devices. A number of the PMOS transistor devices is equal to a number of the NMOS transistor devices in the gate electrode level of the cell. The cell also includes a number of interconnect levels formed above the gate electrode level.
摘要翻译：半导体器件的单元包括形成为包括多个扩散区域的基板部分，该多个扩散区域包括至少一个p型扩散区域和至少一个由一个或多个非有源区域彼此分离的n型扩散区域。电池包括包括多个导电特征的栅电极层，该导电特征限定为只在第一平行方向上延伸。栅极电极层中的每个导电特征由相应的起始矩形布局特征制成。一些导电特征形成相应的PMOS和/或NMOS晶体管器件。多个PMOS晶体管器件等于电池栅极电平中的NMOS晶体管器件的数量。电池还包括形成在栅极电极上方的多个互连电平。

93. 发明申请

US20100012984A1 Semiconductor Device Portion Having Sub-Wavelength-Sized Gate Electrode Conductive Structures Formed from Linear Shaped Gate Electrode Layout Features Defined with Minimum End-to-End Spacing and Having Equal Number of PMOS and NMOS Transistors 有权
标题翻译：具有亚波长尺寸的栅极电极的半导体器件部分由直线形栅极电极形成的导电结构由最小端到端间隔定义并具有等量的PMOS和NMOS晶体管的布局特征
公开(公告)号：US20100012984A1
公开(公告)日：2010-01-21
申请号：US12567586
申请日：2009-09-25
申请人： Scott T. Becker , Michael C. Smayling
发明人： Scott T. Becker , Michael C. Smayling
IPC分类号： H01L27/088
CPC分类号： H01L27/11807 , G06F17/5068 , G06F17/5072 , H01L21/28123 , H01L21/823871 , H01L23/5226 , H01L23/5283 , H01L27/0207 , H01L27/088 , H01L27/092 , H01L29/42372 , H01L29/42376 , H01L2027/11812 , H01L2027/11814 , H01L2027/11855 , H01L2027/11861 , H01L2027/11862 , H01L2027/11864 , H01L2027/11866 , H01L2027/11875 , H01L2027/11887 , H01L2027/11888 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device includes a substrate portion having a plurality of diffusion regions defined therein. A gate electrode level region is formed above the substrate portion to include conductive features defined to extend in only a first parallel direction. Adjacent ones of the conductive features that share a common line of extent in the first parallel direction are fabricated from respective originating layout features that are separated from each other by an end-to-end spacing having a substantially equal and minimum size across the gate electrode level region. A width of the conductive features is less than a wavelength of light used in a photolithography process for their fabrication. Some of the conductive features extend over the plurality of diffusion regions to form PMOS or NMOS transistor devices. A number of the PMOS transistor devices is equal to a number of the NMOS transistor devices in the gate electrode level region.
摘要翻译：半导体器件包括其中限定有多个扩散区的衬底部分。在基板部分上方形成栅极电平区域，以包括仅在第一平行方向上延伸的导电特征。通过相应的起始布局特征制造在第一平行方向上共享公共线的相邻导电特征的相邻的导电特征，所述起始布局特征通过跨越栅电极的基本相等和最小尺寸的端对端间隔彼此分开水平地区。导电特征的宽度小于用于其制造的光刻工艺中使用的光的波长。一些导电特征在多个扩散区域上延伸以形成PMOS或NMOS晶体管器件。多个PMOS晶体管器件等于栅电极电平区域中的NMOS晶体管器件的数量。

94. 发明申请

US20100012983A1 Semiconductor Device Portion Having Gate Electrode Conductive Structures Formed from Linear Shaped Gate Electrode Layout Features Defined with Minimum End-to-End Spacing and Having Equal Number of PMOS and NMOS Transistors 有权
标题翻译：半导体器件部分具有由直线形栅极电极形成的栅电极导电结构，具有最小端到端间隔和具有相等数量的PMOS和NMOS晶体管的布局特征
公开(公告)号：US20100012983A1
公开(公告)日：2010-01-21
申请号：US12567574
申请日：2009-09-25
申请人： Scott T. Becker , Michael C. Smayling
发明人： Scott T. Becker , Michael C. Smayling
IPC分类号： H01L27/088
CPC分类号： H01L27/11807 , G06F17/5068 , G06F17/5072 , H01L21/28123 , H01L21/823871 , H01L23/5226 , H01L23/5283 , H01L27/0207 , H01L27/088 , H01L27/092 , H01L29/42372 , H01L29/42376 , H01L2027/11812 , H01L2027/11814 , H01L2027/11855 , H01L2027/11861 , H01L2027/11862 , H01L2027/11864 , H01L2027/11866 , H01L2027/11875 , H01L2027/11887 , H01L2027/11888 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device includes a substrate portion having a plurality of diffusion regions defined therein. The semiconductor device includes a gate electrode level region including a number of conductive features defined to extend in only a first parallel direction. Adjacent ones of the number of conductive features that share a common line of extent in the first parallel direction are fabricated from respective originating layout features that are separated from each other by an end-to-end spacing having a size that is substantially equal across the gate electrode level region and is minimized to an extent allowed by a semiconductor device manufacturing capability. Some of the conductive features within the gate electrode level region extend over the plurality of diffusion regions to form PMOS or NMOS transistor devices. A number of the PMOS transistor devices is equal to a number of the NMOS transistor devices in the gate electrode level region.
摘要翻译：半导体器件包括其中限定有多个扩散区的衬底部分。该半导体器件包括包含多个导电特征的栅极电平区域，该导电特征被限定为只在第一平行方向上延伸。在第一并行方向上共享公共线路的相同数量的导电特征的相邻的导电特征由相应的起始布局特征制成，所述相互起始布局特征通过端对端间隔彼此分开，所述端对端间隔具有在栅极电极水平区域并且被最小化到半导体器件制造能力允许的程度。栅极电极区域内的一些导电特征在多个扩散区域上延伸以形成PMOS或NMOS晶体管器件。多个PMOS晶体管器件等于栅电极电平区域中的NMOS晶体管器件的数量。

95. 发明申请

US20100012981A1 Semiconductor Device Portion Having Gate Electrode Conductive Structures Formed from Linear Shaped Gate Electrode Layout Features Defined Along At Least Four Gate Electrode Tracks with Minimum End-to-End Spacing and Having Corresponding Non-Symmetric Diffusion Regions 有权
标题翻译：半导体器件部分具有由直线形栅极电极形成的栅极电极导电结构布局特征，沿着至少四个门极电极定义，具有最小端到端间距并具有相应的非对称扩散区域
公开(公告)号：US20100012981A1
公开(公告)日：2010-01-21
申请号：US12567542
申请日：2009-09-25
申请人： Scott T. Becker , Michael C. Smayling
发明人： Scott T. Becker , Michael C. Smayling
IPC分类号： H01L27/04 , H01L29/06
CPC分类号： H01L27/11807 , G06F17/5068 , G06F17/5072 , H01L21/28123 , H01L21/823871 , H01L23/5226 , H01L23/5283 , H01L27/0207 , H01L27/088 , H01L27/092 , H01L29/42372 , H01L29/42376 , H01L2027/11812 , H01L2027/11814 , H01L2027/11855 , H01L2027/11861 , H01L2027/11862 , H01L2027/11864 , H01L2027/11866 , H01L2027/11875 , H01L2027/11887 , H01L2027/11888 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device includes a substrate portion having a plurality of diffusion regions defined therein in a non-symmetrical manner relative to a virtual line defined to bisect the substrate portion. The semiconductor device includes a gate electrode level region including a number of conductive features defined to extend in only a first parallel direction. Adjacent ones of the number of conductive features that share a common line of extent in the first parallel direction are fabricated from respective originating layout features that are separated from each other by an end-to-end spacing having a size that is substantially equal across the gate electrode level region and is minimized to an extent allowed by a semiconductor device manufacturing capability. The gate electrode level region includes conductive features defined along at least four different virtual lines of extent in the first parallel direction.
摘要翻译：半导体器件包括：衬底部分，其具有限定在其中的多个扩散区域，相对于限定为将基底部分平分的虚拟线，以非对称的方式。该半导体器件包括包含多个导电特征的栅极电平区域，该导电特征被限定为只在第一平行方向上延伸。在第一并行方向上共享公共线路的相同数量的导电特征的相邻的导电特征由相应的起始布局特征制成，所述相互起始布局特征通过端对端间隔彼此分开，所述端对端间隔具有在栅极电极水平区域并且被最小化到半导体器件制造能力允许的程度。栅极电极级区域包括沿着沿着第一平行方向的至少四个不同虚拟线段限定的导电特征。

96. 发明申请

US20100006951A1 Semiconductor Device Portion Having Sub-193 Nanometers -Sized Gate Electrode Conductive Structures Formed from Rectangular Shaped Gate Electrode Layout Features and Having Equal Number of PMOS and NMOS Transistors 有权
标题翻译：具有亚193纳米的半导体器件部分由矩形形状的栅电极形成的栅极电极导电结构布局特征并具有相等数量的PMOS和NMOS晶体管
公开(公告)号：US20100006951A1
公开(公告)日：2010-01-14
申请号：US12563042
申请日：2009-09-18
申请人： Scott T. Becker , Michael C. Smayling
发明人： Scott T. Becker , Michael C. Smayling
IPC分类号： H01L27/088
CPC分类号： H01L27/0207 , H01L23/522 , H01L27/11807 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device is disclosed as having a substrate portion that includes a plurality of diffusion regions that include at least one p-type diffusion region and at least one n-type diffusion region. A gate electrode level region is formed above the substrate portion to include a number of conductive features defined to extend in only a first parallel direction. Each of the conductive features within the gate electrode level region is fabricated from a respective originating rectangular-shaped layout feature. Within a five wavelength photolithographic interaction radius within the gate electrode level region, a width size of the conductive features is less than 193 nanometers, which is the wavelength of light used in a photolithography process to fabricate the conductive features. The conductive features within the gate electrode level region form an equal number of PMOS and NMOS transistor devices.
摘要翻译：半导体器件被公开为具有包括至少一个p型扩散区域和至少一个n型扩散区域的多个扩散区域的衬底部分。栅极电极水平区域形成在衬底部分之上，以包括限定为仅沿第一平行方向延伸的多个导电特征。栅极电平区域内的导电特征中的每一个由相应的起始矩形布局特征制成。在栅极电极区域内的五波长光刻相互作用半径内，导电特征的宽度尺寸小于193纳米，这是在光刻工艺中用于制造导电特征的光的波长。栅极电平区域内的导电特征形成相等数量的PMOS和NMOS晶体管器件。

97. 发明申请

US20100006948A1 Semiconductor Device Portion Having Sub-193 Nanometers -Sized Gate Electrode Conductive Structures Formed from Rectangular Shaped Gate Electrode Layout Features and Having At Least Eight Transistors 有权
标题翻译：具有亚193纳米的半导体器件部分 - 由矩形形状的栅极电极形成的栅电极导电结构布局特征并具有至少八个晶体管
公开(公告)号：US20100006948A1
公开(公告)日：2010-01-14
申请号：US12563061
申请日：2009-09-18
申请人： Scott T. Becker , Michael C. Smayling
发明人： Scott T. Becker , Michael C. Smayling
IPC分类号： H01L27/088
CPC分类号： H01L27/11807 , G06F17/5068 , G06F17/5072 , H01L21/28123 , H01L21/823871 , H01L23/5226 , H01L23/5283 , H01L27/0207 , H01L27/088 , H01L27/092 , H01L29/42372 , H01L29/42376 , H01L2027/11812 , H01L2027/11814 , H01L2027/11855 , H01L2027/11861 , H01L2027/11862 , H01L2027/11864 , H01L2027/11866 , H01L2027/11875 , H01L2027/11887 , H01L2027/11888 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device includes a substrate portion that includes a plurality of diffusion regions that include at least one p-type diffusion region and at least one n-type diffusion region. A gate electrode level region is formed above the substrate portion to include a number of conductive features defined to extend in only a first parallel direction. Each of the conductive features within the gate electrode level region is fabricated from a respective originating rectangular-shaped layout feature. Within a five wavelength photolithographic interaction radius within the gate electrode level region, a width size of the conductive features is less than 193 nanometers, which is the wavelength of light used in a photolithography process to fabricate the conductive features. A total number of the PMOS transistor devices and the NMOS transistor devices in the gate electrode level region is greater than or equal to eight.
摘要翻译：半导体器件包括：衬底部分，其包括多个扩散区域，其包括至少一个p型扩散区域和至少一个n型扩散区域。栅极电极水平区域形成在衬底部分之上，以包括限定为仅沿第一平行方向延伸的多个导电特征。栅极电平区域内的导电特征中的每一个由相应的起始矩形布局特征制成。在栅极电极区域内的五波长光刻相互作用半径内，导电特征的宽度尺寸小于193纳米，这是在光刻工艺中用于制造导电特征的光的波长。栅极电极区域中的PMOS晶体管器件和NMOS晶体管器件的总数大于或等于8。

98. 发明申请

US20100006902A1 Semiconductor Device Portion Having Sub-Wavelength-Sized Gate Electrode Conductive Structures Formed from Rectangular Shaped Gate Electrode Layout Features Defined Along At Least Four Gate Electrode Tracks and Having Corresponding Non-Symmetric Diffusion Regions 有权
标题翻译：具有亚波长尺寸的栅极电极的半导体器件部分由矩形形状的栅电极形成的布置特征沿着至少四个栅极电极轨迹定义并具有相应的非对称扩散区域
公开(公告)号：US20100006902A1
公开(公告)日：2010-01-14
申请号：US12561243
申请日：2009-09-16
申请人： Scott T. Becker , Michael C. Smayling
发明人： Scott T. Becker , Michael C. Smayling
IPC分类号： H01L27/04 , H01L29/06
CPC分类号： H01L27/11807 , G06F17/5068 , G06F17/5072 , H01L21/28123 , H01L21/823871 , H01L23/5226 , H01L23/5283 , H01L27/0207 , H01L27/088 , H01L27/092 , H01L29/42372 , H01L29/42376 , H01L2027/11812 , H01L2027/11814 , H01L2027/11855 , H01L2027/11861 , H01L2027/11862 , H01L2027/11864 , H01L2027/11866 , H01L2027/11875 , H01L2027/11887 , H01L2027/11888 , H01L2924/0002 , H01L2924/00
摘要： A substrate portion of a semiconductor device is formed to include a plurality of diffusion regions that are defined in a non-symmetrical manner relative to a virtual line defined to bisect the substrate portion. A gate electrode level region is formed above the substrate portion to include a number of conductive features defined to extend in only a first parallel direction. Each of the number of conductive features within the gate electrode level region is fabricated from a respective originating rectangular-shaped layout feature. The conductive features within the gate electrode level region are defined along at least four different virtual lines of extent in the first parallel direction. A width size of the conductive features within the gate electrode level region is measured perpendicular to the first parallel direction and is less than a wavelength of light used in a photolithography process to fabricate the conductive features.
摘要翻译：半导体器件的衬底部分被形成为包括相对于被限定为平分衬底部分的虚拟线以非对称方式限定的多个扩散区域。栅极电极水平区域形成在衬底部分之上，以包括限定为仅沿第一平行方向延伸的多个导电特征。栅极电平区域内的多个导电特征中的每一个由相应的起始矩形布局特征制成。栅电极电平区域内的导电特征沿着沿着第一平行方向的至少四个不同的虚拟线限定。栅极电极区域内的导电特征的宽度尺寸是垂直于第一平行方向测量的，并且小于在光刻工艺中用于制造导电特征的光的波长。

99. 发明申请

US20100006899A1 Semiconductor Device Portion Having Gate Electrode Conductive Structures Formed from Rectangular Shaped Gate Electrode Layout Features and Having Equal Number of PMOS and NMOS Transistors 有权
标题翻译：半导体器件部分具有由矩形形状的栅极电极形成的栅电极导电结构布局特性并具有等量的PMOS和NMOS晶体管
公开(公告)号：US20100006899A1
公开(公告)日：2010-01-14
申请号：US12561247
申请日：2009-09-16
申请人： Scott T. Becker , Michael C. Smayling
发明人： Scott T. Becker , Michael C. Smayling
IPC分类号： H01L27/092 , H01L29/06 , H01L23/528
CPC分类号： H01L27/11807 , G06F17/5068 , G06F17/5072 , H01L21/28123 , H01L21/823871 , H01L23/5226 , H01L23/5283 , H01L27/0207 , H01L27/088 , H01L27/092 , H01L29/42372 , H01L29/42376 , H01L2027/11812 , H01L2027/11814 , H01L2027/11855 , H01L2027/11861 , H01L2027/11862 , H01L2027/11864 , H01L2027/11866 , H01L2027/11875 , H01L2027/11887 , H01L2027/11888 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device is disclosed as having a substrate portion that includes a plurality of diffusion regions that include at least one p-type diffusion region and at least one n-type diffusion region. A gate electrode level region is formed above the substrate portion to include a number of conductive features defined to extend in only a first parallel direction. Each of the conductive features within the gate electrode level region is fabricated from a respective originating rectangular-shaped layout feature. Some of the conductive features within the gate electrode level region extend over the p-type diffusion regions to form respective PMOS transistor devices. Also, some of the conductive features within the gate electrode level region extend over the n-type diffusion regions to form respective NMOS transistor devices. A number of the PMOS transistor devices is equal to a number of the NMOS transistor devices in the gate electrode level region.
摘要翻译：半导体器件被公开为具有包括至少一个p型扩散区域和至少一个n型扩散区域的多个扩散区域的衬底部分。栅极电极水平区域形成在衬底部分之上，以包括限定为仅沿第一平行方向延伸的多个导电特征。栅极电平区域内的导电特征中的每一个由相应的起始矩形布局特征制成。栅极电极区域中的一些导电特征在p型扩散区域上延伸以形成相应的PMOS晶体管器件。此外，栅极电极区域内的一些导电特征在n型扩散区域上延伸以形成相应的NMOS晶体管器件。多个PMOS晶体管器件等于栅电极电平区域中的NMOS晶体管器件的数量。

100. 发明授权

US07590968B1 Methods for risk-informed chip layout generation 有权
标题翻译：风险信息芯片布局生成方法
公开(公告)号：US07590968B1
公开(公告)日：2009-09-15
申请号：US11680552
申请日：2007-02-28
申请人： Scott T. Becker , Michael C. Smayling
发明人： Scott T. Becker , Michael C. Smayling
IPC分类号： G06F17/50
CPC分类号： G06F17/5068 , G06F17/5072
摘要： A chip layout is generated based on a quantified fabrication process capability. A minimum required value is selected for a fabrication process capability factor associated with a fabrication process to be performed on a layer sub-region within the chip. Design rules are determined for the layer sub-region within the chip that will enable the selected minimum required value for the fabrication process capability factor associated with the layer sub-region to be satisfied. A layout is then generated for the layer sub-region within the chip using the determined design rules associated with the layer sub-region. Fabrication process capability can be improved by restricting the design rules and generated layouts to a linear design style that requires features defined within the chip to be linear in shape and without bends. The linear design style enables optimization of photolithographic rendering without the need to consider two-dimensional optical effects.
摘要翻译：基于量化的制造工艺能力产生芯片布局。选择与在芯片内的层子区域执行的制造工艺相关联的制造工艺能力因素的最小所需值。确定芯片内的层子区域的设计规则，使得能够满足与层子区域相关联的制造工艺能力因素所选择的最小所需值。然后使用与层子区域相关联的确定的设计规则为芯片内的层子区域生成布局。可以通过将设计规则和生成的布局限制为线性设计风格来提高制造工艺能力，该线性设计风格需要在芯片内定义的特征是线性的，没有弯曲。线性设计风格可以优化光刻渲染，而无需考虑二维光学效果。

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