会员体验
专利管家(专利管理)
工作空间(专利管理)
风险监控(情报监控)
数据分析(专利分析)
侵权分析(诉讼无效)
联系我们
交流群
官方交流:
QQ群: 891211   
微信请扫码    >>>
现在联系顾问~
热词
    • 92. 发明授权
    • Heat exchanger
    • 热交换器
    • US07174948B2
    • 2007-02-13
    • US10493467
    • 2002-08-24
    • Martin SchindlerMichael Schmidt
    • Martin SchindlerMichael Schmidt
    • F01N5/02
    • F28D7/1684F01N3/043F01N5/02F28D21/0003F28F9/0236Y02T10/16Y02T10/20
    • The invention relates to an exhaust-gas thermal conductor (1), comprising a tube array with exhaust gas flowing therethrough and cooling medium flowing around the same. The tube array is welded to a tube base (5), connected to the housing (2). As a result of varying temperature effects on the tubes and on the housing (2) whilst operating the exhaust gas thermal conductor (1), thermal stresses, as a result of differing expansion of the tubes and the housing (2), occur. According to the invention, said stresses may be avoided, whereby slots (8-10) are arranged in the housing sleeve (2), which are externally sealed by means of a bellows.
    • 本发明涉及一种排气热导体(1),其包括具有流过其中的废气的管阵列和围绕其排出的冷却介质。 管阵列焊接到连接到壳体(2)的管座(5)上。 由于在操作废气导热体(1)时管子和壳体(2)上的温度影响变化的结果,由于管和壳体(2)的不同膨胀而产生热应力。 根据本发明,可以避免所述应力,由此在壳体套筒(2)中布置狭槽(8-10),外壳套筒(2)通过波纹管被外部密封。
    • 99. 发明申请
    • MULTI-LAYER GATE STACK STRUCTURE COMPRISING A METAL LAYER FOR A FET DEVICE, AND METHOD FOR FABRICATING THE SAME
    • 包含用于FET器件的金属层的多层栅格堆叠结构及其制造方法
    • US20050275046A1
    • 2005-12-15
    • US10865763
    • 2004-06-14
    • Matthias GoldbachFrank JakubowskiRalf KoepeChao-Wen LayKristin SchupkeMichael SchmidtCheng-Chih Huang
    • Matthias GoldbachFrank JakubowskiRalf KoepeChao-Wen LayKristin SchupkeMichael SchmidtCheng-Chih Huang
    • H01L21/28H01L21/3205H01L31/062
    • H01L21/28044
    • A multi-layer gate stack structure of a field-effect transistor device is fabricated by providing a gate electrode layer stack with a polysilicon layer, a transition metal interface layer, a nitride barrier layer and then a metal layer on a gate dielectric, wherein the transition metal is titanium, tantalum or cobalt. Patterning the gate electrode layer stack comprises a step of patterning the metal layer and the barrier layer with an etch stop on the surface of the interface layer. Exposed portions of the interface layer are removed and the remaining portions are pulled back from the sidewalls of the gate stack structure leaving divots extending along the sidewalls of the gate stack structure between the barrier layer and the polysilicon layer. A nitride liner encapsulating the metal layer, the barrier layer and the interface layer fills the divots left by the pulled-back interface layer. The nitride liner is opened before the polysilicon layer is patterned. As the requirement for an overetch into the polysilicon layer during the etch of the metal layer, the barrier layer and the interface layer is omitted, the height of the polysilicon layer can be reduced. The aspect ration of the gate stack structure is improved, the feasibility of pattern and fill processes enhanced and the range of an angle under which implants can be performed is extended.
    • 通过提供具有多晶硅层,过渡金属界面层,氮化物阻挡层,然后在栅极电介质上的金属层的栅电极层堆叠来制造场效应晶体管器件的多层栅极堆叠结构,其中, 过渡金属是钛,钽或钴。 对栅电极层堆叠进行图案化包括在界面层的表面上用蚀刻阻挡层图案化金属层和阻挡层的步骤。 界面层的暴露部分被去除,其余的部分从栅极叠层结构的侧壁被拉回,留下在阻挡层和多晶硅层之间的栅堆叠结构的侧壁延伸的纹理。 封装金属层,阻挡层和界面层的氮化物衬垫填充由拉回界面层留下的凹坑。 在将多晶硅层图案化之前打开氮化物衬垫。 作为在金属层的蚀刻期间进行多晶硅层的蚀刻的要求,省略了阻挡层和界面层,可以降低多晶硅层的高度。 提高了栅极堆叠结构的方面,增加了图案和填充过程的可行性,并且延长了可以进行植入的角度范围。