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91. 发明授权

US06764912B1 Passivation of nitride spacer 有权
标题翻译：氮化物间隔物钝化
公开(公告)号：US06764912B1
公开(公告)日：2004-07-20
申请号：US09919943
申请日：2001-08-02
申请人： John Clayton Foster , Eric N. Paton , Matthew S. Buynoski , Qi Xiang , Paul R. Besser , Paul L. King
发明人： John Clayton Foster , Eric N. Paton , Matthew S. Buynoski , Qi Xiang , Paul R. Besser , Paul L. King
IPC分类号： H01L21336
CPC分类号： H01L21/28194 , H01L29/51 , H01L29/511 , H01L29/513 , H01L29/517 , H01L29/518 , H01L29/665 , H01L29/6656
摘要： The formation of metal silicides in silicon nitride spacers on a gate electrode causes bridging between a gate electrode and the source and drain regions of a semiconductor device. The bridging is prevented by forming a thin layer of silicon oxide on the silicon nitride spacers prior to forming the metal silicide layers on the device.
摘要翻译：栅电极上的氮化硅间隔物中的金属硅化物的形成导致栅电极与半导体器件的源区和漏区之间的桥接。通过在器件上形成金属硅化物层之前在氮化硅间隔物上形成氧化硅薄层来防止桥接。

92. 发明授权

US06703308B1 Method of inserting alloy elements to reduce copper diffusion and bulk diffusion 失效
标题翻译：插入合金元素以减少铜扩散和体扩散的方法
公开(公告)号：US06703308B1
公开(公告)日：2004-03-09
申请号：US09994400
申请日：2001-11-26
申请人： Paul R. Besser , Matthew S. Buynoski , Sergey D. Lopatin , Alline F. Myers , Phin-Chin Connie Wang
发明人： Paul R. Besser , Matthew S. Buynoski , Sergey D. Lopatin , Alline F. Myers , Phin-Chin Connie Wang
IPC分类号： H01L2144
CPC分类号： H01L21/76843 , H01L21/76849 , H01L21/76859 , H01L21/76867
摘要： A method of fabricating an integrated circuit can include forming a barrier material layer along lateral side walls and a bottom of a via aperture which is configured to receive a via material that electrically connects a first conductive layer and a second conductive layer, implanting a first alloy element into the barrier material layer, and implanting a second alloy element after deposition of the via material. The implanted first alloy element makes the barrier material layer more resistant to copper diffusion. The implanted second alloy element diffuses to a top interface of the via material and reduces bulk diffusion from the via material.
摘要翻译：一种制造集成电路的方法可以包括沿着侧壁和形成通孔的底部形成阻挡材料层，所述通孔被配置为接收电连接第一导电层和第二导电层的通孔材料，注入第一合金元件进入阻挡材料层，以及在沉积通孔材料之后注入第二合金元件。植入的第一合金元素使得阻挡材料层更能抵抗铜扩散。植入的第二合金元件扩散到通孔材料的顶部界面并且减小从通孔材料的体积扩散。

93. 发明授权

US06613643B1 Structure, and a method of realizing, for efficient heat removal on SOI 有权
标题翻译：结构和一种实现SOI上高效散热的方法
公开(公告)号：US06613643B1
公开(公告)日：2003-09-02
申请号：US10155044
申请日：2002-05-24
申请人： Srinath Krishnan , Matthew S. Buynoski
发明人： Srinath Krishnan , Matthew S. Buynoski
IPC分类号： H01L2176
CPC分类号： H01L21/76254
摘要： In one embodiment, the present invention relates to a method of forming a silicon-on-insulator substrate, involving the steps of providing a first silicon substrate and a second silicon substrate; surface modifying at least one of the first silicon substrate and the second silicon substrate by forming a pattern thereon; forming a first insulation layer over the first silicon substrate to provide a first structure and a second insulation layer over the second silicon substrate to provide a second structure; bonding the first structure and the second structure together so that the first insulation layer is adjacent the second insulation layer; and removing a portion of the first or second silicon substrate thereby providing the silicon-on-insulator substrate.
摘要翻译：在一个实施例中，本发明涉及一种形成绝缘体上硅衬底的方法，包括提供第一硅衬底和第二硅衬底的步骤; 通过在其上形成图案来表面修饰第一硅衬底和第二硅衬底中的至少一个; 在所述第一硅衬底上形成第一绝缘层，以在所述第二硅衬底上方提供第一结构和第二绝缘层，以提供第二结构; 将第一结构和第二结构结合在一起，使得第一绝缘层与第二绝缘层相邻; 以及去除第一或第二硅衬底的一部分，从而提供绝缘体上硅衬底。

94. 发明授权

US06605513B2 Method of forming nickel silicide using a one-step rapid thermal anneal process and backend processing 有权
标题翻译：使用一步快速热退火工艺和后端加工形成硅化镍的方法
公开(公告)号：US06605513B2
公开(公告)日：2003-08-12
申请号：US09729699
申请日：2000-12-06
申请人： Eric N. Paton , Ercan Adem , Jacques J. Bertrand , Paul R. Besser , Matthew S. Buynoski , John Clayton Foster , Paul L. King , George Jonathan Kluth , Minh Van Ngo , Christy Mei-Chu Woo
发明人： Eric N. Paton , Ercan Adem , Jacques J. Bertrand , Paul R. Besser , Matthew S. Buynoski , John Clayton Foster , Paul L. King , George Jonathan Kluth , Minh Van Ngo , Christy Mei-Chu Woo
IPC分类号： H01L21336
CPC分类号： H01L29/665 , H01L21/28061 , H01L21/28518 , H01L29/4933
摘要： A self-aligned silicide process that can accommodate a low thermal budget and form silicide regions of small dimensions in a controlled reaction. In a first temperature treatment, nickel metal or nickel alloy is reacted with a silicon material to form at least one high resistance nickel silicide region. Unreacted nickel is removed. A dielectric layer is then deposited over a high resistance nickel silicide regions. In a second temperature treatment, the at least one high resistance nickel silicide region and dielectric layer are reacted at a prescribed temperature to form at least one low resistance silicide region and process the dielectric layer. Bridging between regions is avoided by the two-step process as silicide growth is controlled, and unreacted nickel between silicide regions is removed after the first temperature treatment. The processing of the high resistance nickel silicide regions and the dielectric layer are conveniently combined into a single temperature treatment.
摘要翻译：自对准硅化物工艺，可以适应低热预算，并在受控反应中形成小尺寸的硅化物区域。在第一温度处理中，镍金属或镍合金与硅材料反应以形成至少一个高电阻镍硅化物区域。去除未反应的镍。然后将电介质层沉积在高电阻镍硅化物区域上。在第二温度处理中，至少一个高电阻镍硅化物区域和电介质层在规定温度下反应以形成至少一个低电阻硅化物区域并处理介电层。通过控制硅化物生长的两步法避免区域之间的桥接，并且在第一温度处理之后去除硅化物区域之间的未反应的镍。将高电阻镍硅化物区域和电介质层的处理方便地组合成单温度处理。

95. 发明授权

US06440868B1 Metal gate with CVD amorphous silicon layer and silicide for CMOS devices and method of making with a replacement gate process 失效
标题翻译：具有CVD非晶硅层的金属栅极和用于CMOS器件的硅化物和用替代栅极工艺制造的方法
公开(公告)号：US06440868B1
公开(公告)日：2002-08-27
申请号：US09691259
申请日：2000-10-19
申请人： Paul R. Besser , Qi Xiang , Matthew S. Buynoski
发明人： Paul R. Besser , Qi Xiang , Matthew S. Buynoski
IPC分类号： H01L21302
CPC分类号： H01L21/28052 , H01L29/517 , H01L29/66545 , Y10S438/926
摘要： A semiconductor structure and method for making the same provides a metal gate on a silicon substrate. The gate includes a high dielectric constant on the substrate, and a chemical vapor deposited layer of amorphous silicon on the high k gate dielectric. The metal is then deposited on the CVD amorphous silicon layer. An annealing process forms silicide in the gate, with a layer of silicon remaining unreacted. The work function of the metal gate is substantially the same as a polysilicon gate due to the presence of the CVD amorphous silicon layer.
摘要翻译：半导体结构及其制造方法在硅衬底上提供金属栅极。该栅极包括在该基板上的高介电常数和在该高k栅极电介质上的非晶硅化学气相沉积层。然后将金属沉积在CVD非晶硅层上。退火工艺在栅极中形成硅化物，其中一层硅残留未反应。由于CVD非晶硅层的存在，金属栅极的功函数与多晶硅栅极基本相同。

96. 发明授权

US06417030B1 Leaky lower interface for reduction of floating body effect in SOI devices 失效
标题翻译：泄漏下界面，以减少SOI器件中的浮体效应
公开(公告)号：US06417030B1
公开(公告)日：2002-07-09
申请号：US09789134
申请日：2001-02-20
申请人： Matthew S. Buynoski , Donald L. Wollesen
发明人： Matthew S. Buynoski , Donald L. Wollesen
IPC分类号： H01L2100
CPC分类号： H01L29/78696 , H01L29/78618 , Y10S438/977
摘要： A silicon on insulator (SOI) device includes an electrically-conducting interface region along a portion of the interface between the insulator and a semiconductor layer atop the insulator. The electrically-conducting interface region provides a “leaky” electrical coupling between the body and source regions of a transistor device such as a “MOSFET”, thereby reducing floating body effects of the device. A method of forming such a semiconductor device includes forming the electrically-conducting interface region by damaging or implanting materials in the insulator and/or the semiconductor in the vicinity of the interface therebetween. The method may include producing a stepped interface region, such as by etching, in order to aid properly locating the transistor device relative to the electrically-conducting interface region.
摘要翻译：绝缘体上硅（SOI）器件包括沿着绝缘体与绝缘体上方的半导体层之间的界面的一部分的导电界面区域。导电界面区域在诸如“MOSFET”的晶体管器件的主体和源极区域之间提供“泄漏”电耦合，从而减少器件的浮体效应。形成这种半导体器件的方法包括通过在绝缘体和/或半导体之间的界面附近损坏或注入材料来形成导电界面区域。该方法可以包括例如通过蚀刻来产生阶梯式界面区域，以便有助于相对于导电界面区域适当地定位晶体管器件。

97. 发明授权

US06376343B1 Reduction of metal silicide/silicon interface roughness by dopant implantation processing 有权
标题翻译：通过掺杂剂注入处理减少金属硅化物/硅界面粗糙度
公开(公告)号：US06376343B1
公开(公告)日：2002-04-23
申请号：US09812695
申请日：2001-03-21
申请人： Matthew S. Buynoski , Paul R. Besser , Qi Xiang
发明人： Matthew S. Buynoski , Paul R. Besser , Qi Xiang
IPC分类号： H01L21425
CPC分类号： H01L29/6659 , H01L21/26513 , H01L21/28518 , H01L21/823814 , H01L29/665
摘要： Deleterious roughness of metal silicide/doped Si interfaces arising during conventional salicide processing for forming shallow-depth source and drain junction regions of MOS transistors and/or CMOS devices due to poor compatibility of particular dopants and metal suicides is avoided, or at least substantially reduced, by implanting a first (main) dopant species having relatively good compatibility with the metal silicide, such that the maximum concentration thereof is at a depth above the depth to which silicidation reaction occurs and implanting a second (auxiliary) dopant species having relatively poor compatibility with the metal silicide, wherein the maximum concentration thereof is less than that of the first (main) dopant and is at a depth below the depth to which silicidation reaction occurs. The invention enjoys particular utility in forming NiSi layers on As-doped Si substrates.
摘要翻译：避免了由于特定掺杂剂和金属硅化物的不良相容性而形成浅晶体管和/或CMOS器件的浅深度源极和漏极结区域的常规自对准硅化物处理期间产生的金属硅化物/掺杂Si界面的有缺陷的粗糙度，或至少大大降低通过植入与金属硅化物具有相对良好的相容性的第一（主要）掺杂剂物质，使得其最大浓度在高于发生硅化反应的深度的深度处，并且注入具有相对较差相容性的第二（辅助）掺杂剂种类金属硅化物，其中其最大浓度小于第一（主要）掺杂剂的最大浓度，并且处于低于发生硅化反应的深度的深度。本发明特别适用于在掺杂Si的衬底上形成NiSi层。

98. 发明授权

US06300203B1 Electrolytic deposition of dielectric precursor materials for use in in-laid gate MOS transistors 有权
标题翻译：电介质前体材料的电沉积用于嵌入栅极MOS晶体管
公开(公告)号：US06300203B1
公开(公告)日：2001-10-09
申请号：US09679872
申请日：2000-10-05
申请人： Matthew S. Buynoski , Paul R. Besser , Qi Xang , Paul L. King , Eric N. Paton
发明人： Matthew S. Buynoski , Paul R. Besser , Qi Xang , Paul L. King , Eric N. Paton
IPC分类号： H01L21336
CPC分类号： H01L21/28194 , H01L21/31683 , H01L29/517 , H01L29/66583
摘要： High quality dielectric layers, e.g., high-k dielectric layers comprised of at least one refractory or lanthanum series transition metal oxide or silicate, for use as gate insulator layers in in-laid metal gate MOS transistors and CMOS devices, are formed by electrolytically plating a metal or metal-based dielectric precursor layer comprising at least one refractory or lanthanum series transition metal, on a semiconductor substrate, typically a silicon-based substrate, and then reacting the precursor layer with oxygen or with oxygen and the semiconductor substrate to form the at least one refractory or lanthanum series transition metal oxide or silicate. The inventive methodology prevents, or at least substantially reduces, oxygen access to the substrate surface during at least the initial stage(s) of formation of the gate insulator layer, thereby minimizing deleterious formation of oxygen-induced surface states at the semiconductor substrate/gate insulator interface.
摘要翻译：通过电解电镀形成高质量的电介质层，例如由至少一种难熔或镧系列过渡金属氧化物或硅酸盐构成的高k电介质层，用作在叠层金属栅极MOS晶体管和CMOS器件中作为栅极绝缘体层在半导体衬底（通常为硅基衬底）上包含至少一种难熔或镧系过渡金属的金属或金属基电介质前体层，然后使前体层与氧或氧和半导体衬底反应，形成至少一种耐火材料或镧系列过渡金属氧化物或硅酸盐。本发明的方法在至少形成栅极绝缘体层的初始阶段期间防止或至少基本上减少氧接触到衬底表面，从而最小化半导体衬底/栅极处的氧诱导表面状态的有害形成绝缘子接口。

99. 发明授权

US06291278B1 Method of forming transistors with self aligned damascene gate contact 有权
标题翻译：用自对准镶嵌门接触形成晶体管的方法
公开(公告)号：US06291278B1
公开(公告)日：2001-09-18
申请号：US09303694
申请日：1999-05-03
申请人： Qi Xiang , Matthew S. Buynoski , Ming-Ren Lin
发明人： Qi Xiang , Matthew S. Buynoski , Ming-Ren Lin
IPC分类号： H01L21336
CPC分类号： H01L21/76897 , H01L21/28518 , H01L21/823871 , H01L29/66545
摘要： A method of fabricating a transistor having shallow source and drain extensions utilizes a self-aligned contact. The drain extensions are provided through an opening between a contact area and the gate structure. A high-K gate dielectric material can be utilized. P-MOS and N-MOS transistors can be created according to the disclosed method.
摘要翻译：制造具有浅源极和漏极延伸的晶体管的方法利用自对准接触。漏极延伸部分通过接触区域和栅极结构之间的开口提供。可以使用高K栅介电材料。可以根据所公开的方法创建P-MOS和N-MOS晶体管。

100. 发明授权

US06255147B1 Silicon on insulator circuit structure with extra narrow field transistors and method of forming same 有权
标题翻译：具有超窄场效应晶体管的绝缘体上硅电路结构及其形成方法
公开(公告)号：US06255147B1
公开(公告)日：2001-07-03
申请号：US09494997
申请日：2000-01-31
申请人： Matthew S. Buynoski
发明人： Matthew S. Buynoski
IPC分类号： H01L2184
CPC分类号： H01L29/66772 , H01L21/76264 , H01L21/76275 , H01L21/76283
摘要： A method of forming a narrow circuit component on a silicon on insulator (SOI) substrate includes silicon on insulator (SOI) substrate including forming a mask over the surface of a device layer to define an island region surrounded by a peripheral trench region. The mask is trimmed to reduce the size of the island and increase the size of the peripheral trench region. The peripheral trench region is then etched to isolate the island and a circuit component is formed therein
摘要翻译：在绝缘体上硅（SOI）衬底上形成窄电路元件的方法包括绝缘体上硅（SOI）衬底，包括在器件层的表面上形成掩模以限定由周边沟槽区域包围的岛状区域。修整掩模以减小岛的尺寸并增加外围沟槽区的尺寸。然后蚀刻外围沟槽区域以隔离岛，并且在其中形成电路部件

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