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91. 发明授权

US07361958B2 Nonplanar transistors with metal gate electrodes 有权
公开(公告)号：US07361958B2
公开(公告)日：2008-04-22
申请号：US10956279
申请日：2004-09-30
申请人： Justin K. Brask , Brian S. Doyle , Jack Kavalieros , Mark Doczy , Uday Shah , Robert S. Chau
发明人： Justin K. Brask , Brian S. Doyle , Jack Kavalieros , Mark Doczy , Uday Shah , Robert S. Chau
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L29/785 , H01L21/845 , H01L27/1211 , H01L29/0673 , H01L29/41791 , H01L29/66439 , H01L29/66545 , H01L29/66795 , Y10S438/926 , Y10S438/974
摘要： A semiconductor device comprising a semiconductor body having a top surface and a first and second laterally opposite sidewalls as formed on an insulating substrate is claimed. A gate dielectric is formed on the top surface of the semiconductor body and on the first and second laterally opposite sidewalls of the semiconductor body. A gate electrode is then formed on the gate dielectric on the top surface of the semiconductor body and adjacent to the gate dielectric on the first and second laterally opposite sidewalls of the semiconductor body. The gate electrode comprises a metal film formed directly adjacent to the gate dielectric layer. A pair of source and drain regions are then formed in the semiconductor body on opposite sides of the gate electrode.

92. 发明授权

US07709312B2 Methods for inducing strain in non-planar transistor structures 有权
标题翻译：在非平面晶体管结构中诱导应变的方法
公开(公告)号：US07709312B2
公开(公告)日：2010-05-04
申请号：US11540863
申请日：2006-09-29
申请人： Been-Yih Jin , Brian Doyle , Uday Shah , Jack Kavalieros
发明人： Been-Yih Jin , Brian Doyle , Uday Shah , Jack Kavalieros
IPC分类号： H01L21/336
CPC分类号： H01L29/785 , H01L29/66628 , H01L29/66795 , H01L29/7848 , H01L29/7851
摘要： Methods for inducing compressive strain in channel region of a non-planar transistor and devices and systems formed by such methods. In one embodiment, a method can include forming trenches in a semiconductor body adjacent to gate structure spacers. The semiconductor body can be situated on a substrate and in a different plane relative to the substrate. The gate structure can be situated on the semiconductor body and the silicon fin and perpendicular to the semiconductor body. After formation of the semiconductor body and the gate structure on the substrate, a dielectric material can be conformally deposited on the substrate and etched to form spacers on the semiconductor body and the gate structure. The substrate can be patterned and etched to form trenches in the semiconductor body adjacent to the spacers on the gate structure. A strain material can be introduced into the trenches.
摘要翻译：用于在非平面晶体管的沟道区域中诱导压缩应变的方法以及通过这种方法形成的器件和系统。在一个实施例中，一种方法可以包括在与栅极结构间隔物相邻的半导体本体中形成沟槽。半导体本体可以位于衬底上并且在相对于衬底的不同平面中。栅极结构可以位于半导体本体和硅片上并且垂直于半导体本体。在衬底上形成半导体本体和栅极结构之后，电介质材料可以共形沉积在衬底上并被蚀刻以在半导体本体和栅极结构上形成间隔物。可以对衬底进行图案化和蚀刻，以在与栅极结构上的间隔物相邻的半导体本体中形成沟槽。可以将应变材料引入到沟槽中。

93. 发明申请

US20080079094A1 Methods for inducing strain in non-planar transistor structures 有权
标题翻译：在非平面晶体管结构中诱导应变的方法
公开(公告)号：US20080079094A1
公开(公告)日：2008-04-03
申请号：US11540863
申请日：2006-09-29
申请人： Been-Yih Jin , Brian Doyle , Uday Shah , Jack Kavalieros
发明人： Been-Yih Jin , Brian Doyle , Uday Shah , Jack Kavalieros
IPC分类号： H01L29/76 , H01L21/336
CPC分类号： H01L29/785 , H01L29/66628 , H01L29/66795 , H01L29/7848 , H01L29/7851
摘要： Methods for inducing compressive strain in channel region of a non-planar transistor and devices and systems formed by such methods. In one embodiment, a method can include forming trenches in a semiconductor body adjacent to gate structure spacers. The semiconductor body can be situated on a substrate and in a different plane relative to the substrate. The gate structure can be situated on the semiconductor body and the silicon fin and perpendicular to the semiconductor body. After formation of the semiconductor body and the gate structure on the substrate, a dielectric material can be conformally deposited on the substrate and etched to form spacers on the semiconductor body and the gate structure. The substrate can be patterned and etched to form trenches in the semiconductor body adjacent to the spacers on the gate structure. A strain material can be introduced into the trenches.
摘要翻译：用于在非平面晶体管的沟道区域中诱导压缩应变的方法以及通过这种方法形成的器件和系统。在一个实施例中，一种方法可以包括在与栅极结构间隔物相邻的半导体本体中形成沟槽。半导体本体可以位于衬底上并且在相对于衬底的不同平面中。栅极结构可以位于半导体本体和硅片上并且垂直于半导体本体。在衬底上形成半导体本体和栅极结构之后，电介质材料可以共形沉积在衬底上并被蚀刻以在半导体本体和栅极结构上形成间隔物。可以对衬底进行图案化和蚀刻，以在与栅极结构上的间隔物相邻的半导体本体中形成沟槽。可以将应变材料引入到沟槽中。

94. 发明申请

US20070257325A1 Tri-gate device with conformal PVD workfunction metal on its three-dimensional body and fabrication method thereof 有权
标题翻译：具有保形PVD功能金属的三栅极器件及其制造方法
公开(公告)号：US20070257325A1
公开(公告)日：2007-11-08
申请号：US11418295
申请日：2006-05-03
申请人： Willy Rachmady , Brian Doyle , Jack Kavalieros , Uday Shah
发明人： Willy Rachmady , Brian Doyle , Jack Kavalieros , Uday Shah
IPC分类号： H01L21/336
CPC分类号： H01L29/78 , H01L29/4908 , H01L29/66795 , H01L29/785
摘要： A method of fabricating a tri-gate semiconductor device comprising a semiconductor body having an upper surface and side surfaces and a metal gate that has an approximately equal thickness on the upper and side surfaces. Embodiments of a tri-gate device with conformal physical vapor deposition workfunction metal on its three-dimensional body are described herein. Other embodiments may be described and claimed.
摘要翻译：一种制造三栅极半导体器件的方法，包括具有上表面和侧表面的半导体本体和在上表面和侧表面上具有大致相同厚度的金属栅极。本文描述了具有保形物理气相沉积功能金属的三栅极器件在其三维体上的实施例。可以描述和要求保护其他实施例。

95. 发明授权

US08987091B2 III-N material structure for gate-recessed transistors 有权
标题翻译：用于栅极 - 凹槽晶体管的III-N材料结构
公开(公告)号：US08987091B2
公开(公告)日：2015-03-24
申请号：US13976840
申请日：2011-12-23
申请人： Han Wui Then , Marko Radosavljevic , Uday Shah , Niloy Mukherjee , Ravi Pillarisetty , Benjamin Chu-Kung , Jack T. Kavalieros , Robert S. Chau
发明人： Han Wui Then , Marko Radosavljevic , Uday Shah , Niloy Mukherjee , Ravi Pillarisetty , Benjamin Chu-Kung , Jack T. Kavalieros , Robert S. Chau
IPC分类号： H01L21/336 , H01L31/00 , H01L29/423 , H01L29/51 , H01L29/66 , H01L29/778 , H01L29/40 , H01L29/20
CPC分类号： H01L29/7787 , H01L21/02241 , H01L21/02252 , H01L21/02255 , H01L21/02258 , H01L21/02458 , H01L21/0254 , H01L21/268 , H01L21/30604 , H01L21/30612 , H01L21/31111 , H01L29/2003 , H01L29/205 , H01L29/365 , H01L29/401 , H01L29/4236 , H01L29/512 , H01L29/518 , H01L29/66462
摘要： III-N transistors with recessed gates. An epitaxial stack includes a doped III-N source/drain layer and a III-N etch stop layer disposed between a the source/drain layer and a III-N channel layer. An etch process, e.g., utilizing photochemical oxidation, selectively etches the source/drain layer over the etch stop layer. A gate electrode is disposed over the etch stop layer to form a recessed-gate III-N HEMT. At least a portion of the etch stop layer may be oxidized with a gate electrode over the oxidized etch stop layer for a recessed gate III-N MOS-HEMT including a III-N oxide. A high-k dielectric may be formed over the oxidized etch stop layer with a gate electrode over the high-k dielectric to form a recessed gate III-N MOS-HEMT having a composite gate dielectric stack.
摘要翻译：具有凹入栅极的III-N晶体管。外延堆叠包括掺杂的III-N源极/漏极层和设置在源/漏层和III-N沟道层之间的III-N蚀刻停止层。蚀刻工艺，例如利用光化学氧化，选择性地蚀刻蚀刻停止层上的源极/漏极层。栅电极设置在蚀刻停止层上方以形成凹入栅III-N HEMT。蚀刻停止层的至少一部分可以用氧化蚀刻停止层上的栅电极氧化，用于包括III-N氧化物的凹陷栅III-N MOS-HEMT。可以在氧化的蚀刻停止层上形成高k电介质，并在高k电介质上形成栅电极，以形成具有复合栅电介质叠层的凹陷栅III-N MOS-HEMT。

96. 发明申请

US20140103397A1 TECHNIQUES FOR FORMING NON-PLANAR GERMANIUM QUANTUM WELL DEVICES 审中-公开
标题翻译：用于形成非平板锗量子阱器件的技术
公开(公告)号：US20140103397A1
公开(公告)日：2014-04-17
申请号：US14141648
申请日：2013-12-27
申请人： Ravi Pillarisetty , Jack T. Kavalieros , Willy Rachmady , Uday Shah , Benjamin Chu-Kung , Marko Radosavljevic , Niloy Mukherjee , Gilbert Dewey , Been Y. Jin , Robert S. Chau
发明人： Ravi Pillarisetty , Jack T. Kavalieros , Willy Rachmady , Uday Shah , Benjamin Chu-Kung , Marko Radosavljevic , Niloy Mukherjee , Gilbert Dewey , Been Y. Jin , Robert S. Chau
IPC分类号： H01L29/66 , H01L29/78
CPC分类号： H01L29/775 , B82Y10/00 , H01L21/76 , H01L29/0653 , H01L29/1054 , H01L29/155 , H01L29/165 , H01L29/267 , H01L29/517 , H01L29/66431 , H01L29/66439 , H01L29/66477 , H01L29/66795 , H01L29/66977 , H01L29/7782 , H01L29/7849 , H01L29/785 , H01L29/7851
摘要： Techniques are disclosed for forming a non-planar germanium quantum well structure. In particular, the quantum well structure can be implemented with group IV or III-V semiconductor materials and includes a germanium fin structure. In one example case, a non-planar quantum well device is provided, which includes a quantum well structure having a substrate (e.g. SiGe or GaAs buffer on silicon), a IV or III-V material barrier layer (e.g., SiGe or GaAs or AlGaAs), a doping layer (e.g., delta/modulation doped), and an undoped germanium quantum well layer. An undoped germanium fin structure is formed in the quantum well structure, and a top barrier layer deposited over the fin structure. A gate metal can be deposited across the fin structure. Drain/source regions can be formed at respective ends of the fin structure.
摘要翻译：公开了用于形成非平面锗量子阱结构的技术。特别地，量子阱结构可以用IV或III-V族半导体材料实现，并且包括锗鳍结构。在一个示例性情况下，提供了非平面量子阱器件，其包括具有衬底（例如硅上的SiGe或GaAs缓冲器），IV或III-V材料阻挡层（例如，SiGe或GaAs或 AlGaAs），掺杂层（例如，掺杂Δ/调制）和未掺杂的锗量子阱层。在量子阱结构中形成未掺杂的锗鳍结构，以及沉积在鳍结构上的顶部势垒层。栅极金属可以跨鳍片结构沉积。排水/源极区域可以形成在翅片结构的相应端部处。

97. 发明申请

US20140054548A1 TECHNIQUES FOR FORMING NON-PLANAR GERMANIUM QUANTUM WELL DEVICES 审中-公开
公开(公告)号：US20140054548A1
公开(公告)日：2014-02-27
申请号：US14069880
申请日：2013-11-01
申请人： Ravi Pillarisetty , Jack T. Kavalieros , Willy Rachmady , Uday Shah , Benjamin Chu-Kung , Marko Radosavljevic , Niloy Mukherjee , Gilbert Dewey , Been-Yih Jin , Robert S. Chau
发明人： Ravi Pillarisetty , Jack T. Kavalieros , Willy Rachmady , Uday Shah , Benjamin Chu-Kung , Marko Radosavljevic , Niloy Mukherjee , Gilbert Dewey , Been-Yih Jin , Robert S. Chau
IPC分类号： H01L29/775 , H01L21/76 , H01L29/66
CPC分类号： H01L29/775 , B82Y10/00 , H01L21/76 , H01L29/0653 , H01L29/1054 , H01L29/155 , H01L29/165 , H01L29/267 , H01L29/517 , H01L29/66431 , H01L29/66439 , H01L29/66477 , H01L29/66795 , H01L29/66977 , H01L29/7782 , H01L29/7849 , H01L29/785 , H01L29/7851
摘要： Techniques are disclosed for forming a non-planar germanium quantum well structure. In particular, the quantum well structure can be implemented with group IV or III-V semiconductor materials and includes a germanium fin structure. In one example case, a non-planar quantum well device is provided, which includes a quantum well structure having a substrate (e.g. SiGe or GaAs buffer on silicon), a IV or III-V material barrier layer (e.g., SiGe or GaAs or AlGaAs), a doping layer (e.g., delta/modulation doped), and an undoped germanium quantum well layer. An undoped germanium fin structure is formed in the quantum well structure, and a top barrier layer deposited over the fin structure. A gate metal can be deposited across the fin structure. Drain/source regions can be formed at respective ends of the fin structure.

98. 发明申请

US20120309173A1 ISOLATION FOR NANOWIRE DEVICES 有权
标题翻译：纳米器件的隔离
公开(公告)号：US20120309173A1
公开(公告)日：2012-12-06
申请号：US13563456
申请日：2012-07-31
申请人： Uday Shah , Benjamin Chu-Kung , Been-Yih Jin , Ravi Pillarisetty , Marko Radosavljevic , Willy Rachmady
发明人： Uday Shah , Benjamin Chu-Kung , Been-Yih Jin , Ravi Pillarisetty , Marko Radosavljevic , Willy Rachmady
IPC分类号： H01L21/20 , B82Y40/00
CPC分类号： H01L29/0665 , B82Y10/00 , B82Y40/00 , H01L21/02236 , H01L21/02532 , H01L21/02603 , H01L21/76224 , H01L29/0649 , H01L29/0653 , H01L29/0669 , H01L29/0673 , H01L29/66439 , H01L29/775 , H01L29/78 , H01L29/78696 , H01L2221/1094
摘要： The present disclosure relates to the field of fabricating microelectronic devices. In at least one embodiment, the present disclosure relates to forming an isolated nanowire, wherein isolation structure adjacent the nanowire provides a substantially level surface for the formation of microelectronic structures thereon.
摘要翻译：本公开涉及制造微电子器件的领域。在至少一个实施方案中，本公开涉及形成分离的纳米线，其中与纳米线相邻的隔离结构提供用于在其上形成微电子结构的基本水平的表面。

99. 发明授权

US08168508B2 Method of isolating nanowires from a substrate 有权
标题翻译：从衬底分离纳米线的方法
公开(公告)号：US08168508B2
公开(公告)日：2012-05-01
申请号：US12346554
申请日：2008-12-30
申请人： Benjamin Chu-Kung , Uday Shah , Ravi Pillarisetty , Been-Yih Jin , Marko Radosavljevic , Willy Rachmady
发明人： Benjamin Chu-Kung , Uday Shah , Ravi Pillarisetty , Been-Yih Jin , Marko Radosavljevic , Willy Rachmady
IPC分类号： H01L21/76
CPC分类号： H01L29/06 , B82Y99/00 , H01L21/76205 , H01L21/76224 , H01L29/0657 , H01L29/66795 , H01L29/775 , H01L29/7854
摘要： A method is provided. The method includes forming a plurality of nanowires on a top surface of a substrate and forming an oxide layer adjacent to a bottom surface of each of the plurality of nanowires, wherein the oxide layer is to isolate each of the plurality of nanowires from the substrate.
摘要翻译：提供一种方法。该方法包括在衬底的顶表面上形成多个纳米线并形成与多个纳米线中的每一个的底表面相邻的氧化物层，其中氧化物层将多个纳米线与衬底隔离。

100. 发明申请

US20110147697A1 Isolation for nanowire devices 有权
标题翻译：纳米线器件隔离
公开(公告)号：US20110147697A1
公开(公告)日：2011-06-23
申请号：US12653847
申请日：2009-12-18
申请人： Uday Shah , Benjamin Chu-Kung , Been-Yih Jin , Ravi Pillarisetty , Marko Radosavljevic , Willy Rachmady
发明人： Uday Shah , Benjamin Chu-Kung , Been-Yih Jin , Ravi Pillarisetty , Marko Radosavljevic , Willy Rachmady
IPC分类号： H01L29/66 , H01L21/20
CPC分类号： H01L29/0665 , B82Y10/00 , B82Y40/00 , H01L21/02236 , H01L21/02532 , H01L21/02603 , H01L21/76224 , H01L29/0649 , H01L29/0653 , H01L29/0669 , H01L29/0673 , H01L29/66439 , H01L29/775 , H01L29/78 , H01L29/78696 , H01L2221/1094
摘要： The present disclosure relates to the field of fabricating microelectronic devices. In at least one embodiment, the present disclosure relates to forming an isolated nanowire, wherein isolation structure adjacent the nanowire provides a substantially level surface for the formation of microelectronic structures thereon.
摘要翻译：本公开涉及制造微电子器件的领域。在至少一个实施方案中，本公开涉及形成分离的纳米线，其中与纳米线相邻的隔离结构提供用于在其上形成微电子结构的基本水平的表面。

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