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91. 发明申请

US20080050903A1 ELECTRICALLY PROGRAMMABLE FUSE STRUCTURES WITH NARROWED WIDTH REGIONS CONFIGURED TO ENHANCE CURRENT CROWDING AND METHODS OF FABRICATING THEREOF 失效
标题翻译：电气可编程的保险丝结构，具有配置为提高电流消耗的窄幅区域及其制作方法
公开(公告)号：US20080050903A1
公开(公告)日：2008-02-28
申请号：US11876942
申请日：2007-10-23
申请人： Roger BOOTH , Jack Mandelman , William Tonti
发明人： Roger BOOTH , Jack Mandelman , William Tonti
IPC分类号： H01L21/44
CPC分类号： H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： Electrically programmable fuse structures and methods of fabrication thereof are presented, wherein a fuse includes first and second terminal portions interconnected by an elongate fuse element. The first terminal portion has a maximum width greater than a maximum width of the fuse element, and the fuse includes a narrowed width region where the first terminal portion and fuse element interface. The narrowed width region extends at least partially into and includes part of the first terminal portion. The width of the first terminal portion in the narrowed region is less than the maximum width of the first terminal portion to enhance current crowding therein. In another implementation, the fuse element includes a restricted width region wherein width of the fuse element is less than the maximum width thereof to enhance current crowding therein, and length of the restricted width region is less than a total length of the fuse element.
摘要翻译：提出了电可编程熔丝结构及其制造方法，其中熔丝包括通过细长的熔丝元件互连的第一和第二端部。第一端子部分具有大于熔丝元件的最大宽度的最大宽度，并且熔丝包括第一端子部分和熔丝元件接合的变窄的宽度区域。狭窄宽度区域至少部分地延伸并包括第一端子部分的一部分。变窄区域中的第一端子部分的宽度小于第一端子部分的最大宽度，以增强其中的电流拥挤。在另一实施方式中，熔丝元件包括限制宽度区域，其中熔丝元件的宽度小于其最大宽度以增强其中的电流拥挤，并且受限宽度区域的长度小于熔丝元件的总长度。

92. 发明申请

US20070241409A1 SEMICONDUCTOR STRUCTURES FOR LATCH-UP SUPPRESSION AND METHODS OF FORMING SUCH SEMICONDUCTOR STRUCTURES 有权
标题翻译：用于锁定抑制的半导体结构和形成这种半导体结构的方法
公开(公告)号：US20070241409A1
公开(公告)日：2007-10-18
申请号：US11764571
申请日：2007-06-18
申请人： Toshiharu Furukawa , Robert Gauthier , David Horak , Charles Koburger , Jack Mandelman , William Tonti
发明人： Toshiharu Furukawa , Robert Gauthier , David Horak , Charles Koburger , Jack Mandelman , William Tonti
IPC分类号： H01L27/092 , H01L21/8238
CPC分类号： H01L21/76237 , H01L21/26533 , H01L21/76213 , H01L21/76229 , H01L21/76232 , H01L21/823878 , H01L27/0921 , H01L29/1087 , H01L29/78
摘要： Semiconductor structures and methods for suppressing latch-up in bulk CMOS devices. The semiconductor structure comprises a shaped-modified isolation region that is formed in a trench generally between two doped wells of the substrate in which the bulk CMOS devices are fabricated. The shaped-modified isolation region may comprise a widened dielectric-filled portion of the trench, which may optionally include a nearby damage region, or a narrowed dielectric-filled portion of the trench that partitions a damage region between the two doped wells. Latch-up may also be suppressed by providing a lattice-mismatched layer between the trench base and the dielectric filler in the trench.
摘要翻译：用于抑制大量CMOS器件中的闩锁的半导体结构和方法。该半导体结构包括成形修饰的隔离区，其形成在通常在制造本体CMOS器件的衬底的两个掺杂阱之间的沟槽中。成形改进的隔离区域可以包括沟槽的加宽的电介质填充部分，其可以可选地包括分隔两个掺杂阱之间的损伤区域的沟槽的附近损伤区域或狭窄的电介质填充部分。也可以通过在沟槽中的沟槽基底和介电填料之间提供晶格不匹配的层来抑制闩锁。

93. 发明申请

US20070241408A1 WELL ISOLATION TRENCHES (WIT) FOR CMOS DEVICES 失效
标题翻译：用于CMOS器件的绝缘隔离（WIT）
公开(公告)号：US20070241408A1
公开(公告)日：2007-10-18
申请号：US11759981
申请日：2007-06-08
申请人： Toshiharu Furukawa , Mark Hakey , David Horak , Charles Koburger , Jack Mandelman , William Tonti
发明人： Toshiharu Furukawa , Mark Hakey , David Horak , Charles Koburger , Jack Mandelman , William Tonti
IPC分类号： H01L27/092
CPC分类号： H01L21/823892 , H01L21/76229 , H01L21/823878 , H01L27/11
摘要： A well isolation trenches for a CMOS device and the method for forming the same. The CMOS device includes (a) a semiconductor substrate, (b) a P well and an N well in the semiconductor substrate, (c) a well isolation region sandwiched between and in direct physical contact with the P well and the N well. The P well comprises a first shallow trench isolation (STI) region, and the N well comprises a second STI region. A bottom surface of the well isolation region is at a lower level than bottom surfaces of the first and second STI regions. When going from top to bottom of the well isolation region, an area of a horizontal cross section of the well isolation region is an essentially continuous function.
摘要翻译： CMOS器件的良好隔离沟槽及其形成方法。 CMOS器件包括（a）半导体衬底，（b）半导体衬底中的P阱和N阱，（c）夹在P阱和N阱之间并与P阱和N阱直接物理接触的阱隔离区域。 P阱包括第一浅沟槽隔离（STI）区域，并且N阱包括第二STI区域。阱隔离区域的底表面处于比第一和第二STI区域的底表面更低的水平面。当从隔离区域的顶部到底部进行时，阱隔离区域的水平横截面的区域是基本上连续的函数。

94. 发明申请

US20070189057A1 MULTIPLE PORT MEMORY HAVING A PLURALITY OF PARALLEL CONNECTED TRENCH CAPACITORS IN A CELL 失效
标题翻译：具有多个并联连接的电容器的多端口存储器
公开(公告)号：US20070189057A1
公开(公告)日：2007-08-16
申请号：US11306749
申请日：2006-01-10
申请人： Kangguo Cheng , Ramachandra Divakaruni , Jack Mandelman , Carl Radens , Geng Wang
发明人： Kangguo Cheng , Ramachandra Divakaruni , Jack Mandelman , Carl Radens , Geng Wang
IPC分类号： G11C11/24
CPC分类号： G11C8/16 , G11C11/405 , G11C11/4097 , H01L27/0207 , H01L27/108 , H01L27/10861
摘要： An integrated circuit is provided which includes a memory having multiple ports per memory cell for accessing a data bit within each of a plurality of the memory cells. Such memory includes an array of memory cells in which each memory cell includes a plurality of capacitors connected together as a unitary source of capacitance. A first access transistor is coupled between a first one of the plurality of capacitors and a first bitline and a second access transistor is coupled between a second one of the plurality of capacitors and a second bitline. In each memory cell, a gate of the first access transistor is connected to a first wordline and a gate of the second access transistor is connected to a second wordline.
摘要翻译：提供一种集成电路，其包括每个存储器单元具有多个端口的存储器，用于访问多个存储器单元中的每一个内的数据位。这种存储器包括存储单元的阵列，其中每个存储单元包括连接在一起作为整体电容源的多个电容器。第一存取晶体管耦合在多个电容器中的第一电容器和第一位线之间，第二存取晶体管耦合在多个电容器中的第二电容器和第二位线之间。在每个存储单元中，第一存取晶体管的栅极连接到第一字线，第二存取晶体管的栅极连接到第二字线。

95. 发明申请

US20070170516A1 TRIPLE-WELL CMOS DEVICES WITH INCREASED LATCH-UP IMMUNITY AND METHODS OF FABRICATING SAME 有权
标题翻译：具有增加的锁存功能的三倍体CMOS器件及其制造方法
公开(公告)号：US20070170516A1
公开(公告)日：2007-07-26
申请号：US11340344
申请日：2006-01-26
申请人： Delbert Cecchi , Toshiharu Furukawa , Jack Mandelman
发明人： Delbert Cecchi , Toshiharu Furukawa , Jack Mandelman
IPC分类号： H01L29/76 , H01L21/8238
CPC分类号： H01L27/0921 , H01L27/0928 , H01L29/1087 , H01L29/7833
摘要： A triple-well CMOS structure having reduced latch-up susceptibility and a method of fabricating the structure. The method includes forming a buried P-type doped layer having low resistance under the P-wells and N-wells in which CMOS transistors are formed and forming a gap in a buried N-type doped layer formed in the P-wells, the is gap aligned under a contact to the P-well. The buried P-type doped layer and gap in the buried N-type doped layer allow a low resistance hole current path around parasitic bipolar transistors of the CMOS transistors.
摘要翻译：具有减小的闩锁磁化率的三阱CMOS结构和制造该结构的方法。该方法包括在P阱下形成具有低电阻的掩埋P型掺杂层和形成CMOS晶体管的N阱，并在P阱中形成的掩埋N型掺杂层中形成间隙，在与P阱的接触下对齐的间隙。埋入的P型掺杂层和掩埋N型掺杂层中的间隙允许在CMOS晶体管的寄生双极晶体管周围的低电阻空穴电流路径。

96. 发明申请

US20070093036A1 Methods for forming germanium-on-insulator semiconductor structures using a porous layer and semiconductor structures formed by these methods 失效
标题翻译：使用多孔层形成绝缘体上半导体结构的方法和通过这些方法形成的半导体结构的方法
公开(公告)号：US20070093036A1
公开(公告)日：2007-04-26
申请号：US11259297
申请日：2005-10-26
申请人： Kangguo Cheng , Brian Greene , Jack Mandelman
发明人： Kangguo Cheng , Brian Greene , Jack Mandelman
IPC分类号： H01L21/30 , H01L21/20 , H01L21/76
CPC分类号： H01L21/76251 , H01L21/76245 , Y10S438/933
摘要： A semiconductor structure that includes a monocrystalline germanium-containing layer, preferably substantially pure germanium, a substrate, and a buried insulator layer separating the germanium-containing layer from the substrate. A porous layer, which may be porous silicon, is formed on a substrate and a germanium-containing layer is formed on the porous silicon layer. The porous layer may be converted to a layer of oxide, which provides the buried insulator layer. Alternatively, the germanium-containing layer may be transferred from the porous layer to an insulating layer on another substrate. After the transfer, the insulating layer is buried between the latter substrate and the germanium-containing layer.
摘要翻译：一种半导体结构，其包括单晶含锗层，优选基本上纯的锗，衬底和将锗含量层与衬底分离的掩埋绝缘体层。在基板上形成可以是多孔硅的多孔层，在多孔硅层上形成含锗层。多孔层可以转化成一层氧化物，这提供了埋层绝缘体层。或者，含锗层可以从多孔层转移到另一衬底上的绝缘层。在转移之后，绝缘层被埋在后面的衬底和含锗层之间。

97. 发明申请

US20070090433A1 Isolation collar void and methods of forming the same 审中-公开
标题翻译：隔离环空隙及其形成方法
公开(公告)号：US20070090433A1
公开(公告)日：2007-04-26
申请号：US11259295
申请日：2005-10-26
申请人： Kangguo Cheng , Herbert Ho , Jack Mandelman
发明人： Kangguo Cheng , Herbert Ho , Jack Mandelman
IPC分类号： H01L29/00 , H01L21/00
CPC分类号： H01L29/0657
摘要： In a first aspect, a first apparatus is provided. The first apparatus includes a void formed around one or more portions of a microelectronic device in a bulk substrate. The void is adapted to reduce a parasitic leakage between the microelectronic device and the bulk substrate. Numerous other aspects are provided.
摘要翻译：在第一方面中，提供了一种第一装置。第一装置包括在体基板中的微电子器件的一个或多个部分周围形成的空隙。该空隙适于减少微电子器件与本体衬底之间的寄生泄漏。提供了许多其他方面。

98. 发明申请

US20070047293A1 DUAL PORT GAIN CELL WITH SIDE AND TOP GATED READ TRANSISTOR 有权
标题翻译：双端口增益单元与侧面和顶部读取晶体管
公开(公告)号：US20070047293A1
公开(公告)日：2007-03-01
申请号：US11161962
申请日：2005-08-24
申请人： Jack Mandelman , Kangguo Cheng , Ramachandra Divakaruni , Carl Radens , Geng Wang
发明人： Jack Mandelman , Kangguo Cheng , Ramachandra Divakaruni , Carl Radens , Geng Wang
IPC分类号： G11C11/24
CPC分类号： H01L27/108 , H01L27/10829 , H01L27/10867 , H01L27/1203
摘要： A DRAM memory cell and process sequence for fabricating a dense (20 or 18 square) layout is fabricated with silicon-on-insulator (SOI) CMOS technology. Specifically, the present invention provides a dense, high-performance SRAM cell replacement that is compatible with existing SOI CMOS technologies. Various gain cell layouts are known in the art. The present invention improves on the state of the art by providing a dense layout that is fabricated with SOI CMOS. In general terms, the memory cell includes a first transistor provided with a gate, a source, and a drain respectively; a second transistor having a first gate, a second gate, a source, and a drain respectively; and a capacitor having a first terminal, wherein the first terminal of said capacitor and the second gate of said second transistor comprise a single entity.
摘要翻译：使用绝缘体上硅（SOI）CMOS技术制造用于制造致密（20或18平方）布局的DRAM存储单元和工艺顺序。具体地，本发明提供了与现有SOI CMOS技术兼容的致密的高性能SRAM单元替换。各种增益单元布局在本领域中是已知的。本发明通过提供利用SOI CMOS制造的致密布局来改善现有技术的状态。通常，存储单元包括分别设置有栅极，源极和漏极的第一晶体管; 分别具有第一栅极，第二栅极，源极和漏极的第二晶体管; 以及具有第一端子的电容器，其中所述电容器的第一端子和所述第二晶体管的第二栅极包括单个实体。

99. 发明申请

US20070010059A1 Fin field effect transistors (FinFETs) and methods for making the same 审中-公开
标题翻译： Fin场效应晶体管（FinFET）及其制造方法
公开(公告)号：US20070010059A1
公开(公告)日：2007-01-11
申请号：US11522164
申请日：2006-09-15
申请人： William Hovis , Jack Mandelman
发明人： William Hovis , Jack Mandelman
IPC分类号： H01L21/336
CPC分类号： H01L29/4908 , H01L29/42384 , H01L29/66795 , H01L29/785
摘要： In a first aspect, a first method is provided for semiconductor device manufacturing. The first method includes the steps of (1) forming a first side of a fin of a fin field effect transistor (FinFET); (2) processing the first side of the fin; and (3) forming a second side of the fin while supporting the first side of the fin. Numerous other aspects are provided.
摘要翻译：在第一方面中，提供了半导体器件制造的第一种方法。第一种方法包括以下步骤：（1）形成鳍状场效应晶体管（FinFET）的鳍的第一侧; （2）处理鳍片的第一面; 和（3）在支撑翅片的第一侧的同时形成翅片的第二侧。提供了许多其他方面。

100. 发明申请

US20060261414A1 Fin field effect transistors (FinFETs) and methods for making the same 有权
标题翻译： Fin场效应晶体管（FinFET）及其制造方法
公开(公告)号：US20060261414A1
公开(公告)日：2006-11-23
申请号：US11132652
申请日：2005-05-19
申请人： William Hovis , Jack Mandelman
发明人： William Hovis , Jack Mandelman
IPC分类号： H01L29/76
CPC分类号： H01L29/4908 , H01L29/42384 , H01L29/66795 , H01L29/785
摘要： In a first aspect, a first method is provided for semiconductor device manufacturing. The first method includes the steps of (1) forming a first side of a fin of a fin field effect transistor (FinFET); (2) processing the first side of the fin; and (3) forming a second side of the fin while supporting the first side of the fin. Numerous other aspects are provided.
摘要翻译：在第一方面中，提供了半导体器件制造的第一种方法。第一种方法包括以下步骤：（1）形成鳍状场效应晶体管（FinFET）的鳍的第一侧; （2）处理鳍片的第一面; 和（3）在支撑翅片的第一侧的同时形成翅片的第二侧。提供了许多其他方面。

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