专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

91. 发明授权

US06903436B1 Multiple-time programmable electrical fuse utilizing MOS oxide breakdown 失效
标题翻译：多次可编程电熔丝利用MOS氧化物分解
公开(公告)号：US06903436B1
公开(公告)日：2005-06-07
申请号：US10833968
申请日：2004-04-27
申请人： Ruei-Chin Luo , Chung-Cheng Chou , Ching-Wei Wu
发明人： Ruei-Chin Luo , Chung-Cheng Chou , Ching-Wei Wu
IPC分类号： G11C17/16 , G11C17/18 , H01L23/525 , H01L29/00 , H01L29/76
CPC分类号： G11C17/16 , G11C17/18 , H01L23/5252 , H01L2924/0002 , H01L2924/00
摘要： An improved a programmable electrical fuse device utilizing MOS oxide breakdown is described herein. The fuse device comprises a programmable MOS device having a first gate width, a reference MOS device having a second gate width that is substantially less than the first gate width, and a sense amplifier operable to detect a difference in current and generate a corresponding logical signal. According to one embodiment, the fuse device can be programmed only once to invert its logical state and thereby provide a changeable logical signal. This is done by applying an overvoltage signal to the programmable MOS device so that its oxide layer breaks down. Since the programmable MOS device and the reference MOS device are on opposite sides of the sense amplifier, an opposite logical signal is generated by shorting-out the programmable MOS device. According to another embodiment, the fuse device can be programmed and erased multiple times by breaking down oxide layers in MOS devices that are alternating sides of a sense amplifier.
摘要翻译：本文描述了利用MOS氧化物击穿的改进的可编程电熔丝装置。熔丝器件包括具有第一栅极宽度的可编程MOS器件，具有基本上小于第一栅极宽度的第二栅极宽度的参考MOS器件，以及用于检测电流差并产生相应逻辑信号的读出放大器。根据一个实施例，熔丝器件可以仅被编程一次以反转其逻辑状态，从而提供可变的逻辑信号。这通过对可编程MOS器件施加过电压信号以使其氧化层发生故障来完成。由于可编程MOS器件和参考MOS器件位于读出放大器的相对侧，所以通过短路可编程MOS器件产生相反的逻辑信号。根据另一实施例，通过分解作为读出放大器的交替侧的MOS器件中的氧化物层，可以对熔丝器件进行多次编程和擦除。

92. 发明申请

US20050052919A1 Temperature detecting circuit for controlling a self-refresh period of a semiconductor memory device 有权
标题翻译：用于控制半导体存储器件的自刷新周期的温度检测电路
公开(公告)号：US20050052919A1
公开(公告)日：2005-03-10
申请号：US10658833
申请日：2003-09-09
申请人： Chung-Cheng Chou
发明人： Chung-Cheng Chou
IPC分类号： G11C11/406 , G11C7/00
CPC分类号： G11C11/40626 , G11C11/406 , G11C2211/4061
摘要： Systems for providing a temperature detecting circuit includes seven transistors and six resistors. In a preferred embodiment, one of the seven transistors is configured as an enabling element and the others form two comparators. The six resistors form three voltage dividers with output varying based upon changing temperature. Two comparators are included that sense the difference between the outputs of two of the voltage dividers, and generate a corresponding 2-bit detection signal by which the refresh period is determined. Other systems and methods are also provided.
摘要翻译：用于提供温度检测电路的系统包括七个晶体管和六个电阻器。在优选实施例中，七个晶体管中的一个被配置为使能元件，而另一个形成两个比较器。六个电阻形成三个分压器，输出根据温度变化而变化。包括两个比较器，用于检测两个分压器的输出之间的差异，并产生相应的2位检测信号，由此确定刷新周期。还提供了其他系统和方法。

93. 发明授权

US09064550B2 Method and apparatus for word line suppression 有权
标题翻译：用于字线抑制的方法和装置
公开(公告)号：US09064550B2
公开(公告)日：2015-06-23
申请号：US13279375
申请日：2011-10-24
申请人： Jonathan Tsung-Yung Chang , Chiting Cheng , Chien-Kuo Su , Chung-Cheng Chou , Jack Liu
发明人： Jonathan Tsung-Yung Chang , Chiting Cheng , Chien-Kuo Su , Chung-Cheng Chou , Jack Liu
IPC分类号： G11C11/00 , G11C8/08 , G11C11/418
CPC分类号： G11C8/08 , G11C11/418
摘要： A memory access operation on a bit cell of a digital memory, e.g., a static random access memory (SRAM), is assisted by reducing the word line control voltage for reading and boosting it for writing, thus improving data integrity. The bit cell has cross coupled inverters for storing and retrieving a logic state via bit line connections through a passing gate transistor controlled by the word line. A level of a word line signal controlling the passing gate transistor is shifted from a first voltage value to a higher second voltage value to begin a memory access cycle. The level of the word line signal is shifted from the second voltage value to a third voltage value less than the second voltage value during the access cycle. The word line signal is maintained at the third voltage value for a time interval during the access cycle.
摘要翻译：数字存储器的位单元（例如静态随机存取存储器（SRAM））上的存储器访问操作通过减少字线控制电压来进行辅助，用于读取和提升其用于写入，从而提高数据完整性。位单元具有交叉耦合的反相器，用于经由位线连接通过由字线控制的通过栅极晶体管来存储和取回逻辑状态。控制通过栅极晶体管的字线信号的电平从第一电压值移位到较高的第二电压值，以开始存储器访问周期。在访问周期期间，字线信号的电平从第二电压值移位到小于第二电压值的第三电压值。在访问周期期间，字线信号保持在第三电压值一段时间间隔。

94. 发明授权

US09025356B2 Fly-over conductor segments in integrated circuits with successive load devices along a signal path 有权
标题翻译：集成电路中的飞越导体段，沿着信号路径连续的负载装置
公开(公告)号：US09025356B2
公开(公告)日：2015-05-05
申请号：US13221081
申请日：2011-08-30
申请人： Hsiao-Wen Lu , Wei-Jer Hsieh , Chiting Cheng , Chung-Cheng Chou , Jonathan Tsung-Yung Chang
发明人： Hsiao-Wen Lu , Wei-Jer Hsieh , Chiting Cheng , Chung-Cheng Chou , Jonathan Tsung-Yung Chang
IPC分类号： G11C5/06 , G11C7/10 , G11C11/00 , G11C11/413
CPC分类号： G11C5/063 , G11C11/413 , Y10T307/445
摘要： The propagation delay of a signal through multiple load devices coupled sequentially along a conductor is improved by separating a subset of the load devices that is more distant from the signal source, and coupling the more distant subset to the signal through a fly-over conductor that bypasses the subset that is nearer to the signal source. The technique is applicable to subsets of bit cells in a random access memory (SRAM) coupled to a given word line, or to word line decoder gates coupled sequentially to a strobe signal, as well as other circuits wherein load devices selectable as a group can be divided into subsets by proximity to the signal source. In an SRAM layout with multiple levels, different metal deposition layers carry the conductor legs between the load devices versus the fly-over conductor bypassing the nearer subset.
摘要翻译：通过分离距离信号源更远的负载装置的子集，并通过飞越导体将更远的子集耦合到信号，改善了通过沿导体顺序耦合的多个负载装置的信号的传播延迟，绕过更靠近信号源的子集。该技术适用于耦合到给定字线的随机存取存储器（SRAM）中的位单元的子集，或者适用于顺序耦合到选通信号的字线解码器门，以及其他可选择作为一组的负载装置的电路通过靠近信号源将其划分为子集。在具有多个级别的SRAM布局中，不同的金属沉积层承载负载装置之间的导体腿与绕过更近的子集的飞越导体。

95. 发明授权

US08405441B2 Latch circuitry and methods of operating latch circuitry 有权
标题翻译：锁存电路和操作锁存电路的方法
公开(公告)号：US08405441B2
公开(公告)日：2013-03-26
申请号：US13070868
申请日：2011-03-24
申请人： Chien-Kuo Su , Yi-Tzu Chen , Chung-Cheng Chou
发明人： Chien-Kuo Su , Yi-Tzu Chen , Chung-Cheng Chou
IPC分类号： H03K3/356
CPC分类号： H03K3/012 , H03K3/356121 , H03K3/356173
摘要： A latch circuit includes an output driver electrically coupled with a circuit. The circuit is electrically coupled with the output driver through a first path and a second path. The circuit is configured to receive a data signal. The circuit is configured to divert a signal of the output driver through the first path at a falling edge of the data signal. The circuit is configured to divert the signal of the output driver through the second path at a rising edge of the data signal.
摘要翻译：锁存电路包括与电路电耦合的输出驱动器。电路通过第一路径和第二路径与输出驱动器电耦合。电路被配置为接收数据信号。电路被配置为在数据信号的下降沿通过第一路径转移输出驱动器的信号。电路被配置为在数据信号的上升沿通过第二路径转移输出驱动器的信号。

96. 发明授权

US08331132B2 Adaptive write bit line and word line adjusting mechanism for memory 有权
标题翻译：适应性写入位线和字线调整机制用于存储器
公开(公告)号：US08331132B2
公开(公告)日：2012-12-11
申请号：US12849570
申请日：2010-08-03
申请人： Hank Cheng , Ming-Zhang Kuo , Chung-Cheng Chou
发明人： Hank Cheng , Ming-Zhang Kuo , Chung-Cheng Chou
IPC分类号： G11C11/24 , G11C7/00 , G11C8/00
CPC分类号： G11C7/00 , G11C7/20 , G11C8/08 , G11C11/413 , G11C2207/2254
摘要： A memory includes a capacitor coupled to a write bit line or a word line. An initializer is configured to initialize a voltage level at a first node between the capacitor and the write bit line or a word line. An initial level adjuster is configured to adjust a voltage level of a second node at one terminal of the capacitor. A pulse generator configured to supply a pulse to the initial level adjuster to control the initial level adjuster. A boost signal is configured to be supplied to a third node on the other terminal of the capacitor opposite the first node to boost a voltage level of the write bit line lower than ground or to boost a voltage level of the word line higher than a power supply voltage.
摘要翻译：存储器包括耦合到写位线或字线的电容器。初始化器被配置为初始化电容器和写位线或字线之间的第一节点处的电压电平。初始电平调节器被配置为调节电容器的一个端子处的第二节点的电压电平。脉冲发生器，被配置为向初始电平调节器提供脉冲以控制初始电平调节器。升压信号被配置为提供给与第一节点相对的电容器的另一个端子上的第三节点，以提高写入位线的低于地的电压电平，或将字线的电压电平提高到高于功率电源电压。

97. 发明申请

US20120188838A1 MEMORY WITH WORD-LINE SEGMENT ACCESS 有权
标题翻译：使用WORD-LINE SEGMENT访问的记忆
公开(公告)号：US20120188838A1
公开(公告)日：2012-07-26
申请号：US13010039
申请日：2011-01-20
申请人： Chiting Cheng , Hsiu-Feng Peng , Ming-Zhang Kuo , Chung-Cheng Chou
发明人： Chiting Cheng , Hsiu-Feng Peng , Ming-Zhang Kuo , Chung-Cheng Chou
IPC分类号： G11C8/08
CPC分类号： G11C8/08 , G11C7/12 , G11C8/14 , G11C11/418 , G11C11/419
摘要： A memory comprises a row of bit cells, including a first plurality of bit cells and a second plurality of bit cells. A first word line segment driver is connected to the first plurality of bits cells. A second word line segment driver is connected to the second plurality of bits cells. The first and second word line segment drivers are selectively operable for activating one of the first and second pluralities of bit cells at a time to the exclusion of the other plurality of bit cells. A shared sense amplifier is coupled to at least one of the first plurality of bit cells and at least one of the second plurality of bit cells. The shared sense amplifier is configured to receive signals from whichever of the one first or second bit cell is activated by its respective word line segment driver at a given time.
摘要翻译：存储器包括一行比特单元，包括第一多个比特单元和第二多个比特单元。第一字线段驱动器连接到第一多个位单元。第二字线段驱动器连接到第二多个位单元。第一和第二字线段驱动器被选择性地可操作用于一次激活第一和第二多个位单元之一以排除其他多个位单元。共享读出放大器耦合到第一多个位单元和第二多个位单元中的至少一个位单元中的至少一个。共享读出放大器被配置为在给定时间从其相应的字线段驱动器接收由一个第一或第二位单元中的哪一个激活的信号。

98. 发明授权

US07599212B2 Method and apparatus for high-efficiency operation of a dynamic random access memory 有权
标题翻译：动态随机存取存储器高效运行的方法和装置
公开(公告)号：US07599212B2
公开(公告)日：2009-10-06
申请号：US11625572
申请日：2007-01-22
申请人： Hank Cheng , Chen-Hui Hsieh , Chung-Cheng Chou
发明人： Hank Cheng , Chen-Hui Hsieh , Chung-Cheng Chou
IPC分类号： G11C11/24
CPC分类号： G11C7/08 , G11C7/065 , G11C7/1006 , G11C7/12 , G11C11/4091 , G11C11/4094
摘要： The disclosure generally relates to a method and apparatus for reading and writing information to a memory cell in communication with a word line and one of a bit line or a complementary bit line. A method according to one embodiment includes: equalizing the bit line and the complementary bit line to a common voltage; addressing the memory cell by connecting the memory cell to one of the bit line or the complementary bit line; reading the memory cell by detecting a first charge stored in the memory cell and communicated said first charge to one of the bit line or the complementary bit line; and writing a second charge into the memory cell by communicating the second charge to the memory cell through an inverter and one of the bit line or the complementary bit line. In one embodiment, the inverter is activated only to communicate the second charge to the memory cell.
摘要翻译：本公开总体上涉及一种用于读取和写入与字线和位线或互补位线中的一个通信的存储器单元的信息的方法和装置。根据一个实施例的方法包括：将位线和互补位线均衡为公共电压; 通过将存储器单元连接到位线或互补位线之一来寻址存储器单元; 通过检测存储在存储单元中的第一电荷并将所述第一电荷传送到位线或互补位线之一来读取存储单元; 以及通过将所述第二电荷通过反相器和所述位线或所述互补位线之一传送到所述存储单元，将第二电荷写入所述存储单元。在一个实施例中，反相器仅被激活以将第二电荷传送到存储单元。

99. 发明授权

US07578583B2 Fluid injection devices with sensors, fluid injection system and method of analyzing fluid in fluid injection devices 失效
标题翻译：具有传感器，流体注射系统和流体注射装置中流体分析方法的流体注射装置
公开(公告)号：US07578583B2
公开(公告)日：2009-08-25
申请号：US11505796
申请日：2006-08-16
申请人： Chung-Cheng Chou , Chih-Ming Lin
发明人： Chung-Cheng Chou , Chih-Ming Lin
IPC分类号： B41J2/05 , B41J29/393
CPC分类号： B41J2/14153 , B41J2002/14354
摘要： A fluid injection device integrating a piezoelectric sensor, a fluid injection apparatus and a method for analyzing fluid content in a fluid injection device. The fluid injection device comprises a fluid injector and a piezoelectric sensor. The fluid injector comprises a plurality of fluid chambers formed in a substrate for receiving fluid. A structural layer is disposed on the substrate and the plurality of fluid chambers. At least one fluid actuator is disposed on the structural layer opposing each fluid chamber. A nozzle is adjacent to the at least one fluid actuator and connecting each fluid chamber through the structural layer. The piezoelectric sensor id disposed on the structural layer to analyze fluid content in each fluid chamber.
摘要翻译：一种集成压电传感器，流体注射装置和用于分析流体注射装置中的流体含量的方法的流体注入装置。流体注射装置包括流体注射器和压电传感器。流体注射器包括形成在用于接收流体的基底中的多个流体室。结构层设置在基板和多个流体室上。至少一个流体致动器设置在与每个流体室相对的结构层上。喷嘴与所述至少一个流体致动器相邻，并且将每个流体室连接通过结构层。设置在结构层上的压电传感器id用于分析每个流体室中的流体含量。

100. 发明授权

US07494207B2 Fluid injection device preventing activation of a bipolar junction transistor (BJT) therein 失效
标题翻译：流体注入装置防止其中的双极结型晶体管（BJT）的激活
公开(公告)号：US07494207B2
公开(公告)日：2009-02-24
申请号：US11331514
申请日：2006-01-13
申请人： Tsung-Wei Huang , Chung-Cheng Chou
发明人： Tsung-Wei Huang , Chung-Cheng Chou
IPC分类号： B41J2/05
CPC分类号： B41J2/04541 , B41J2/0455 , B41J2/0458 , B41J2/14072 , B41J2202/13
摘要： Fluid injection devices comprise M sets of fluid injection units. Each fluid injection unit comprises N injectors separately connecting to a driver. A controller separately transmits a signal to the driver, thereby simultaneously driving a selected injector of each of the M sets of fluid injection units. A non-selected injector of each of the M sets of fluid injection units does not trigger bipolar junction transistors (BJTs).
摘要翻译：流体注射装置包括M组流体注射单元。每个流体注射单元包括分别连接到驱动器的N个注射器。控制器分别将信号发送到驾驶员，从而同时驱动M组流体注射单元中的每一个的所选择的注射器。 M组流体注入单元中的每一个的未选择的注射器不触发双极结型晶体管（BJT）。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式