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    • 95. 发明申请
    • Battery charging system and related method for preventing overheating while charging
    • 电池充电系统及相关方法,用于防止充电时过热
    • US20070126405A1
    • 2007-06-07
    • US11164703
    • 2005-12-02
    • Wei-Peng KaoChih-Chang ChenTsung-Ju Tsai
    • Wei-Peng KaoChih-Chang ChenTsung-Ju Tsai
    • H02J7/04
    • H02J7/0091H02J7/0029
    • A battery charging system charges a battery using a charging circuit. The battery has an input port for receiving a charging current and a thermistor electrically connected to an output port. For battery temperatures above a threshold temperature, a resistance produced by the thermistor increases as the battery temperature increases. The charging circuit includes an input connector electrically connected to the output port of the battery and a resistance measuring circuit for measuring the resistance produced by the thermistor of the battery. A current generating circuit produces a charging current according to the measured resistance, and as the measured resistance increases, the charging current produced by the current generating circuit decreases. An output connector of the charging circuit is electrically connected to the input port of the battery for providing the charging current to the battery.
    • 电池充电系统使用充电电路对电池充电。 电池具有用于接收充电电流的输入端口和电连接到输出端口的热敏电阻。 对于电池温度高于阈值温度,热敏电阻产生的电阻随着电池温度的升高而增加。 充电电路包括电连接到电池的输出端口的输入连接器和用于测量由电池的热敏电阻产生的电阻的电阻测量电路。 电流产生电路根据测量的电阻产生充电电流,并且随着测量的电阻增加,由电流发生电路产生的充电电流减小。 充电电路的输出连接器电连接到电池的输入端口,以向电池提供充电电流。
    • 99. 发明授权
    • Method to modify 0.25 μm 1T-RAM by extra resist protect oxide (RPO) blocking
    • 通过额外的抗氧化保护氧化物(RPO)阻挡来修改0.25 mum 1T-RAM的方法
    • US06852589B2
    • 2005-02-08
    • US10323098
    • 2002-12-18
    • Ching-Kwun HuangChih-Chang ChenHsien-Chih PengPin-Shyne Chin
    • Ching-Kwun HuangChih-Chang ChenHsien-Chih PengPin-Shyne Chin
    • H01L21/44H01L21/8238H01L21/8242
    • H01L27/10873H01L27/10894
    • A method to fabricate a 1T-RAM device, comprising the following steps. A semiconductor substrate having an access transistor area and an exposed bottom plate within a capacitor area proximate the access transistor area is provided. A gate with an underlying gate dielectric layer within the access transistor area are formed. The gate and underlying gate dielectric layer having sidewall spacers formed over their respective exposed side walls. A top plate with an underlying capacitor layer over the bottom plate within the capacitor area are formed. The top plate and underlying capacitor layer having sidewall spacers formed over their respective exposed side walls. A patterned resist protect oxide (RPO) layer is formed over at least the drain of the structure not to be silicided. Metal silicide portions are formed over the structure not protected by the RPO layer.
    • 一种制造1T-RAM设备的方法,包括以下步骤。 提供了具有接近晶体管区域和接近存取晶体管区域的电容器区域内的暴露底板的半导体衬底。 在存取晶体管区域内形成具有底层栅介质层的栅极。 栅极和底层栅介质层具有形成在它们各自暴露的侧壁上的侧壁间隔物。 形成在电容器区域内的底板上方具有底层电容器层的顶板。 顶板和底层电容器层具有形成在它们各自的暴露的侧壁上的侧壁间隔物。 形成图案化的抗蚀剂保护氧化物(RPO)层至少在不被硅化的结构的漏极上。 在不受RPO层保护的结构上形成金属硅化物部分。