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91. 发明授权

US06898119B2 Nonvolatile semiconductor memory and its test method 有权
标题翻译：非易失性半导体存储器及其测试方法
公开(公告)号：US06898119B2
公开(公告)日：2005-05-24
申请号：US10919282
申请日：2004-08-17
申请人： Kenichi Imamiya , Koichi Kawai
发明人： Kenichi Imamiya , Koichi Kawai
IPC分类号： G11C16/02 , G11C16/00 , G11C29/44 , G11C29/50 , G11C29/56 , G11C16/06
CPC分类号： G11C16/3481 , G11C16/04 , G11C29/028 , G11C29/12005 , G11C29/50 , G11C29/50004
摘要： A nonvolatile semiconductor memory is disclosed, which comprises a nonvolatile memory cell array, a write circuit which repeatedly executes a write and a verification, and a write voltage control circuit, the write voltage control circuit comprising a first binary counter which counts a first clock signal supplied every time the verification fails and supplies output data to the write circuit, a first register which stores data for setting the number of erases and verifications, a second binary counter which is reset using a first timing, counts a second clock signal supplied if a verify write executed on the target write unit fails, an accumulative value storage circuit which is reset using a second timing and stores a value corresponding to an accumulative value for the contents of the second binary counter, and a nonvolatile storage element which stores the appropriate value for the write start voltage.
摘要翻译：公开了一种非易失性半导体存储器，其包括非易失性存储单元阵列，重复执行写入和验证的写入电路以及写入电压控制电路，所述写入电压控制电路包括对第一时钟信号进行计数的第一二进制计数器在每次验证失败时提供并将输出数据提供给写入电路，存储用于设置擦除和验证数量的数据的第一寄存器，使用第一定时复位的第二二进制计数器对第二时钟信号进行计数，如果验证在目标写入单元上执行的写入失败，使用第二定时复位的累加值存储电路存储对应于第二二进制计数器的内容的累积值的值，以及存储适当值的非易失性存储元件用于写入启动电压。

92. 发明申请

US20050018483A1 Nonvolatile semiconductor memory and its test method 有权
公开(公告)号：US20050018483A1
公开(公告)日：2005-01-27
申请号：US10919282
申请日：2004-08-17
申请人： Kenichi Imamiya , Koichi Kawai
发明人： Kenichi Imamiya , Koichi Kawai
IPC分类号： G11C16/02 , G11C16/00 , G11C29/44 , G11C29/50 , G11C29/56 , G11C11/34
CPC分类号： G11C16/3481 , G11C16/04 , G11C29/028 , G11C29/12005 , G11C29/50 , G11C29/50004
摘要： A nonvolatile semiconductor memory is disclosed, which comprises a nonvolatile memory cell array, a write circuit which repeatedly executes a write and a verification, and a write voltage control circuit, the write voltage control circuit comprising a first binary counter which counts a first clock signal supplied every time the verification fails and supplies output data to the write circuit, a first register which stores data for setting the number of erases and verifications, a second binary counter which is reset using a first timing, counts a second clock signal supplied if a verify write executed on the target write unit fails, an accumulative value storage circuit which is reset using a second timing and stores a value corresponding to an accumulative value for the contents of the second binary counter, and a nonvolatile storage element which stores the appropriate value for the write start voltage.

93. 发明授权

US06751122B2 Nonvolatile semiconductor memory device 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US06751122B2
公开(公告)日：2004-06-15
申请号：US10371306
申请日：2003-02-21
申请人： Koichi Kawai , Kenichi Imamiya , Koji Hosono
发明人： Koichi Kawai , Kenichi Imamiya , Koji Hosono
IPC分类号： G11C1606
CPC分类号： G11C16/20 , G11C16/0483
摘要： The nonvolatile semiconductor memory device includes a memory cell array containing a plurality of nonvolatile memory cells and an initial setup data region in which initial setup data specified to determine operation conditions of the device is to be written. The device further includes a detection circuit which detects turn-on of power. The device further includes a readout circuit which reads out the initial setup data from the initial setup data region of the memory cell array upon detecting power-on by the detection circuit. The device further includes a determination circuit which determines whether the initial setup data read out by the readout circuit is effective or ineffective. The device further includes a setup circuit which sets up the device in an operative-prohibiting status when the initial setup data is determined as ineffective by the determination circuit.
摘要翻译：非易失性半导体存储器件包括存储单元阵列，该存储单元阵列包含多个非易失性存储单元和初始设置数据区域，其中指定用于确定该器件的操作条件的初始设置数据将被写入。该装置还包括检测电源接通的检测电路。该装置还包括读出电路，其在检测电路检测到上电时从存储单元阵列的初始设置数据区读出初始设置数据。该装置还包括确定电路，其确定由读出电路读出的初始设置数据是有效还是无效。该装置还包括一个建立电路，当初始设置数据被确定为无效的确定电路时，该设备将该设备设置为操作禁止状态。

94. 发明授权

US06717858B2 Non-volatile semiconductor memory device in which one page is set for a plurality of memory cell arrays 有权
公开(公告)号：US06717858B2
公开(公告)日：2004-04-06
申请号：US10190069
申请日：2002-07-03
申请人： Koichi Kawai , Kenichi Imamiya , Hiroshi Nakamura , Koji Hosono
发明人： Koichi Kawai , Kenichi Imamiya , Hiroshi Nakamura , Koji Hosono
IPC分类号： G11C1606
CPC分类号： G11C16/3459 , G11C16/0483 , G11C16/08 , G11C16/3454
摘要： A plurality of memory cell arrays are provided. Each of the memory cell arrays has a plurality of memory cells and the memory cells are connected to a plurality of word lines. Corresponding with the plurality of memory cell arrays, a plurality of word line drive circuits and a plurality of bit line control circuits are provided. Each of the word line drive circuits selects and drives the word lines of the corresponding memory cell array. Each of the bit control circuits carries out verifying reading for the data written in advance in the plurality of memory cells of the corresponding memory cell array, and controls a select and driving operation for the word lines of the corresponding word line drive circuit based on a result of the verifying reading.

95. 发明授权

US06661706B2 Semiconductor storage device having page copying 有权
标题翻译：具有页复制的半导体存储装置
公开(公告)号：US06661706B2
公开(公告)日：2003-12-09
申请号：US10194337
申请日：2002-07-12
申请人： Koichi Kawai , Kenichi Imamiya , Hiroshi Nakamura
发明人： Koichi Kawai , Kenichi Imamiya , Hiroshi Nakamura
IPC分类号： G11C1604
CPC分类号： G11C16/105 , G11C7/1006 , G11C7/1021 , G11C16/0483 , G11C16/06 , G11C16/10 , G11C16/102 , G11C16/3431 , H01L27/115
摘要： Data read from memory cells of one page in a memory cell array that corresponds to a page address of a copy source is sensed and latched by a sense/latch circuit. The sense/latch circuit has a plurality of latch circuits, and the plurality of latch circuits is specified according to the column address. The latch circuit specified in accordance with the column address is supplied with the data to be rewritten. The latch circuit specified in accordance with its address latches the data to be rewritten, whereby rewriting of the data is performed. The data of one page after rewritten is written into the page in the memory cell array that corresponds to the page address of a copy destination.
摘要翻译：从对应于复制源的页面地址的存储单元阵列中的一页的存储器单元读取的数据被感测/锁存电路检测和锁存。感测/锁存电路具有多个锁存电路，并且根据列地址指定多个锁存电路。根据列地址指定的锁存电路被提供要被重写的数据。根据其地址指定的锁存电路锁存要重写的数据，由此执行数据的重写。重写后的一页的数据被写入到与复制目的地的页面地址对应的存储单元阵列中的页面中。

96. 发明授权

US4540104A Device for sealing the floating roof of an oil tank 失效
标题翻译：用于密封油箱浮顶的装置
公开(公告)号：US4540104A
公开(公告)日：1985-09-10
申请号：US594114
申请日：1984-03-28
申请人： Koichi Kawai , Minoru Mikuriya
发明人： Koichi Kawai , Minoru Mikuriya
IPC分类号： B65D88/42 , B65D88/46
CPC分类号： B65D88/46
摘要： A floating roof-type oil-tank sealing device wherein an inclined connector extends between an upper portion of a seal shoe and the lower portion of outer rim of a floating pontoon, and in such a state that each end of the inclined connector is pivotally supported by means of an inserted pin. A compression spring applies pressure to the inclined connector, thereby causing the seal shoe to slidably contact the peripheral tank wall. A seal member is provided between the outer rim of the pontoon and seal shoe in contact with the level of a stored oil. One end of a weather hood is fixed to the upper portion of the seal shoe, and the other end of the weather hood is made to slide along the surface of an inclined guide provided at the edge of the upper plate of the pontoon.
摘要翻译：一种浮顶式油罐密封装置，其中倾斜连接器在密封靴的上部和浮动浮筒的外缘的下部之间延伸，并且在倾斜连接器的每个端部枢转地支撑通过插入的针脚。压缩弹簧对倾斜连接器施加压力，从而使密封靴与外围罐壁滑动接触。在浮筒的外缘和密封鞋之间设置有密封件，该密封件与储存的油的水平面接触。防风雨罩的一端固定在密封鞋的上部，使防风雨罩的另一端沿着设置在浮筒上板边缘的倾斜导轨的表面滑动。

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