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91. 发明申请

US20090268510A1 DYNAMIC RANDOM ACCESS MEMORY CIRCUIT, DESIGN STRUCTURE AND METHOD 有权
标题翻译：动态随机访问存储器电路，设计结构和方法
公开(公告)号：US20090268510A1
公开(公告)日：2009-10-29
申请号：US12108548
申请日：2008-04-24
申请人： John E. Barth, JR. , Kangguo Cheng , Hoki Kim , Geng Wang
发明人： John E. Barth, JR. , Kangguo Cheng , Hoki Kim , Geng Wang
IPC分类号： G11C11/24 , H01L21/8242
CPC分类号： H01L27/10829 , G11C7/02 , G11C11/4099 , H01L27/10861 , H01L27/10885 , H01L27/10891 , H01L27/10897
摘要： Disclosed is a DRAM circuit that incorporates an improved reference cell, has half the capacitance of the memory cell, does not require a particular reference voltage, and can be formed using the same fabrication processes as the memory cell. This DRAM circuit comprises a memory cell with a single trench capacitor and a reference cell having two trench capacitors. The two reference cell trench capacitors are connected in series through a merged buried capacitor plate such that they provide half the capacitance of the memory cell trench capacitor. Additionally, the reference cell trench capacitors have essentially the same structure as the memory cell trench capacitor so that they can be formed in conjunction with the memory cell trench capacitor. Also disclosed are a design structure for the above-described memory circuit and a method for forming the above-described memory circuit.
摘要翻译：公开了一种DRAM电路，其包含改进的参考单元，具有存储单元的一半电容，不需要特定参考电压，并且可以使用与存储单元相同的制造工艺来形成。该DRAM电路包括具有单沟槽电容器的存储单元和具有两个沟槽电容器的参考单元。两个参考单元沟槽电容器通过合并的埋入式电容器板串联连接，使得它们提供存储单元沟槽电容器的一半的电容。此外，参考单元沟槽电容器具有与存储单元沟槽电容器基本相同的结构，使得它们可以与存储单元沟槽电容器结合形成。还公开了用于上述存储电路的设计结构和用于形成上述存储电路的方法。

92. 发明授权

US07439149B1 Structure and method for forming SOI trench memory with single-sided strap 失效
标题翻译：用单面带形成SOI沟槽存储器的结构和方法
公开(公告)号：US07439149B1
公开(公告)日：2008-10-21
申请号：US11861704
申请日：2007-09-26
申请人： Kangguo Cheng , Ramachandra Divakaruni , Herbert L. Ho , Geng Wang
发明人： Kangguo Cheng , Ramachandra Divakaruni , Herbert L. Ho , Geng Wang
IPC分类号： H01L21/20
CPC分类号： H01L27/10867 , H01L27/0207
摘要： A method of forming a trench memory cell includes forming a trench capacitor within a substrate material, the trench capacitor including a node dielectric layer formed within a trench and a conductive capacitor electrode material formed within the trench in contact with the node dielectric layer; forming a strap mask so as cover one side of the trench and removing one or more materials from an uncovered opposite side of the trench; and forming a conductive buried strap material within the trench; wherein the strap mask is patterned in a manner such that a single-sided buried strap is defined within the trench, the single-sided buried strap configured in a manner such that the deep trench capacitor is electrically accessible at only one side of the trench.
摘要翻译：形成沟槽存储单元的方法包括在衬底材料内形成沟槽电容器，所述沟槽电容器包括形成在沟槽内的节点电介质层和形成在所述沟槽内与所述节点电介质层接触的导电电容器电极材料; 形成带状掩模，以覆盖沟槽的一侧，并从沟槽的未覆盖的相对侧移除一种或多种材料; 以及在所述沟槽内形成导电掩埋带材料; 其中所述带掩模被图案化，使得在所述沟槽内限定单面掩埋带，所述单侧埋入带以使得所述深沟槽电容器仅在所述沟槽的一侧电可访问的方式构造。

93. 发明授权

US07388261B2 Structure and method for accurate deep trench resistance measurement 有权
标题翻译：精确深沟槽电阻测量的结构和方法
公开(公告)号：US07388261B2
公开(公告)日：2008-06-17
申请号：US11853040
申请日：2007-09-11
申请人： Kangguo Cheng , Geng Wang
发明人： Kangguo Cheng , Geng Wang
IPC分类号： H01L29/76
CPC分类号： H01L22/34 , H01L27/1087 , H01L29/8605 , H01L2924/0002 , H01L2924/00
摘要： A test structure for implementing resistance measurement of a deep trench formed in a semiconductor device includes a pair of deep trenches formed within a semiconductor substrate. The pair of deep trenches has a dielectric material formed on side and bottom surfaces thereof, and includes a conductive fill material therein. Bottom portions of the pair of deep trenches are merged with one another so as to provide an electrically conductive path therethrough.
摘要翻译：用于实现在半导体器件中形成的深沟槽的电阻测量的测试结构包括形成在半导体衬底内的一对深沟槽。一对深沟槽具有在其侧表面和底表面上形成的电介质材料，并且在其中包括导电填充材料。一对深沟槽的底部部分彼此合并，以提供穿过其中的导电路径。

94. 发明申请

US20050224852A1 Offset vertical device 失效
标题翻译：偏移垂直装置
公开(公告)号：US20050224852A1
公开(公告)日：2005-10-13
申请号：US10813352
申请日：2004-03-30
申请人： Kangguo Cheng , Ramachandra Divakaruni , Geng Wang
发明人： Kangguo Cheng , Ramachandra Divakaruni , Geng Wang
IPC分类号： H01L21/334 , H01L21/8242 , H01L27/108 , H01L29/94
CPC分类号： H01L27/10867 , H01L27/1087 , H01L29/66181 , H01L29/945
摘要： The present invention includes a method for forming a memory array and the memory array produced therefrom. Specifically, the memory array includes at least one first-type memory device, each of the at least one first-type memory device comprising a first transistor and a first underlying capacitor that are in electrical contact to each other through a first buried strap, where the first buried strap positioned on a first collar region; and at least one second-type memory cell, where each of the at least are second-type memory device comprises a second transistor and a second underlying capacitor that are in electrical contact through an offset buried strap, where the offset buried strap is positioned on a second collar region, wherein the second collar region has a length equal to the first collar region.
摘要翻译：本发明包括一种用于形成存储器阵列的方法和由其制成的存储器阵列。具体而言，存储器阵列包括至少一个第一型存储器件，至少一个第一型存储器件中的每一个包括通过第一掩埋带彼此电接触的第一晶体管和第一底层电容器，其中位于第一环区的第一掩埋带; 以及至少一个第二类型存储单元，其中至少第二类型存储器件中的每一个包括第二晶体管和第二底层电容器，所述第二晶体管和第二底层电容器通过偏移掩埋带电接触，其中所述偏移掩埋带位于第二衣领区域，其中第二衣领区域具有等于第一衣领区域的长度。

95. 发明授权

US08470684B2 Suppression of diffusion in epitaxial buried plate for deep trenches 失效
标题翻译：用于深沟槽的外延掩埋板中的扩散抑制
公开(公告)号：US08470684B2
公开(公告)日：2013-06-25
申请号：US13106349
申请日：2011-05-12
申请人： Chengwen Pei , Geng Wang
发明人： Chengwen Pei , Geng Wang
IPC分类号： H01L21/20
CPC分类号： H01L29/66181 , H01L21/2652 , H01L27/10829 , H01L27/10861 , H01L27/10897 , H01L29/945
摘要： Dopants of a first conductivity type are implanted into a top portion of a semiconductor substrate having a doping of the first conductivity type to increase the dopant concentration in the top portion, which is a first-conductivity-type semiconductor layer. A semiconductor material layer having a doping of the second conductivity type, a buried insulator layer, and a top semiconductor layer are formed thereupon. Deep trenches having a narrow width have a bottom surface within the second-conductivity-type semiconductor layer, which functions as a buried plate. Deep trenches having a wider width are etched into the first-conductivity-type layer underneath, and can be used to form an isolation structure. The additional dopants in the first-conductivity-type semiconductor layer provide a counterdoping against downward diffusion of dopants of the second conductivity type to enhance electrical isolation.
摘要翻译：将第一导电类型的掺杂剂注入到具有第一导电类型的掺杂的半导体衬底的顶部中，以增加作为第一导电型半导体层的顶部中的掺杂剂浓度。在其上形成具有第二导电类型的掺杂的半导体材料层，掩埋绝缘体层和顶部半导体层。具有窄宽度的深沟槽具有在第二导电型半导体层内的底表面，其用作掩埋板。具有较宽宽度的深沟槽被蚀刻到下面的第一导电类型层中，并且可用于形成隔离结构。第一导电型半导体层中的附加掺杂剂提供反向掺杂以抵抗第二导电类型的掺杂剂的向下扩散以增强电隔离。

96. 发明授权

US08299573B2 Trench capacitor 失效
标题翻译：沟槽电容器
公开(公告)号：US08299573B2
公开(公告)日：2012-10-30
申请号：US12818448
申请日：2010-06-18
申请人： Chengwen Pei , Xi Li , Geng Wang
发明人： Chengwen Pei , Xi Li , Geng Wang
IPC分类号： H01L21/02
CPC分类号： H01L29/945 , H01L21/3065 , H01L27/1087 , H01L29/36 , H01L29/66181
摘要： A trench and method of fabrication is disclosed. The trench shape is cylindrosymmetric, and is created by forming a dopant profile that is monotonically increasing in dopant concentration level as a function of depth into the substrate. A dopant sensitive etch is then performed, resulting in a trench shape providing increased surface area, yet having relatively smooth trench walls.
摘要翻译：公开了一种沟槽和制造方法。沟槽形状是圆柱对称的，并且通过形成掺杂剂分布而形成，掺杂剂分布随掺杂剂浓度水平而单调增加，作为进入衬底的深度的函数。然后进行掺杂剂敏感蚀刻，导致沟槽形状提供增加的表面积，但具有相对平滑的沟槽壁。

97. 发明授权

US08236632B2 FET structures with trench implantation to improve back channel leakage and body resistance 有权
标题翻译：具有沟槽注入的FET结构，以改善背沟道泄漏和体电阻
公开(公告)号：US08236632B2
公开(公告)日：2012-08-07
申请号：US12899635
申请日：2010-10-07
申请人： David M. Fried , Jeffrey B. Johnson , Kevin McStay , Paul C. Parries , Chengwen Pei , Gan Wang , Geng Wang , Yanli Zhang
发明人： David M. Fried , Jeffrey B. Johnson , Kevin McStay , Paul C. Parries , Chengwen Pei , Gan Wang , Geng Wang , Yanli Zhang
IPC分类号： H01L21/00 , H01L21/84 , H01L21/338
CPC分类号： H01L29/0847 , H01L21/26586 , H01L27/1203 , H01L29/1083 , H01L29/165 , H01L29/66636 , H01L29/7833
摘要： An FET structure on a semiconductor substrate which includes forming recesses for a source and a drain of the gate structure on a semiconductor substrate, halo implanting regions through the bottom of the source and drain recesses, the halo implanted regions being underneath the gate stack, implanting junction butting at the bottom of the source and drain recesses, and filling the source and drain recesses with a doped epitaxial material. In exemplary embodiments, the semiconductor substrate is a semiconductor on insulator substrate including a semiconductor layer on a buried oxide layer. In exemplary embodiments, the junction butting and halo implanted regions are in contact with the buried oxide layer. In other exemplary embodiments, there is no junction butting. In exemplary embodiments, halo implants implanted to a lower part of the FET body underneath the gate structure provide higher doping level in lower part of the FET body to reduce body resistance, without interfering with FET threshold voltage.
摘要翻译：半导体衬底上的FET结构，其包括在半导体衬底上形成用于栅极结构的源极和漏极的凹槽，通过源极和漏极凹部的底部的晕圈注入区域，位于栅极叠层下方的晕圈注入区域，注入在源极和漏极凹部的底部接合，并且用掺杂的外延材料填充源极和漏极凹部。在示例性实施例中，半导体衬底是在掩埋氧化物层上包括半导体层的绝缘体上半导体衬底。在示例性实施例中，接合对接和晕圈注入区域与掩埋氧化物层接触。在其他示例性实施例中，没有接合对接。在示例性实施例中，注入到栅极结构下面的FET体的下部的卤素注入在FET体的下部提供更高的掺杂水平，以降低体电阻，而不会干扰FET阈值电压。

98. 发明申请

US20120196413A1 METHOD AND STRUCTURE TO IMPROVE BODY EFFECT AND JUNCTION CAPACITANCE 审中-公开
标题翻译：改善身体效能和结电容的方法和结构
公开(公告)号：US20120196413A1
公开(公告)日：2012-08-02
申请号：US13432544
申请日：2012-03-28
申请人： Xiangdong Chen , Geng Wang , Da Zhang
发明人： Xiangdong Chen , Geng Wang , Da Zhang
IPC分类号： H01L21/336
CPC分类号： H01L29/1083 , H01L29/665 , H01L29/66575 , H01L29/78
摘要： A method and structure implant a first-type impurity within a substrate to form a channel region within the substrate adjacent a top surface of the substrate; form a gate stack on the top surface of the substrate above the channel region; and implant a second-type impurity within the substrate to form source and drain regions within the substrate adjacent the top surface. The channel region is positioned between the source and drain regions. The second-type impurity has an opposite polarity with respect to the first-type impurity. The method and structure implant a greater concentration of the first-type impurity, relative to a concentration of the first-type impurity within the channel region, to form a primary body doping region within the substrate below (relative to the top surface) the channel region; and to form secondary body doping regions within the substrate below (relative to the top surface) the source and drain regions.
摘要翻译：一种方法和结构在衬底内注入第一种杂质以在衬底内邻近衬底的顶表面形成沟道区; 在通道区域上方的衬底的顶表面上形成栅极堆叠; 并且在所述衬底内注入第二类型杂质以在所述衬底内邻近所述顶表面形成源区和漏区。沟道区域位于源区和漏区之间。第二种杂质相对于第一种杂质具有相反的极性。所述方法和结构相对于沟道区域内的第一类型杂质的浓度注入更大浓度的第一类型杂质，以在衬底下方（相对于顶表面）在通道内形成主体掺杂区域地区; 并且在源极和漏极区域之下（相对于顶表面）下方的衬底内形成辅助体掺杂区域。

99. 发明申请

US20120187490A1 FET STRUCTURES WITH TRENCH IMPLANTATION TO IMPROVE BACK CHANNEL LEAKAGE AND BODY RESISTANCE 有权
标题翻译：具有TRENCH植入的FET结构以提高反向通道泄漏和体电阻
公开(公告)号：US20120187490A1
公开(公告)日：2012-07-26
申请号：US13426547
申请日：2012-03-21
申请人： David M. Fried , Jeffrey B. Johnson , Kevin McStay , Paul C. Parries , Chengwen Pei , Gan Wang , Geng Wang , Yanli Zhang
发明人： David M. Fried , Jeffrey B. Johnson , Kevin McStay , Paul C. Parries , Chengwen Pei , Gan Wang , Geng Wang , Yanli Zhang
IPC分类号： H01L29/78
CPC分类号： H01L29/0847 , H01L21/26586 , H01L27/1203 , H01L29/1083 , H01L29/165 , H01L29/66636 , H01L29/7833
摘要： A field effect transistor (FET) structure on a semiconductor substrate which includes a gate structure having a spacer on a semiconductor substrate; an extension implant underneath the gate structure; a recessed source and a recessed drain filled with a doped epitaxial material; halo implanted regions adjacent a bottom of the recessed source and drain and being underneath the gate stack. In an exemplary embodiment, there is implanted junction butting underneath the bottom of each of the recessed source and drain, the junction butting being separate and distinct from the halo implanted regions. In another exemplary embodiment, the doped epitaxial material is graded from a lower dopant concentration at a side of the recessed source and drain to a higher dopant concentration at a center of the recessed source and drain. In a further exemplary embodiment, the semiconductor substrate is a semiconductor on insulator substrate.
摘要翻译：一种半导体衬底上的场效应晶体管（FET）结构，其包括在半导体衬底上具有间隔物的栅极结构; 栅极结构下面的延伸植入物; 凹陷的源极和填充有掺杂的外延材料的凹陷的漏极; 邻近凹陷源的底部的卤素注入区域和漏极并位于栅极叠层下方。在示例性实施例中，在凹陷源和漏极中的每一个的底部下方注入结合对接，该接合部分与光晕注入区域分开且不同。在另一个示例性实施例中，掺杂的外延材料从凹陷源的一侧的较低掺杂剂浓度和漏极分级到凹陷源极和漏极的中心处的较高掺杂剂浓度。在另一示例性实施例中，半导体衬底是绝缘体上半导体衬底。

100. 发明申请

US20120139085A1 Structure and Method for Topography Free SOI Integration 有权
标题翻译：地形自由SOI集成的结构与方法
公开(公告)号：US20120139085A1
公开(公告)日：2012-06-07
申请号：US12958429
申请日：2010-12-02
申请人： Ravi M. Todi , Joseph Ervin , Chengwen Pei , Geng Wang
发明人： Ravi M. Todi , Joseph Ervin , Chengwen Pei , Geng Wang
IPC分类号： H01L29/38 , H01L21/3213
CPC分类号： H01L29/02 , H01L21/76254
摘要： A semiconductor structure is provided that includes a semiconductor oxide layer having features. The semiconductor oxide layer having the features is located between an active semiconductor layer and a handle substrate. The semiconductor structure includes a planarized top surface of the active semiconductor layer such that the semiconductor oxide layer is beneath the planarized top surface. The features within the semiconductor oxide layer are mated with a surface of the active semiconductor layer.
摘要翻译：提供了包括具有特征的半导体氧化物层的半导体结构。具有特征的半导体氧化物层位于有源半导体层和手柄基板之间。半导体结构包括有源半导体层的平坦化顶表面，使得半导体氧化物层位于平坦化的顶表面之下。半导体氧化物层内的特征与有源半导体层的表面配合。

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