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91. 发明授权

US06589813B1 Chip size stack package and method of fabricating the same 失效
标题翻译：芯片尺寸堆叠封装及其制造方法
公开(公告)号：US06589813B1
公开(公告)日：2003-07-08
申请号：US09604089
申请日：2000-06-27
申请人： Sang Wook Park
发明人： Sang Wook Park
IPC分类号： H01L2144
CPC分类号： H01L24/05 , H01L21/56 , H01L23/3185 , H01L23/49575 , H01L24/03 , H01L24/45 , H01L24/48 , H01L2224/04042 , H01L2224/05624 , H01L2224/05644 , H01L2224/05655 , H01L2224/32245 , H01L2224/451 , H01L2224/48091 , H01L2224/48247 , H01L2224/4826 , H01L2224/48463 , H01L2224/73215 , H01L2224/85399 , H01L2924/00014 , H01L2924/01006 , H01L2924/01013 , H01L2924/01024 , H01L2924/01027 , H01L2924/01028 , H01L2924/01029 , H01L2924/0105 , H01L2924/01078 , H01L2924/01079 , H01L2924/014 , H01L2924/07811 , H01L2924/12042 , H01L2924/181 , H01L2924/30105 , H01L2224/45099 , H01L2924/00012 , H01L2924/00 , H01L2924/00015 , H01L2224/05599
摘要： Disclosed are a chip size stack package and a method of fabricating the same. Two semiconductor chips are arranged such that their bond pads-forming surfaces are opposed to each other. Insulating layers are applied to the bond pads-forming surfaces of the semiconductor chips, and via-holes for exposing bond pads are formed in the insulating layers. Metal traces which are exposed at both sides of the insulating layers are formed on the via-holes, whereby the insulating layers are bonded to each other and the metal traces are also bonded to each other. One ends of metal wires are connected to the metal traces which are exposed at the insulating layers, and both sides of the semiconductor chips are molded by an encapsulate such that the other ends of the metal wires are exposed. Instead of the metal wires, pattern tapes can be used. One ends of the pattern tapes are electrically connected to the metal traces when the insulating layers are bonded to each other, and the other ends of the pattern tapes are exposed. In this case, a space between the staked semiconductor chips is also molded. In place of the encapsulate, an anisotrophic conductive adhesive can be intervened between the semiconductor chips. A heat sink can be attached to a surface of the upper semiconductor chip.
摘要翻译：公开了一种芯片尺寸的堆叠封装及其制造方法。两个半导体芯片布置成使得它们的焊盘形成表面彼此相对。将绝缘层施加到半导体芯片的接合焊盘形成表面，并且在绝缘层中形成用于暴露接合焊盘的通孔。在通孔上形成有在绝缘层的两侧露出的金属迹线，由此绝缘层彼此接合并且金属迹线也彼此结合。金属线的一端连接到暴露在绝缘层的金属迹线，半导体芯片的两侧通过使金属线的另一端露出的封装而成型。代替金属线，可以使用图案带。当绝缘层彼此接合时，图案带的一端电连接到金属迹线，图案带的另一端露出。在这种情况下，也模制了加盖的半导体芯片之间的空间。代替封装，可以在半导体芯片之间插入各向异性导电粘合剂。可以将散热器附接到上半导体芯片的表面。

92. 发明授权

US06519846B2 Chip size package and method of fabricating the same 有权
标题翻译：芯片尺寸封装及其制造方法
公开(公告)号：US06519846B2
公开(公告)日：2003-02-18
申请号：US09782699
申请日：2001-02-13
申请人： Sang Wook Park , Ji Yon Kim
发明人： Sang Wook Park , Ji Yon Kim
IPC分类号： H05K330
CPC分类号： H01L24/03 , H01L23/24 , H01L23/3171 , H01L24/05 , H01L24/11 , H01L24/13 , H01L24/45 , H01L24/48 , H01L29/0657 , H01L2224/02235 , H01L2224/02255 , H01L2224/02317 , H01L2224/02319 , H01L2224/02321 , H01L2224/0233 , H01L2224/02335 , H01L2224/0235 , H01L2224/02379 , H01L2224/02381 , H01L2224/031 , H01L2224/03334 , H01L2224/0401 , H01L2224/04042 , H01L2224/05548 , H01L2224/11334 , H01L2224/1134 , H01L2224/13076 , H01L2224/13082 , H01L2224/131 , H01L2224/13144 , H01L2224/451 , H01L2224/45144 , H01L2224/4813 , H01L2224/48227 , H01L2224/48599 , H01L2224/94 , H01L2924/00014 , H01L2924/01013 , H01L2924/01024 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/0105 , H01L2924/01056 , H01L2924/0106 , H01L2924/01075 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/10157 , H01L2924/12041 , H01L2924/14 , H01L2924/15311 , H01L2924/16152 , H01L2924/181 , Y10T29/4913 , Y10T29/49144 , Y10T29/49147 , Y10T29/49149 , Y10T29/49155 , H01L2224/02 , H01L2224/03 , H01L2924/00 , H01L2924/00015 , H01L2224/05599
摘要： A chip size package is disclosed herein, as well as a method for fabricating the same. A recess is formed in a surface of semiconductor chip. Bonding pads are formed on a bottom center of the recess and insulating pads 30 are formed on both lateral sides of the recess. The respective pads are connected to each other with metal wires. An epoxy compound is filled in the recess. Herein, midway portions of the metal wires are exposed from the epoxy compound. Bumps are formed on the midway portions of the metal wires being exposed from the epoxy compound and solder balls are mounted on the bumps. Therefore, the epoxy compound is not protruded from the semiconductor chip, thickness of the package is equal to that of the semiconductor chip. The thickness of package is minimized.
摘要翻译：本文公开了一种芯片尺寸封装以及其制造方法。在半导体芯片的表面形成凹部。接合垫形成在凹部的底部中心，并且绝缘垫30形成在凹部的两个侧面上。各个焊盘用金属线彼此连接。在凹槽中填充环氧化合物。这里，金属线的中间部分从环氧化合物露出。在从环氧化合物暴露的金属线的中间部分形成有凸起，并且焊球安装在凸块上。因此，环氧化合物不从半导体芯片突出，封装的厚度等于半导体芯片的厚度。包装的厚度最小化。

93. 发明授权

US06281118B1 Method of manufacturing semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US06281118B1
公开(公告)日：2001-08-28
申请号：US09328695
申请日：1999-06-09
申请人： Sang Wook Park
发明人： Sang Wook Park
IPC分类号： H01L214763
CPC分类号： H01L21/76838
摘要： A method of manufacturing semiconductor device which can reduce contact resistance and stabilize contact interface, is disclosed. According to the present invention, firstly, a semiconductor substrate on which a lower conductor pattern is formed is provided. The lower conductor pattern has a first doped polysilicon layer and a first tungsten silicide layer formed thereon. Next, an intermediate insulating layer is formed on the substrate. The intermediate insulating layer is then etched to expose a portion of the surface of the first tungsten silicide layer of the lower conductor pattern, thereby forming a contact hole. Thereafter the substrate in which the contact hole is formed, is thermally treated by rapid thermal processing under H2 atmosphere. A second doped polysilicon layer and the second tungsten silicide layer are then formed on the surface of the contact hole treated thermally and on the intermediate insulating, sequentially. Thereafter the second tungsten silicide layer and the second doped polysilicon layer are patterned to form an upper conductor pattern being in contact with the lower conductor pattern.
摘要翻译：公开了一种能够降低接触电阻并稳定接触界面的半导体器件的制造方法。根据本发明，首先，提供形成有下导体图案的半导体基板。下导体图案具有形成在其上的第一掺杂多晶硅层和第一硅化钨层。接下来，在基板上形成中间绝缘层。然后蚀刻中间绝缘层以暴露下导体图案的第一硅化钨层的一部分表面，从而形成接触孔。此后，在H2气氛下通过快速热处理热处理形成有接触孔的基板。然后依次在热处理和中间绝缘的接触孔的表面上形成第二掺杂多晶硅层和第二硅化钨层。此后，第二硅化钨层和第二掺杂多晶硅层被图案化以形成与下导体图案接触的上导体图案。

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