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91. 发明申请

US20110213930A1 Multi-level cell memory device and method thereof 有权
标题翻译：多级单元存储装置及其方法
公开(公告)号：US20110213930A1
公开(公告)日：2011-09-01
申请号：US13067099
申请日：2011-05-09
申请人： Sung Chung Park , Jun Jin Kong , Young Hwan Lee , Dong Ku Kang
发明人： Sung Chung Park , Jun Jin Kong , Young Hwan Lee , Dong Ku Kang
IPC分类号： G06F12/08
CPC分类号： G11C11/5621 , G11C7/1006 , G11C29/00
摘要： A Multi-Level Cell (MLC) memory device and method thereof are provided. The example MLC memory device may be configured to perform data operations, and may include an MLC memory cell, a first coding device performing a first coding function, the first coding function being one of an encoding function and a decoding function, a second coding device performing a second coding function, the second coding function being one of an encoding function and a decoding function and a signal module configured to perform at least one of instructing the MLC memory cell to store data output by the second coding device if the first and second coding functions are encoding functions, and generating a demapped bit stream based on data retrieved from the MLC memory cell if the first and second coding functions are decoding functions.
摘要翻译：提供了一种多级单元（MLC）存储器件及其方法。示例MLC存储器件可以被配置为执行数据操作，并且可以包括MLC存储器单元，执行第一编码功能的第一编码装置，作为编码功能和解码功能之一的第一编码功能，第二编码装置执行第二编码功能，所述第二编码功能是编码功能和解码功能之一;以及信号模块，被配置为执行指令所述MLC存储器单元存储由所述第二编码装置输出的数据中的至少一个，如果所述第一和第二编码功能编码功能是编码功能，并且如果第一和第二编码功能是解码功能，则基于从MLC存储器单元检索的数据来生成解映射比特流。

92. 发明授权

US07962841B2 Data decoding apparatus and method in a communication system 有权
标题翻译：通信系统中的数据解码装置和方法
公开(公告)号：US07962841B2
公开(公告)日：2011-06-14
申请号：US11592381
申请日：2006-11-03
申请人： Shi-Chang Rho , Jun Jin Kong
发明人： Shi-Chang Rho , Jun Jin Kong
IPC分类号： H03M13/03
CPC分类号： H03M13/4184 , H03M13/4169 , H03M13/6502
摘要： A majority voting Viterbi decoder includes a branch metric calculator (BMC) for measuring a difference between a received symbol and a reference symbol and outputting branch metrics from the difference; an add-compare-selection (ACS) unit for determining an optimal path using the branch metrics; a survival path memory unit for outputting decoded symbols by performing decoding based on the optimal path; and a majority voting unit for determining a final decoded symbol by performing majority voting for the decoded symbols output from the survival path memory unit. Accordingly, by adding the majority voting unit, a decoding depth can be reduced without the loss of an encoding gain required in a system, and by reducing the decoding depth, miniaturization is possible, power consumption can be reduced, and a processing delay in a memory can be minimized.
摘要翻译：多数投票维特比解码器包括用于测量接收符号和参考符号之间的差分的分支度量计算器（BMC），并从差值输出分支度量; 加法比较选择（ACS）单元，用于使用所述分支度量确定最优路径; 存储路径存储单元，用于通过基于最优路径进行解码来输出解码符号; 以及多数投票单元，用于通过对从生存路径存储单元输出的解码符号执行多数投票来确定最终解码符号。因此，通过添加多数投票单元，可以在不损失系统所需的编码增益的情况下减少解码深度，并且通过降低解码深度，可以实现小型化，能够降低功耗，并且可以减少处理延迟记忆可以最小化。

93. 发明授权

US07957475B2 Dual carrier modulation (DCM) demapper and DCM demapping method 有权
标题翻译：双载波调制（DCM）解映射器和DCM解映射方法
公开(公告)号：US07957475B2
公开(公告)日：2011-06-07
申请号：US11704907
申请日：2007-02-12
申请人： Sung Chung Park , Yun Young Kim , Jun Jin Kong , Jae Ho Roh
发明人： Sung Chung Park , Yun Young Kim , Jun Jin Kong , Jae Ho Roh
IPC分类号： H04K1/10
CPC分类号： H04L27/2649 , H04L25/022 , H04L25/067 , H04L27/3416
摘要： A DCM demapper and a DCM demapping method are provided. The DCM demapper includes: a basic signal generation unit generating a plurality of basic signals using a signal and channel information of two subcarriers; a soft decision generation unit generating a plurality of soft decisions using the plurality of basic signals; and a soft decision selection unit selecting a soft decision corresponding to each bit of the two subcarriers among the generated soft decisions.
摘要翻译：提供DCM解映射器和DCM解映射方法。 DCM解映射器包括：使用信号和两个子载波的信道信息生成多个基本信号的基本信号生成单元; 软判决生成单元，使用所述多个基本信号生成多个软判决; 以及软判决选择单元，在所生成的软决策中选择与所述两个子载波的每个比特相对应的软判决。

94. 发明授权

US07843727B2 Memory device and data reading method 有权
标题翻译：存储器和数据读取方式
公开(公告)号：US07843727B2
公开(公告)日：2010-11-30
申请号：US12232138
申请日：2008-09-11
申请人： Kyoung Lae Cho , Donghun Yu , Yoon Dong Park , Jun Jin Kong , Jae Hong Kim , Heeseok Eun
发明人： Kyoung Lae Cho , Donghun Yu , Yoon Dong Park , Jun Jin Kong , Jae Hong Kim , Heeseok Eun
IPC分类号： G11C16/04
CPC分类号： G11C11/5642 , G11C16/3418 , G11C29/00
摘要： A memory device and a memory data reading method are provided. The memory device may include: a multi-bit cell array; a programming unit that stores N data pages in a memory page in the multi-bit cell array; and a control unit that divides the N data pages into a first group and second group, reads data of the first group from the memory page, and determines a scheme of reading data of the second group from the memory page based on the read data of the first group.
摘要翻译：提供存储器件和存储器数据读取方法。存储器件可以包括：多位单元阵列; 编程单元，其将N个数据页存储在多位单元阵列中的存储器页面中; 以及控制单元，其将N个数据页划分为第一组和第二组，从存储器页面读取第一组的数据，并且基于读取的数据确定从存储器页面读取第二组的数据的方案第一组。

95. 发明申请

US20100251077A1 STORAGE DEVICE AND DATA STORAGE SYSTEM INCLUDING OF THE SAME 审中-公开
标题翻译：存储设备和包括其的数据存储系统
公开(公告)号：US20100251077A1
公开(公告)日：2010-09-30
申请号：US12729285
申请日：2010-03-23
申请人： Yong June Kim , Jae Hong Kim , Jun Jin Kong , Hong Rak Son
发明人： Yong June Kim , Jae Hong Kim , Jun Jin Kong , Hong Rak Son
IPC分类号： G06F12/02 , H03M13/05 , G06F11/10
CPC分类号： G06F11/1048
摘要： A storage device includes a controller unit and a memory cell array. The controller unit is for outputting data through a first data path or a second data path according to a property of externally supplied input data. The memory cell array includes a first memory and a second memory, and receives and stores the data from the controller unit output through the first and second data paths. The first memory has a different memory cell structure than the second memory.
摘要翻译：存储装置包括控制器单元和存储单元阵列。控制器单元用于根据外部提供的输入数据的属性通过第一数据路径或第二数据路径输出数据。存储单元阵列包括第一存储器和第二存储器，并且通过第一和第二数据路径接收并存储来自控制器单元输出的数据。第一存储器具有与第二存储器不同的存储单元结构。

96. 发明授权

US07706181B2 Multi-bit programming device and method using single-bit memory cells 有权
标题翻译：多位编程设备和使用单位存储单元的方法
公开(公告)号：US07706181B2
公开(公告)日：2010-04-27
申请号：US11896349
申请日：2007-08-31
申请人： Sung-Jae Byun , Dong Hyuk Chae , Kyoung Lae Cho , Jun Jin Kong , Young Hwan Lee , Seung Jae Lee , Nam Phil Jo , Dong Ku Kang
发明人： Sung-Jae Byun , Dong Hyuk Chae , Kyoung Lae Cho , Jun Jin Kong , Young Hwan Lee , Seung Jae Lee , Nam Phil Jo , Dong Ku Kang
IPC分类号： G11C11/34 , G11C16/04
CPC分类号： G11C11/5628 , G11C2211/5621 , G11C2211/5641
摘要： A multi-bit programming device and method for a non-volatile memory are provided. In one example embodiment, a multi-bit programming device may include a multi-bit programming unit configured to multi-bit program original multi-bit data to a target memory cell in a memory cell array, and a backup programming unit configured to select backup memory cells in the memory cell array with respect to each bit of the original multi-bit data, and program each bit of the original multi-bit data to a respective one of the selected backup memory cells.
摘要翻译：提供了一种用于非易失性存储器的多位编程设备和方法。在一个示例实施例中，多位编程设备可以包括多位编程单元，其被配置为将原始多位数据多位地编程到存储单元阵列中的目标存储器单元，以及备份编程单元，被配置为选择备份相对于原始多位数据的每个位存储单元阵列中的存储器单元，以及将原始多位数据的每个位编程到所选择的备份存储器单元中的相应一个。

97. 发明申请

US20090222701A1 Apparatus for determining number of bits to be stored in memory cell 失效
标题翻译：用于确定要存储在存储单元中的位数的装置
公开(公告)号：US20090222701A1
公开(公告)日：2009-09-03
申请号：US12219103
申请日：2008-07-16
申请人： Seung-Hwan Song , Kyoung Lae Cho , Jun Jin Kong , Jae Hong Kim
发明人： Seung-Hwan Song , Kyoung Lae Cho , Jun Jin Kong , Jae Hong Kim
IPC分类号： G06F11/00 , G06F12/16
CPC分类号： G11C11/56 , G06F11/1012 , G11C29/00
摘要： Example embodiments relate to an apparatus which may determine a length of data to be stored in a memory cell, and may store the data in a memory based on the determined length. A memory data storage apparatus according to example embodiments may, include: a determination unit that may determine a number of bits of data and a number of bits of data detection information to be stored in a memory cell; a data receiving unit that may receive data corresponding to the determined number of bits; an error correction coding unit that may perform an error correction coding with respect to the received data and generate data detection information corresponding to the number of bits of the data detection information; and a data storage unit that may store the received data and generated data detection information in the memory cell.
摘要翻译：示例性实施例涉及可以确定要存储在存储器单元中的数据的长度的装置，并且可以基于所确定的长度将数据存储在存储器中。根据示例实施例的存储器数据存储装置可以包括：确定单元，其可以确定要存储在存储器单元中的数据的位数和数据检测信息的位数; 数据接收单元，其可以接收与所确定的位数相对应的数据; 纠错编码单元，其可以对所接收的数据执行纠错编码，并生成与数据检测信息的位数相对应的数据检测信息; 以及数据存储单元，其可以将所接收的数据和生成的数据检测信息存储在存储单元中。

98. 发明申请

US20090190396A1 Memory device and method of reading memory data 有权
标题翻译：存储器件和读取存储器数据的方法
公开(公告)号：US20090190396A1
公开(公告)日：2009-07-30
申请号：US12219264
申请日：2008-07-18
申请人： Kyoung Lae Cho , Dong Hun Yu , Jun Jin Kong , Seung-Hwan Song , Yoon Dong Park , Jong Han Kim , Young Hwan Lee
发明人： Kyoung Lae Cho , Dong Hun Yu , Jun Jin Kong , Seung-Hwan Song , Yoon Dong Park , Jong Han Kim , Young Hwan Lee
IPC分类号： G11C16/06 , G11C7/00
CPC分类号： G11C16/34 , G11C11/5642 , G11C2211/5634
摘要： A memory device and a method of reading multi-bit data stored in a multi-bit cell array may be provided. The memory device may include a multi-bit cell array including a least one memory page with each memory page having a plurality of multi-bit cells, and a determination unit to divide the plurality of multi-bit cells into a first group and second group. The first group may include multi-bit cells with a threshold voltage higher than a reference voltage. The second group may include multi-bit cells with a threshold voltage lower than the reference voltage. The determination unit may sequentially update the first group and second group while changing the reference voltage.
摘要翻译：可以提供存储器件和读取存储在多位单元阵列中的多位数据的方法。存储器件可以包括多比特单元阵列，其包括至少一个存储器页，每个存储器页具有多个多位单元，以及确定单元，用于将多个多位单元划分成第一组和第二组。第一组可以包括具有高于参考电压的阈值电压的多位单元。第二组可以包括阈值电压低于参考电压的多位单元。确定单元可以在改变参考电压的同时顺序地更新第一组和第二组。

99. 发明申请

US20090177931A1 Memory device and error control codes decoding method 有权
标题翻译：存储器件和错误控制代码解码方法
公开(公告)号：US20090177931A1
公开(公告)日：2009-07-09
申请号：US12153121
申请日：2008-05-14
申请人： Seung-Hwan Song , Jun Jin Kong , Jae Hong Kim , Kyoung Lae Cho , Sung Chung Park
发明人： Seung-Hwan Song , Jun Jin Kong , Jae Hong Kim , Kyoung Lae Cho , Sung Chung Park
IPC分类号： G06F11/07 , G06F11/00
CPC分类号： G06F11/141 , G06F11/1012 , G06F11/1072 , G11C11/5642 , G11C16/10 , G11C29/00
摘要： Memory devices and/or error control codes (ECC) decoding methods may be provided. A memory device may include a memory cell array, and a decoder to perform hard decision decoding of first data read from the memory cell array by a first read scheme, and to generate output data and error information of the output data. The memory device may also include and a control unit to determine an error rate of the output data based on the error information, and to determine whether to transmit an additional read command for soft decision decoding to the memory cell array based on the error rate. An ECC decoding time may be reduced through such a memory device.
摘要翻译：可以提供存储器件和/或错误控制代码（ECC）解码方法。存储器件可以包括存储单元阵列和解码器，以通过第一读取方案对从存储器单元阵列读取的第一数据进行硬判决解码，并且生成输出数据和输出数据的输出数据和错误信息。存储器装置还可以包括和控制单元，用于基于错误信息确定输出数据的错误率，并且基于错误率来确定是否向存储器单元阵列发送用于软判决解码的附加读命令。可以通过这样的存储器件来减少ECC解码时间。

100. 发明申请

US20090122929A1 Apparatus and method for cancelling interferences between orthogonal coded signals in mobile communication system 有权
标题翻译：用于消除移动通信系统中的正交编码信号之间的干扰的装置和方法
公开(公告)号：US20090122929A1
公开(公告)日：2009-05-14
申请号：US12155395
申请日：2008-06-03
申请人： Donghun Yu , Jun Jin Kong , Sung Chung Park
发明人： Donghun Yu , Jun Jin Kong , Sung Chung Park
IPC分类号： H04B1/10
CPC分类号： H04L25/0204 , H04B1/71052 , H04L25/0224 , H04L25/0246
摘要： Apparatuses and methods for cancelling interferences between signals are provided. The apparatuses includes: a receiving unit that receives an orthogonal coded signal from a transmitter and generates a received vector; a channel estimation unit that estimates a state of a wireless channel from the transmitter to the apparatus where the cancelling of the interference between signals is performed and generates a channel state matrix; a Q-R decomposition unit that performs Q-R decomposition with respect to the generated channel state matrix and generates a Q matrix and an R matrix, and generates a decision statistic vector based on the generated Q matrix and the received vector; and a signal determination unit that determines a received signal with interference from the orthogonal coded signal being decreased based on the generated decision statistics vector.
摘要翻译：提供了消除信号间干扰的装置和方法。所述装置包括：接收单元，其从发射机接收正交编码信号并产生接收矢量; 信道估计单元，其估计从发射机到其中执行消除信号之间的干扰的装置的无线信道的状态，并产生信道状态矩阵; Q-R分解单元，对所生成的信道状态矩阵进行Q-R分解，生成Q矩阵和R矩阵，并根据生成的Q矩阵和接收矢量生成判定统计量矢量; 以及信号确定单元，其基于所生成的判定统计矢量，确定来自正交编码信号的干扰的接收信号被减少。

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