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91. 发明授权

US06482707B1 Method of improving static refresh 有权
标题翻译：改善静态刷新的方法
公开(公告)号：US06482707B1
公开(公告)日：2002-11-19
申请号：US09532094
申请日：2000-03-21
申请人： Mark Fischer , Charles H. Dennison , Fawad Ahmed , Richard H. Lane , John K. Zahurak , Kunal R. Parekh
发明人： Mark Fischer , Charles H. Dennison , Fawad Ahmed , Richard H. Lane , John K. Zahurak , Kunal R. Parekh
IPC分类号： H01L21336
CPC分类号： H01L29/6659 , H01L21/2652 , H01L21/28247 , H01L29/6656
摘要： A double blanket ion implant method for forming diffusion regions in memory array devices, such as a MOSFET access device is disclosed. The method provides a semiconductor substrate with a gate structure formed on its surface Next, a first pair of diffusion regions are formed in a region adjacent to the channel region by a first blanket ion implantation process. The first blanket ion implantation process has a first energy level and dose. The device is subjected to oxidizing conditions, which form oxidized sidewalls on the gate structure. A second blanket ion implantation process is conducted at the same location as the first ion implantation process adding additional dopant to the diffusion regions. The second blanket ion implantation process has a second energy level and dose. The resultant diffusion regions provide the device with improved static refresh performance over prior art devices. In addition, the first and second energy levels and doses are substantially lower than an energy level and dose used in a prior art single implantation process.
摘要翻译：公开了一种用于在诸如MOSFET访问装置的存储器阵列器件中形成扩散区的双层覆盖离子注入方法。该方法提供了在其表面上形成栅极结构的半导体衬底。接下来，通过第一覆盖离子注入工艺在与沟道区相邻的区域中形成第一对扩散区。第一次毯式离子注入工艺具有第一能级和剂量。该器件经受氧化条件，其在栅极结构上形成氧化的侧壁。在与第一离子注入工艺相同的位置处进行第二覆盖离子注入工艺，向扩散区域添加额外的掺杂剂。第二次毯子离子注入过程具有第二能量水平和剂量。所得到的扩散区域提供了比现有技术的装置更好的静态刷新性能的装置。此外，第一和第二能量水平和剂量基本上低于现有技术单一植入过程中使用的能级和剂量。

92. 发明授权

US06410951B1 Structure for improving static refresh 有权
公开(公告)号：US06410951B1
公开(公告)日：2002-06-25
申请号：US09822249
申请日：2001-04-02
申请人： Mark Fischer , Charles H. Dennison , Fawad Ahmed , Richard H. Lane , John K. Zahurak , Kunal R. Parekh
发明人： Mark Fischer , Charles H. Dennison , Fawad Ahmed , Richard H. Lane , John K. Zahurak , Kunal R. Parekh
IPC分类号： H01L21336
摘要： A double blanket ion implant method for forming diffusion regions in memory array devices, such as a MOSFET access device is disclosed. The method provides a semiconductor substrate with a gate structure formed on its surface. Next, a first pair of diffusion regions are formed in a region adjacent to the channel region by a first blanket ion implantation process. The first blanket ion implantation process has a first energy level and dose. The device is subjected to oxidizing conditions, which form oxidized sidewalls on the gate structure. A second blanket ion implantation process is conducted at the same location as the first ion implantation process adding additional dopant to the diffusion regions. The second blanket ion implantation process has a second energy level and dose. The resultant diffusion regions provide the device with improved static refresh performance over prior art devices. In addition, the first and second energy levels and doses are substantially lower than an energy level and dose used in a prior art single implantation process.

93. 发明授权

US06406977B2 Isolation region forming methods 失效
标题翻译：隔离区形成方法
公开(公告)号：US06406977B2
公开(公告)日：2002-06-18
申请号：US09521095
申请日：2000-03-07
申请人： David L. Dickerson , Richard H. Lane , Charles H. Dennison , Kunal R. Parekh , Mark Fischer , John K. Zahurak
发明人： David L. Dickerson , Richard H. Lane , Charles H. Dennison , Kunal R. Parekh , Mark Fischer , John K. Zahurak
IPC分类号： H01L2176
CPC分类号： H01L21/76232 , H01L21/0332 , H01L21/76235
摘要： In one aspect, the invention includes an isolation region forming method comprising: a) forming an oxide layer over a substrate; b) forming a nitride layer over the oxide layer, the nitride layer and oxide layer having a pattern of openings extending therethrough to expose portions of the underlying substrate; c) etching the exposed portions of the underlying substrate to form openings extending into the substrate; d) after etching the exposed portions of the underlying substrate, removing portions of the nitride layer while leaving some of the nitride layer remaining over the substrate; and e) after removing portions of the nitride layer, forming oxide within the openings in the substrate, the oxide within the openings forming at least portions of isolation regions. In another aspect, the invention includes an isolation region forming method comprising: a) forming a silicon nitride layer over a substrate; b) forming a masking layer over the silicon nitride layer; c) forming a pattern of openings extending through the masking layer to the silicon nitride layer; d) extending the openings through the silicon nitride layer to the underlying substrate, the silicon nitride layer having edge regions proximate the openings and having a central region between the edge regions; e) extending the openings into the underlying substrate; f) after extending the openings into the underlying substrate, reducing a thickness of the silicon nitride layer at the edge regions to thin the edge regions relative to the central region; and g) forming oxide within the openings.
摘要翻译：一方面，本发明包括一种隔离区形成方法，包括：a）在衬底上形成氧化物层; b）在所述氧化物层上形成氮化物层，所述氮化物层和氧化物层具有延伸穿过其中的开口图案以暴露所述下面的衬底的部分; c）蚀刻下面的衬底的暴露部分以形成延伸到衬底中的开口; d）在蚀刻下面的衬底的暴露部分之后，去除氮化物层的部分，同时留下一些保留在衬底上的氮化物层; 以及e）在去除所述氮化物层的部分之后，在所述衬底的所述开口内形成氧化物，所述开口内的氧化物形成至少部分隔离区域。另一方面，本发明包括一种隔离区形成方法，包括：a）在衬底上形成氮化硅层; b）在氮化硅层上形成掩模层; c）形成延伸穿过掩模层的开口图案到氮化硅层; d）将开口穿过氮化硅层延伸到下面的衬底，氮化硅层具有靠近开口的边缘区域，并且在边缘区域之间具有中心区域; e）将开口延伸到下面的基底中; f）在将开口延伸到下面的基底之后，减小边缘区域处的氮化硅层的厚度，以使边缘区域相对于中心区域变薄; 和g）在开口内形成氧化物。

94. 发明申请

US20120117014A1 METHOD AND SYSTEM FOR SELECTING A SYNCHRONOUS OR ASYNCHRONOUS PROCESS TO DETERMINE A FORECAST 有权
标题翻译：选择同步或异步过程以确定预测的方法和系统
公开(公告)号：US20120117014A1
公开(公告)日：2012-05-10
申请号：US13353265
申请日：2012-01-18
申请人： Kedar Doshi , Mark Fischer , Evan Chou
发明人： Kedar Doshi , Mark Fischer , Evan Chou
IPC分类号： G06N5/00
CPC分类号： G06Q10/04 , G06Q10/0639 , G06Q30/0202
摘要： In accordance with embodiments, there are provided mechanisms and methods for selecting a synchronous or asynchronous process to determine a forecast. These mechanisms and methods for such synchronous/asynchronous process selection can enable embodiments to determine forecasts for multiple users (e.g. with hierarchical relationships, etc.) over an arbitrary time interval. The ability of embodiments to provide forecasts that involve such a large amount of data in an effective way can enable forecasting that was otherwise infeasible due to resource limitations.
摘要翻译：根据实施例，提供了用于选择同步或异步过程以确定预测的机制和方法。用于这种同步/异步过程选择的这些机制和方法可使得实施例能够在任意时间间隔上确定多个用户的预测（例如，具有层次关系等）。实施例以有效的方式提供涉及这样大量数据的预测的能力可以使由于资源限制而导致的预测是不可行的。

95. 发明申请

US20120117013A1 METHOD AND SYSTEM FOR SELECTING A SYNCHRONOUS OR ASYNCHRONOUS PROCESS TO DETERMINE A FORECAST 有权
标题翻译：选择同步或异步过程以确定预测的方法和系统
公开(公告)号：US20120117013A1
公开(公告)日：2012-05-10
申请号：US13353260
申请日：2012-01-18
申请人： Kedar Doshi , Mark Fischer , Evan Chou
发明人： Kedar Doshi , Mark Fischer , Evan Chou
IPC分类号： G06N5/00
CPC分类号： G06Q10/04 , G06Q10/0639 , G06Q30/0202
摘要： In accordance with embodiments, there are provided mechanisms and methods for selecting a synchronous or asynchronous process to determine a forecast. These mechanisms and methods for such synchronous; asynchronous process selection can enable embodiments to determine forecasts for multiple users (e.g. with hierarchical relationships, etc.) over an arbitrary time interval. The ability of embodiments to provide forecasts that involve such a large amount of data in an effective way can enable forecasting that was otherwise infeasible due to resource limitations.
摘要翻译：根据实施例，提供了用于选择同步或异步过程以确定预测的机制和方法。这些同步的机制和方法; 异步过程选择可使得实施例能够在任意时间间隔内确定多个用户的预测（例如，具有层次关系等）。实施例以有效的方式提供涉及这样大量数据的预测的能力可以使由于资源限制而导致的预测是不可行的。

96. 发明授权

US08012674B2 Efficient pitch multiplication process 有权
标题翻译：高效的音调乘法过程
公开(公告)号：US08012674B2
公开(公告)日：2011-09-06
申请号：US12687005
申请日：2010-01-13
申请人： Mark Fischer , Stephen Russell , H. Montgomery Manning
发明人： Mark Fischer , Stephen Russell , H. Montgomery Manning
IPC分类号： G03F7/26
CPC分类号： H01L29/06 , H01L21/0338 , H01L21/3088
摘要： Pitch multiplied and non-pitch multiplied features of an integrated circuit, e.g., features in the array, interface and periphery areas of the integrated circuit, are formed by processing a substrate through a mask. The mask is formed by patterning a photoresist layer which simultaneously defines mask elements corresponding to features in the array, interface and periphery areas of the integrated circuit. The pattern is transferred to an amorphous carbon layer. Sidewall spacers are formed on the sidewalls of the patterned amorphous carbon layer. A layer of protective material is deposited and then patterned to expose mask elements in the array region and in selected parts of the interface or periphery areas. Amorphous carbon in the array region or other exposed parts is removed, thereby leaving a pattern including free-standing, pitch multiplied spacers in the array region. The protective material is removed, leaving a pattern of pitch multiplied spacers in the array region and non-pitch multiplied mask elements in the interface and periphery areas. The pattern is transferred to a hard mask layer, through which an underlying substrate is etched.
摘要翻译：通过通过掩模处理衬底来形成集成电路的间距倍增和非间距倍数特征，例如集成电路的阵列，接口和外围区域中的特征。通过图案化光刻胶层来形成掩模，该光致抗蚀剂层同时限定对应于集成电路的阵列，界面和外围区域中的特征的掩模元件。将图案转移到无定形碳层。侧壁间隔物形成在图案化无定形碳层的侧壁上。沉积一层保护材料，然后将其图案化以暴露阵列区域中的掩模元件和界面或外围区域的选定部分。除去阵列区域或其它暴露部分中的无定形碳，从而在阵列区域中留下包括独立的，间距倍增的间隔物的图案。去除保护材料，在阵列区域中留下间距倍数间隔物的图案，并在界面和外围区域留下非间距倍增的掩模元件。将图案转移到硬掩模层，通过该硬掩模层蚀刻下面的基底。

97. 发明申请

US20110106808A1 MULTI-DIMENSIONAL CONTENT ORGANIZATION AND DELIVERY 审中-公开
标题翻译：多维内容组织和交付
公开(公告)号：US20110106808A1
公开(公告)日：2011-05-05
申请号：US12857364
申请日：2010-08-16
申请人： Alexandre Hersans , Mark Fischer , Orjan Kjellberg , Oliver Pin , Sonali Agrawal , Walter Macklem
发明人： Alexandre Hersans , Mark Fischer , Orjan Kjellberg , Oliver Pin , Sonali Agrawal , Walter Macklem
IPC分类号： G06F17/30
CPC分类号： G06F16/2264 , G06F16/283 , G06F16/90328
摘要： The present disclosure provides novel systems and methods for providing multi-dimensional categorization within a multi-tenant database system (“MTS”). Data items in entities stored in a MTS may be categorized along one or more category dimensions. A search query may include one or more selected categories in one or more category dimensions. Categorization methodologies include multi-selection, multi-position, and combinations thereof. Users of the MTS may also be categorized along one or more category dimensions. A filter may present a subset of data items relevant to a user in accordance with their categorization.
摘要翻译：本公开提供了用于在多租户数据库系统（“MTS”）内提供多维分类的新型系统和方法。存储在MTS中的实体中的数据项可以沿着一个或多个类别维分类。搜索查询可以包括一个或多个类别维度中的一个或多个所选择的类别。分类方法包括多选择，多位置及其组合。 MTS的用户也可以按照一个或多个类别维度进行分类。过滤器可以根据其分类呈现与用户相关的数据项的子集。

98. 发明申请

US20100304560A1 SEMICONDUCTOR PROCESSING METHODS 有权
标题翻译：半导体处理方法
公开(公告)号：US20100304560A1
公开(公告)日：2010-12-02
申请号：US12855585
申请日：2010-08-12
申请人： Mark Fischer , Terrence B. McDaniel
发明人： Mark Fischer , Terrence B. McDaniel
IPC分类号： H01L21/768
CPC分类号： H01L23/5225 , H01L27/0207 , H01L27/105 , H01L27/10897 , H01L2924/0002 , H01L2924/00
摘要： The invention includes methods of forming electrically conductive material between line constructions associated with a peripheral region or a pitch region of a semiconductor substrate. The electrically conductive material can be incorporated into an electrically-grounded shield, and/or can be configured to create a magnetic field bias. Also, the conductive material can have electrically isolated segments that are utilized as electrical jumpers for connecting circuit elements. The invention also includes semiconductor constructions comprising the electrically conductive material between line constructions associated with one or both of the pitch region and the peripheral region.
摘要翻译：本发明包括在与半导体衬底的外围区域或间距区域相关联的线路构造之间形成导电材料的方法。导电材料可以结合到电接地屏蔽中，和/或可以被配置成产生磁场偏置。此外，导电材料可以具有用作连接电路元件的电跳线的电隔离段。本发明还包括在与线圈结构相关联的线路结构之间包括导电材料的半导体结构，其与音调区域和外围区域中的一个或两个相关联。

99. 发明授权

US07678648B2 Subresolution silicon features and methods for forming the same 有权
标题翻译：分解硅特征及其形成方法
公开(公告)号：US07678648B2
公开(公告)日：2010-03-16
申请号：US11486800
申请日：2006-07-14
申请人： Kevin J. Torek , Mark Fischer , Robert J. Hanson
发明人： Kevin J. Torek , Mark Fischer , Robert J. Hanson
IPC分类号： H01L21/336 , H01L21/00 , H01L21/84
CPC分类号： H01L29/7851 , H01L27/10808 , H01L27/10826 , H01L27/10879 , H01L29/66795 , H01L29/7853 , H01L29/7854
摘要： Novel etch techniques are provided for shaping silicon features below the photolithographic resolution limits. FinFET devices are defined by recessing oxide and exposing a silicon protrusion to an isotropic etch, at least in the channel region. In one implementation, the protrusion is contoured by a dry isotropic etch having excellent selectivity, using a downstream microwave plasma etch.
摘要翻译：提供了新颖的蚀刻技术，用于在低于光刻分辨率极限的条件下成形硅特征。 FinFET器件通过凹陷氧化物和至少在沟道区域中将硅突起暴露于各向同性蚀刻来限定。在一个实施方案中，使用下游微波等离子体蚀刻，通过具有优异选择性的干各向同性蚀刻来形成突起。

100. 发明授权

US07666578B2 Efficient pitch multiplication process 有权
标题翻译：高效的音调乘法过程
公开(公告)号：US07666578B2
公开(公告)日：2010-02-23
申请号：US11521851
申请日：2006-09-14
申请人： Mark Fischer , Stephen Russell , H. Montgomery Manning
发明人： Mark Fischer , Stephen Russell , H. Montgomery Manning
IPC分类号： G03F7/26 , G03F7/00
CPC分类号： H01L29/06 , H01L21/0338 , H01L21/3088
摘要： Pitch multiplied and non-pitch multiplied features of an integrated circuit, e.g., features in the array, interface and periphery areas of the integrated circuit, are formed by processing a substrate through a mask. The mask is formed by patterning a photoresist layer which simultaneously defines mask elements corresponding to features in the array, interface and periphery areas of the integrated circuit. The pattern is transferred to an amorphous carbon layer. Sidewall spacers are formed on the sidewalls of the patterned amorphous carbon layer. A layer of protective material is deposited and then patterned to expose mask elements in the array region and in selected parts of the interface or periphery areas. Amorphous carbon in the array region or other exposed parts is removed, thereby leaving a pattern including free-standing, pitch multiplied spacers in the array region. The protective material is removed, leaving a pattern of pitch multiplied spacers in the array region and non-pitch multiplied mask elements in the interface and periphery areas. The pattern is transferred to a hard mask layer, through which an underlying substrate is etched.
摘要翻译：通过通过掩模处理衬底来形成集成电路的间距倍增和非间距倍数特征，例如集成电路的阵列，接口和外围区域中的特征。通过图案化光刻胶层来形成掩模，该光致抗蚀剂层同时限定对应于集成电路的阵列，界面和外围区域中的特征的掩模元件。将图案转移到无定形碳层。侧壁间隔物形成在图案化无定形碳层的侧壁上。沉积一层保护材料，然后将其图案化以暴露阵列区域中的掩模元件和界面或外围区域的选定部分。除去阵列区域或其它暴露部分中的无定形碳，从而在阵列区域中留下包括独立的，间距倍增的间隔物的图案。去除保护材料，在阵列区域中留下间距倍数间隔物的图案，并在界面和外围区域留下非间距倍增的掩模元件。将图案转移到硬掩模层，通过该硬掩模层蚀刻下面的基底。

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