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91. 发明授权

US07396699B2 Method of forming non-volatile resistance variable devices and method of forming a programmable memory cell of memory circuitry 有权
标题翻译：形成非易失性电阻可变器件的方法和形成存储器电路的可编程存储器单元的方法
公开(公告)号：US07396699B2
公开(公告)日：2008-07-08
申请号：US11430046
申请日：2006-05-09
申请人： Kristy A. Campbell , John T. Moore
发明人： Kristy A. Campbell , John T. Moore
IPC分类号： H01L21/00
CPC分类号： H01L45/1233 , H01L45/04 , H01L45/085 , H01L45/143 , H01L45/1616 , H01L45/1658 , H01L45/1683
摘要： A first conductive electrode material is formed on a substrate. Chalcogenide comprising material is formed thereover. The chalcogenide material comprises AxSey. A silver comprising layer is formed over the chalcogenide material. The silver is irradiated effective to break a chalcogenide bond of the chalcogenide material at an interface of the silver comprising layer and chalcogenide material and diffuse at least some of the silver into the chalcogenide material. After the irradiating, the chalcogenide material outer surface is exposed to an iodine comprising fluid effective to reduce roughness of the chalcogenide material outer surface from what it was prior to the exposing. After the exposing, a second conductive electrode material is deposited over the chalcogenide material, and which is continuous and completely covering at least over the chalcogenide material, and the second conductive electrode material is formed into an electrode of the device.
摘要翻译：在基板上形成第一导电电极材料。在其上形成包含硫属元素的材料。硫族化物材料包含A x S y S y。在硫族化物材料上形成含银层。银被照射有效地破坏硫族化物材料在含银层和硫族化物材料的界面处的硫属化物键，并将至少一些银扩散到硫族化物材料中。在照射之后，硫族化物材料外表面暴露于含有碘的流体，其有效地减少硫族化物材料外表面的暴露之前的粗糙度。曝光后，将第二导电电极材料沉积在硫族化物材料上，并且至少在硫族化物材料上连续并完全覆盖，并且将第二导电电极材料形成为器件的电极。

92. 发明授权

US07382646B2 Memory architecture containing a high density memory array of semi-volatile or non-volatile memory elements 有权
标题翻译：内存架构包含高密度存储器阵列的半挥发性或非易失性存储元件
公开(公告)号：US07382646B2
公开(公告)日：2008-06-03
申请号：US11581748
申请日：2006-10-17
申请人： John T. Moore , Terry L. Gilton
发明人： John T. Moore , Terry L. Gilton
IPC分类号： G11C11/00
CPC分类号： G11C13/003 , G11C5/063 , G11C7/18 , G11C11/4097 , G11C13/0011 , G11C13/004 , G11C2213/75 , G11C2213/76 , G11C2213/79 , H01L27/0203 , H01L27/105 , H01L27/1052
摘要： An architecture, and its method of formation and operation, containing a high density memory array of semi-volatile or non-volatile memory elements, including, but not limited to, programmable conductive access memory elements. The architecture in one exemplary embodiment has a pair of semi-volatile or non-volatile memory elements which selectively share a bit line through respective first electrodes and access transistors controlled by respective word lines. The memory elements each have a respective second electrode coupled thereto which in cooperation with the bit line access transistors and first electrode, serves to apply read, write and erase signals to the memory element.
摘要翻译：一种架构及其形成和操作方法，其包含半易失性或非易失性存储器元件的高密度存储器阵列，包括但不限于可编程导电存取存储器元件。一个示例性实施例中的架构具有一对半挥发性或非易失性存储器元件，其通过相应的第一电极和由相应字线控制的存取晶体管选择性地共享位线。存储元件各自具有耦合到其上的相应的第二电极，其与位线存取晶体管和第一电极协作，用于向存储元件施加读取，写入和擦除信号。

93. 发明授权

US07348205B2 Method of forming resistance variable devices 有权
标题翻译：形成电阻变量器件的方法
公开(公告)号：US07348205B2
公开(公告)日：2008-03-25
申请号：US11085009
申请日：2005-03-21
申请人： Kristy A. Campbell , Terry L. Gilton , John T. Moore , Jiutao Li
发明人： Kristy A. Campbell , Terry L. Gilton , John T. Moore , Jiutao Li
IPC分类号： H01L21/00
CPC分类号： H01L45/085 , H01L45/1233 , H01L45/141 , H01L45/142 , H01L45/143 , H01L45/144 , H01L45/1641 , H01L45/1658 , H01L45/1683
摘要： A method of forming a resistance variable device includes forming a first conductive electrode material on a substrate. A metal doped chalcogenide comprising material is formed over the first conductive electrode material. Such comprises the metal and AxBy, where “B” is selected from S, Se and Te and mixtures thereof, and where “A” comprises at least one element which is selected from Group 13, Group 14, Group 15, or Group 17 of the periodic table. In one aspect, the chalcogenide comprising material is exposed to an HNO3 solution. In one aspect the outer surface is oxidized effective to form a layer comprising at least one of an oxide of “A” or an oxide of “B”. In one aspect, a passivating material is formed over the metal doped chalcogenide comprising material. A second conductive electrode material is deposited, and a second conductive electrode material of the device is ultimately formed therefrom.
摘要翻译：形成电阻可变器件的方法包括在衬底上形成第一导电电极材料。在第一导电电极材料上形成包含材料的掺杂金属的硫族化物。其中“B”选自S，Se和Te及其混合物，其中“A”包括至少一个元素其选自周期表的第13组，第14组，第15组或第17组。在一个方面，将包含硫属元素的材料暴露于HNO 3 N 3溶液中。在一个方面，外表面被有效地氧化以形成包含“A”的氧化物或“B”的氧化物中的至少一种的层。在一个方面，在包含金属的硫族化物的材料上形成钝化材料。沉积第二导电电极材料，并且最终由器件的第二导电电极材料形成。

94. 发明授权

US07189626B2 Electroless plating of metal caps for chalcogenide-based memory devices 失效
标题翻译：用于基于硫族化物的存储器件的金属盖的无电镀
公开(公告)号：US07189626B2
公开(公告)日：2007-03-13
申请号：US10980658
申请日：2004-11-03
申请人： Patricia C. Elkins , John T. Moore , Rita J. Klein
发明人： Patricia C. Elkins , John T. Moore , Rita J. Klein
IPC分类号： H01L21/20
CPC分类号： H01L21/288 , H01L21/76849 , H01L21/76877 , H01L45/085 , H01L45/1233 , H01L45/143 , H01L45/16
摘要： A method of forming a metal cap over a conductive interconnect in a chalcogenide-based memory device is provided and includes, forming a layer of a first conductive material over a substrate, depositing an insulating layer over the first conductive material and the substrate, forming an opening in the insulating layer to expose at least a portion of the first conductive material, depositing a second conductive material over the insulating layer and within the opening, removing portions of the second conductive material to form a conductive area within the opening, recessing the conductive area within the opening to a level below an upper surface of the insulating layer, forming a cap of a third conductive material over the recessed conductive area within the opening, the third conductive material selected from the group consisting of cobalt, silver, gold, copper, nickel, palladium, platinum, and alloys thereof, depositing a stack of a chalcogenide based memory cell material over the cap, and depositing a conductive material over the chalcogenide stack.
摘要翻译：提供了一种在基于硫族化物的存储器件中在导电互连上形成金属帽的方法，包括：在衬底上形成第一导电材料层，在第一导电材料和衬底上沉积绝缘层，形成在所述绝缘层中开口以露出所述第一导电材料的至少一部分，在所述绝缘层上并在所述开口内沉积第二导电材料，去除所述第二导电材料的部分以在所述开口内形成导电区域，使所述导电在所述开口内的所述绝缘层的上表面以下的层，在所述开口内的所述凹陷导电区域上形成第三导电材料的盖，所述第三导电材料选自钴，银，金，铜，镍，钯，铂及其合金，在高温下沉积基于硫族化物的记忆电池材料的堆叠 p，并在硫族化物堆叠上沉积导电材料。

95. 发明授权

US07115992B2 Electrode structure for use in an integrated circuit 有权
公开(公告)号：US07115992B2
公开(公告)日：2006-10-03
申请号：US10873231
申请日：2004-06-23
申请人： John T. Moore , Joseph F. Brooks
发明人： John T. Moore , Joseph F. Brooks
IPC分类号： H01L23/48
CPC分类号： H01L24/05 , G11C13/0011 , G11C2213/79 , H01L21/76823 , H01L21/76838 , H01L21/76867 , H01L24/03 , H01L45/085 , H01L45/124 , H01L45/143 , H01L45/1658 , H01L45/1683 , H01L2224/05006 , H01L2224/05546 , H01L2924/01005 , H01L2924/01006 , H01L2924/01007 , H01L2924/01014 , H01L2924/01015 , H01L2924/01018 , H01L2924/01028 , H01L2924/01032 , H01L2924/01033 , H01L2924/01047 , H01L2924/01057 , H01L2924/01074 , H01L2924/01082 , H01L2924/05042 , H01L2924/13091 , H01L2924/14 , H01L2924/19043 , H01L2924/3011 , Y10S438/957 , H01L2924/00
摘要： An electrode structure includes a first layer of conductive material and a dielectric layer formed on a surface of the first layer. An opening is formed in the dielectric layer to expose a portion of the surface of the first layer. A binding layer is formed on the dielectric layer and on the exposed portion of the surface of the first layer and a second layer of conductive material is formed on the conductive binding layer. The binding layer can be an oxide and the second layer a conductive material that is diffusible into an oxide. The electrode structure can be annealed to cause conductive material from the second layer to be chemisorbed into the binding layer to improve adhesion between the first and second layers. A programmable cell can be formed by forming a doped glass layer in the electrode structure.

96. 发明授权

US07087454B2 Fabrication of single polarity programmable resistance structure 有权
标题翻译：制造单极性可编程电阻结构
公开(公告)号：US07087454B2
公开(公告)日：2006-08-08
申请号：US10800707
申请日：2004-03-16
申请人： Kristy A. Campbell , John T. Moore , Terry L. Gilton
发明人： Kristy A. Campbell , John T. Moore , Terry L. Gilton
IPC分类号： H01L21/06
CPC分类号： G11C13/0004 , G11C13/0011 , G11C13/0069 , G11C2013/009 , G11C2213/55 , H01L45/085 , H01L45/1233 , H01L45/1266 , H01L45/143 , H01L45/1616 , H01L45/1625
摘要： A resistance variable memory element with improved data retention and switching characteristics switched between resistance memory states upon the application of write pulses having the same polarity. The resistance variable memory element can be provided having at least one silver-selenide layer in between glass layers, the glass layers are a chalcogenide glass having a GexSe100−x composition.
摘要翻译：具有改进的数据保持和开关特性的电阻可变存储元件在施加具有相同极性的写入脉冲时在电阻存储器状态之间切换。可以提供电阻可变存储元件，其在玻璃层之间具有至少一个银硒化物层，玻璃层是具有Ge x Sb 1 O x 100 x x 组成。

97. 发明授权

US07030410B2 Resistance variable device 失效
标题翻译：电阻可变装置
公开(公告)号：US07030410B2
公开(公告)日：2006-04-18
申请号：US10920333
申请日：2004-08-18
申请人： John T. Moore
发明人： John T. Moore
IPC分类号： H01L29/04
CPC分类号： H01L45/1658 , H01C17/075 , H01C17/288 , H01L27/24 , H01L29/685 , H01L45/085 , H01L45/1233 , H01L45/1253 , H01L45/142 , H01L45/143 , H01L45/144 , H01L45/1625 , H01L45/1675 , Y10S438/942 , Y10S438/953
摘要： A method of precluding diffusion of a metal into adjacent chalcogenide material upon exposure to a quanta of actinic energy capable of causing diffusion of the metal into the chalcogenide material includes forming an actinic energy blocking material layer over the metal to a thickness of no greater than 500 Angstroms and subsequently exposing the actinic energy blocking material layer to said quanta of actinic energy. In one implementation, an homogenous actinic energy blocking material layer is formed over the metal and subsequently exposed to said quanta of actinic energy. A method of forming a non-volatile resistance variable device includes providing conductive electrode material over chalcogenide material having metal ions diffused therein. An actinic energy blocking material layer is formed on the conductive electrode material, the actinic energy blocking material layer being effective to shield actinic energy from reaching an interface of the conductive electrode material and the actinic energy blocking material to substantially preclude diffusion of the conductive electrode material into the chalcogenide material upon exposure to said actinic energy. A dielectric layer is formed on the actinic energy blocking material layer. The conductive electrode material is formed into a first electrode. A second electrode is provided proximate the chalcogenide material having the metal diffused therein. Non-volatile resistance variable devices manufacture by these and other methods are contemplated.
摘要翻译：在暴露于能够使金属扩散到硫族化物材料中的光化能的量子时，排除金属扩散到相邻硫族化物材料中的方法包括在金属上形成光化能量阻挡材料层至厚度不大于500 然后将光化性能量阻挡材料层暴露于所述光化能量级。在一个实施方案中，在金属上形成均匀的光化能阻挡材料层，随后暴露于所述光化能量级。形成非易失性电阻可变器件的方法包括在其中扩散金属离子的硫族化物材料上提供导电电极材料。在导电电极材料上形成光化学能量阻挡材料层，光化学能量阻挡材料层有效地屏蔽光化能到达导电电极材料和光化能阻挡材料的界面，从而基本排除导电电极材料的扩散在暴露于所述光化能之后进入硫族化物材料。在光化能阻挡材料层上形成介电层。导电电极材料形成为第一电极。靠近硫属化物材料设置第二电极，其中金属在其中扩散。考虑通过这些和其他方法制造的非易失性电阻可变器件。

98. 发明授权

US06861367B2 Semiconductor processing method using photoresist and an antireflective coating 失效
标题翻译：使用光致抗蚀剂和抗反射涂层的半导体加工方法
公开(公告)号：US06861367B2
公开(公告)日：2005-03-01
申请号：US10719640
申请日：2003-11-21
申请人： Terry L. Gilton , Steve W. Bowes , John T. Moore , Joseph F. Brooks , Kristy A. Campbell
发明人： Terry L. Gilton , Steve W. Bowes , John T. Moore , Joseph F. Brooks , Kristy A. Campbell
IPC分类号： G03F7/09 , H01L21/027 , H01L21/308 , H01L21/768 , H01L21/4763
CPC分类号： G03F7/091 , H01L21/0276 , H01L21/3081 , H01L21/76802 , Y10S438/952
摘要： A semiconductor processing method includes forming an antireflective coating comprising Ge and Se over a substrate to be patterned. Photoresist is formed over the antireflective coating. The photoresist is exposed to actinic radiation effective to pattern the photoresist. The antireflective coating reduces reflection of actinic radiation during the exposing than would otherwise occur under identical conditions in the absence of the antireflective coating. After the exposing, the substrate is patterned through openings in the photoresist and the antireflective coating using the photoresist and the antireflective coating as a mask. In one implementation, after patterning the substrate, the photoresist and the antireflective coating are chemically etched substantially completely from the substrate using a single etching chemistry.
摘要翻译：半导体处理方法包括在待图案化的基板上形成包含Ge和Se的抗反射涂层。在抗反射涂层上形成光致抗蚀剂。光致抗蚀剂暴露于光化辐射，有效地对光致抗蚀剂进行图案化。抗反射涂层减少曝光期间光化辐射的反射，否则在不存在抗反射涂层的同一条件下会发生。曝光后，使用光致抗蚀剂和抗反射涂层作为掩模，将光刻胶和防反射涂层中的开口图案化基板。在一个实施方案中，在图案化基板之后，使用单一蚀刻化学法，使基板完全从基板上完全蚀刻光致抗蚀剂和抗反射涂层。

99. 发明授权

US06856002B2 Graded GexSe100-x concentration in PCRAM 有权
公开(公告)号：US06856002B2
公开(公告)日：2005-02-15
申请号：US10230327
申请日：2002-08-29
申请人： John T. Moore , Terry L. Gilton , Kristy A. Campbell
发明人： John T. Moore , Terry L. Gilton , Kristy A. Campbell
IPC分类号： H01L21/8234 , H01L27/24 , H01L45/00 , H01L29/00
CPC分类号： H01L45/1683 , H01L45/085 , H01L45/1233 , H01L45/143 , H01L45/1658
摘要： The present invention provides a design for a PCRAM element which incorporates multiple metal-containing germanium-selenide glass layers of diverse stoichiometries. The present invention also provides a method of fabricating the disclosed PCRAM structure.

100. 发明授权

US06833329B1 Methods of forming oxide regions over semiconductor substrates 有权
标题翻译：在半导体衬底上形成氧化物区域的方法
公开(公告)号：US06833329B1
公开(公告)日：2004-12-21
申请号：US09602395
申请日：2000-06-22
申请人： John T. Moore
发明人： John T. Moore
IPC分类号： H01L2131
CPC分类号： H01L21/823462 , H01L21/3145 , H01L21/31612
摘要： The invention encompasses a method of forming an oxide region over a semiconductor substrate. A nitrogen-containing layer is formed across at least some of the substrate. After the nitrogen-containing layer is formed, an oxide region is grown from at least some of the substrate. The nitrogen of the nitrogen-containing layer is dispersed within the oxide region. The invention also encompasses a method of forming a pair of transistors associated with a semiconductor substrate. A substrate is provided. A first region of the substrate is defined, and additionally a second region of the substrate is defined. A first oxide region is formed which covers at least some of the first region of the substrate, and which does not cover any of the second region of the substrate. A nitrogen-comprising layer is formed across at least some of the first oxide region and across at least some of the second region of the substrate. After the nitrogen-comprising layer is formed, a second oxide region is grown from the second region of the substrate. A first transistor gate is formed over the first oxide region, and a second transistor gate is formed over the second oxide region.
摘要翻译：本发明包括在半导体衬底上形成氧化物区域的方法。在至少一些基底上形成含氮层。在形成含氮层之后，从衬底中的至少一些生长氧化物区域。含氮层的氮分散在氧化物区域内。本发明还包括形成与半导体衬底相关联的一对晶体管的方法。提供基板。限定衬底的第一区域，并且另外定义衬底的第二区域。形成第一氧化物区域，其覆盖衬底的第一区域中的至少一些，并且不覆盖衬底的任何第二区域。跨越第一氧化物区域中的至少一些并穿过衬底的至少一些第二区域形成含氮层。在形成含氮层之后，从衬底的第二区域生长第二氧化物区域。在第一氧化物区域上形成第一晶体管栅极，在第二氧化物区域上形成第二晶体管栅极。

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