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91. 发明授权

US08053374B2 Method of manufacturing a metal wiring structure 有权
标题翻译：制造金属布线结构的方法
公开(公告)号：US08053374B2
公开(公告)日：2011-11-08
申请号：US12506361
申请日：2009-07-21
申请人： Kyung-In Choi , Hyeon-Deok Lee , Gil-Heyun Choi , Jong-Myeong Lee
发明人： Kyung-In Choi , Hyeon-Deok Lee , Gil-Heyun Choi , Jong-Myeong Lee
IPC分类号： H01L21/31 , H01L21/469 , H01L21/4763
CPC分类号： H01L21/76814 , H01L21/76843 , H01L21/76852 , H01L21/76856 , H01L27/11526 , H01L27/11543 , H01L27/11546 , H01L27/11548
摘要： In a method of manufacturing a metal wiring structure, a first metal wiring and a first barrier layer are formed on a substrate, and the first barrier layer is nitridated. An insulating interlayer is formed on the substrate so as to extend over the first metal wiring and the first barrier layer. Part of the insulating interlayer is removed to form a hole exposing at least part of the first metal wiring and part of the first barrier layer. A nitidation plasma treatment is performed on the exposed portion of the first barrier layer. A second barrier layer is formed along the bottom and sides of the hole. A plug is formed on the second barrier layer to fill the hole.
摘要翻译：在制造金属布线结构的方法中，在基板上形成第一金属布线和第一阻挡层，并且对第一阻挡层进行氮化。绝缘中间层形成在基板上，以便延伸越过第一金属布线和第一阻挡层。去除部分绝缘中间层以形成露出第一金属布线和第一阻挡层的一部分的至少一部分的孔。对第一阻挡层的暴露部分进行硝化等离子体处理。沿着孔的底部和侧面形成第二阻挡层。在第二阻挡层上形成插塞以填充孔。

92. 发明申请

US20110136332A1 METHODS OF FORMING INTEGRATED CIRCUIT DEVICES WITH CRACK-RESISTANT FUSE STRUCTURES 有权
标题翻译：形成集成电路设备的方法，具有抗电弧保险丝结构
公开(公告)号：US20110136332A1
公开(公告)日：2011-06-09
申请号：US12960150
申请日：2010-12-03
申请人： Sang-Hoon Ahn , Gil-Heyun Choi , Jong-Myeong Lee , Sang-Don Nam , Kyu-Hee Han
发明人： Sang-Hoon Ahn , Gil-Heyun Choi , Jong-Myeong Lee , Sang-Don Nam , Kyu-Hee Han
IPC分类号： H01L21/28 , H01L21/31
CPC分类号： H01L23/5258 , H01L2924/0002 , H01L2924/00
摘要： A fuse base insulating region, for example, an insulating interlayer or a compensation region disposed in an insulating interlayer, is formed on a substrate. An etch stop layer is formed on the fuse base insulating region and forming an insulating interlayer having a lower dielectric constant than the first fuse base insulating region on the etch stop layer. A trench extending through the insulating interlayer and the etch stop layer and at least partially into the fuse base insulating region is formed. A fuse is formed in the trench. The fuse base insulating region may have a greater mechanical strength and/or density than the second insulating interlayer.
摘要翻译：在衬底上形成熔丝基底绝缘区域，例如绝缘中间层或设置在绝缘中间层中的补偿区域。在熔丝基底绝缘区上形成蚀刻停止层，形成绝缘中间层，该绝缘中间层的介电常数比蚀刻停止层上的第一熔丝基底绝缘区低。形成了延伸穿过绝缘中间层和蚀刻停止层并且至少部分地进入熔丝基底绝缘区域的沟槽。在沟槽中形成熔丝。保险丝座绝缘区域可具有比第二绝缘中间层更大的机械强度和/或密度。

93. 发明申请

US20110092060A1 METHODS OF FORMING WIRING STRUCTURES 有权
标题翻译：形成接线结构的方法
公开(公告)号：US20110092060A1
公开(公告)日：2011-04-21
申请号：US12836081
申请日：2010-07-14
申请人： Eun-Ok Lee , Dae-Yong Kim , Gil-Heyun Choi , Byung-Hee Kim
发明人： Eun-Ok Lee , Dae-Yong Kim , Gil-Heyun Choi , Byung-Hee Kim
IPC分类号： H01L21/768 , H01L21/28
CPC分类号： H01L29/66621 , H01L21/76831 , H01L21/76885 , H01L21/76889 , H01L21/76897 , H01L27/10814 , H01L27/10855 , H01L27/10885 , H01L27/10888 , H01L27/10894 , H01L29/4236 , H01L29/665 , H01L29/78
摘要： A semiconductor memory wiring method includes: receiving a substrate having a cell array region and a peripheral circuit region; depositing a first insulating layer on the substrate; forming a first contact plug in the cell array region, the first contact plug having a first conductive material extending through the first insulating layer; forming a first elongated conductive line at substantially the same time as forming the first contact plug, the first elongated conductive line having the first conductive material directly covering and integrated with the first contact plug; forming a second contact plug in the peripheral circuit region at substantially the same time as forming the first contact plug, the second contact plug having the first conductive material extending through the first insulating layer; and forming a second elongated conductive line at substantially the same time as forming the second contact plug, the second elongated conductive line having the first conductive material directly covering and integrated with the second contact plug.
摘要翻译：一种半导体存储器布线方法，包括：接收具有单元阵列区域和外围电路区域的基板; 在衬底上沉积第一绝缘层; 在所述电池阵列区域中形成第一接触插塞，所述第一接触插塞具有延伸穿过所述第一绝缘层的第一导电材料; 在形成第一接触插塞的基本上同时形成第一细长导线，所述第一细长导线具有直接覆盖并与第一接触插塞一体化的第一导电材料; 在形成第一接触插塞的基本上相同的时间在外围电路区域中形成第二接触插塞，第二接触插塞具有延伸穿过第一绝缘层的第一导电材料; 并且在与形成所述第二接触插塞的基本同时形成第二细长导电线，所述第二细长导电线具有直接覆盖并与所述第二接触插塞一体化的所述第一导电材料。

94. 发明授权

US07928498B2 Gate structures in semiconductor devices 有权
标题翻译：半导体器件中的栅极结构
公开(公告)号：US07928498B2
公开(公告)日：2011-04-19
申请号：US12428303
申请日：2009-04-22
申请人： Tae-Ho Cha , Seong-Hwee Cheong , Gil-Heyun Choi , Byung-Hee Kim , Hee-Sook Park , Jong-Min Baek
发明人： Tae-Ho Cha , Seong-Hwee Cheong , Gil-Heyun Choi , Byung-Hee Kim , Hee-Sook Park , Jong-Min Baek
IPC分类号： H01L29/788
CPC分类号： H01L29/42324 , H01L21/28273 , H01L21/28282 , H01L27/10873 , H01L29/4941 , H01L29/517
摘要： A gate structure includes an insulation layer on a substrate, a first conductive layer pattern on the insulation layer, a metal ohmic layer pattern on the first conductive layer pattern, a diffusion preventing layer pattern on the metal ohmic layer pattern, an amorphous layer pattern on the diffusion preventing layer pattern, and a second conductive layer pattern on the amorphous layer pattern. The gate structure may have a low sheet resistance and desired thermal stability.
摘要翻译：栅极结构包括在衬底上的绝缘层，绝缘层上的第一导电层图案，第一导电层图案上的金属欧姆层图案，金属欧姆层图案上的扩散防止层图案，扩散防止层图案和非晶层图案上的第二导电层图案。栅极结构可以具有低的薄层电阻和期望的热稳定性。

95. 发明授权

US07879737B2 Methods for fabricating improved gate dielectrics 有权
标题翻译：制造改进的栅极电介质的方法
公开(公告)号：US07879737B2
公开(公告)日：2011-02-01
申请号：US12801115
申请日：2010-05-24
申请人： Woong-Hee Sohn , Gil-Heyun Choi , Byung-Hee Kim , Byung-Hak Lee , Tae-Ho Cha , Hee-Sook Park , Jae-Hwa Park , Geum-Jung Seong
发明人： Woong-Hee Sohn , Gil-Heyun Choi , Byung-Hee Kim , Byung-Hak Lee , Tae-Ho Cha , Hee-Sook Park , Jae-Hwa Park , Geum-Jung Seong
IPC分类号： H01L21/31
CPC分类号： H01L21/823481 , H01L21/28202 , H01L21/28211 , H01L21/2822 , H01L29/518 , H01L29/66545 , H01L29/78 , Y10S438/981
摘要： Disclosed are a variety of methods for increasing the relative thickness in the peripheral or edge regions of gate dielectric patterns to suppress leakage through these regions. The methods provide alternatives to conventional GPOX processes and provide the improved leakage resistance without incurring the degree of increased gate electrode resistance associated with GPOX processes. Each of the methods includes forming a first opening to expose an active area region, forming an oxidation control region on the exposed portion and then forming a second opening whereby a peripheral region free of the oxidation control region is exposed for formation of a gate dielectric layer. The resulting gate dielectric layers are characterized by a thinner central region surrounded or bounded by a thicker peripheral region.
摘要翻译：公开了用于增加栅极电介质图案的外围或边缘区域中的相对厚度以抑制这些区域的泄漏的各种方法。这些方法提供了常规GPOX工艺的替代方案，并提供改进的耐漏电性，而不会导致与GPOX工艺相关的增加的栅电极电阻的程度。每种方法包括形成第一开口以暴露有源区域区域，在暴露部分上形成氧化控制区域，然后形成第二开口，由此暴露氧化控制区域的外围区域以形成栅极介电层。得到的栅极介电层的特征在于由较厚的外围区域包围或界定的较薄的中心区域。

96. 发明申请

US20090239368A1 Methods of Forming an Oxide Layer and Methods of Forming a Gate Using the Same 审中-公开
标题翻译：形成氧化物层的方法和使用其形成浇口的方法
公开(公告)号：US20090239368A1
公开(公告)日：2009-09-24
申请号：US12408994
申请日：2009-03-23
申请人： Jae Hwa Park , Gil-Heyun Choi , Hee-Sook Park , Jong-Min Baek
发明人： Jae Hwa Park , Gil-Heyun Choi , Hee-Sook Park , Jong-Min Baek
IPC分类号： H01L21/336 , H01L21/469 , H01L21/314
CPC分类号： H01L21/28185 , H01L21/02164 , H01L21/02238 , H01L21/02252 , H01L21/28247 , H01L21/31654 , H01L21/32105 , H01L29/40114 , H01L29/6659 , H01L29/7833
摘要： An oxide layer is selectively formed on a layer including silicon by a plasma process using hydrogen gas and a gas including oxygen. The hydrogen gas is controlled to have a flow rate less than about 50 percent of an overall flow rate by adding helium gas to the plasma process.
摘要翻译：通过使用氢气和包括氧的气体的等离子体工艺在包括硅的层上选择性地形成氧化物层。通过向等离子体工艺中加入氦气，氢气被控制为具有小于总流量的约50％的流量。

97. 发明授权

US07585787B2 Semiconductor memory device and method of manufacturing the same 有权
标题翻译：半导体存储器件及其制造方法
公开(公告)号：US07585787B2
公开(公告)日：2009-09-08
申请号：US11648595
申请日：2007-01-03
申请人： Tae-Ho Cha , Gil-Heyun Choi , Byung-Hee Kim , Hee-Sook Park , Jang-Hee Lee , Geum-Jung Seong
发明人： Tae-Ho Cha , Gil-Heyun Choi , Byung-Hee Kim , Hee-Sook Park , Jang-Hee Lee , Geum-Jung Seong
IPC分类号： H01L21/469
CPC分类号： H01L29/4941 , H01L27/105 , H01L27/115 , H01L27/11521 , H01L27/11526 , H01L27/11536 , H01L27/11568 , H01L29/513
摘要： A semiconductor memory device, e.g., a charge trapping type non-volatile memory device, may include a charge trapping structure formed in a first area of a substrate and a gate structure formed in a second area of the substrate. The charge trapping structure may include a tunnel oxide layer pattern, a charge trapping layer pattern and a dielectric layer pattern of aluminum-containing tertiary metal oxide. The gate structure may include a gate oxide layer pattern, a polysilicon layer pattern and an ohmic layer pattern of aluminum-containing tertiary metal silicide. A first electrode and a second electrode may be formed on the charge trapping structure. A lower electrode and an upper electrode may be provided on the gate structure. The dielectric layer pattern may have a higher dielectric constant, and the ohmic layer pattern may have improved thermal stability, thereby enhancing programming and erasing operations of the charge trapping type non-volatile memory device.
摘要翻译：半导体存储器件，例如电荷俘获型非易失性存储器件，可以包括形成在衬底的第一区域中的电荷俘获结构和形成在衬底的第二区域中的栅极结构。电荷捕获结构可以包括隧道氧化物层图案，电荷俘获层图案和含铝三级金属氧化物的介电层图案。栅极结构可以包括栅极氧化物层图案，多晶硅层图案和含铝三次金属硅化物的欧姆层图案。第一电极和第二电极可以形成在电荷捕获结构上。可以在栅极结构上设置下电极和上电极。电介质层图案可以具有更高的介电常数，并且欧姆层图案可以具有改善的热稳定性，从而增强电荷俘获型非易失性存储器件的编程和擦除操作。

98. 发明申请

US20090166868A1 Semiconductor devices including metal interconnections and methods of fabricating the same 审中-公开
标题翻译：包括金属互连的半导体器件及其制造方法
公开(公告)号：US20090166868A1
公开(公告)日：2009-07-02
申请号：US12011750
申请日：2008-01-29
申请人： Jong-Myeong Lee , Gil-Heyun Choi , Jong-Won Hong , Hyun Park , Kyung-In Choi , Hyun-Bae Lee
发明人： Jong-Myeong Lee , Gil-Heyun Choi , Jong-Won Hong , Hyun Park , Kyung-In Choi , Hyun-Bae Lee
IPC分类号： H01L23/52 , H01L21/4763
CPC分类号： H01L21/76849 , H01L21/7684 , H01L21/76867 , H01L21/76897 , H01L23/5226 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device includes a first interlayer dielectric including a trench on a semiconductor layer, a mask pattern on the first interlayer dielectric, a first conductive pattern in the trench, and a second interlayer dielectric on the mask pattern. The second interlayer dielectric includes an opening over the first conductive pattern. A second conductive pattern is in the opening and is electrically connected to the first conductive pattern. The first conductive pattern has an upper surface lower than an upper surface of the mask pattern.
摘要翻译：半导体器件包括在半导体层上包括沟槽的第一层间电介质，第一层间电介质上的掩模图案，沟槽中的第一导电图案和掩模图案上的第二层间电介质。第二层间电介质包括在第一导电图案上的开口。第二导电图案在开口中并且电连接到第一导电图案。第一导电图案具有比掩模图案的上表面低的上表面。

99. 发明授权

US07547632B2 Methods of forming metal layers in the fabrication of semiconductor devices 有权
标题翻译：在制造半导体器件时形成金属层的方法
公开(公告)号：US07547632B2
公开(公告)日：2009-06-16
申请号：US11675158
申请日：2007-02-15
申请人： Jung-Hun Seo , Gil-Heyun Choi , Jong-Myeong Lee , Hee-Sook Park
发明人： Jung-Hun Seo , Gil-Heyun Choi , Jong-Myeong Lee , Hee-Sook Park
IPC分类号： H01L21/44
CPC分类号： C23C16/4408 , C23C16/54 , H01L21/76838 , H01L21/76841 , H01L21/76861
摘要： A metal deposition processing apparatus includes a first processing chamber configured for holding a semiconductor substrate therein. A second processing chamber is configured for holding the semiconductor substrate therein and for forming an upper metal layer thereon. A transfer chamber is connected to the first processing chamber and the second processing chamber. The transfer chamber is configured to transfer the semiconductor substrate between the first processing chamber and the second processing chamber.
摘要翻译：金属沉积处理装置包括：第一处理室，被构造成用于将半导体基板保持在其中。第二处理室构造成用于将半导体衬底保持在其中并用于在其上形成上金属层。传送室连接到第一处理室和第二处理室。传送室配置成在第一处理室和第二处理室之间传送半导体衬底。

100. 发明授权

US07534709B2 Semiconductor device and method of manufacturing the same 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US07534709B2
公开(公告)日：2009-05-19
申请号：US11233580
申请日：2005-09-23
申请人： Jae-Hwa Park , Gil-Heyun Choi , Chang-Won Lee , Byung-Hak Lee , Hee-Sook Park , Woong-Hee Sohn , Jong-Ryeol Yoo , Sun-Pil Yun , Jang-Hee Lee , Dong-Chan Lim
发明人： Jae-Hwa Park , Gil-Heyun Choi , Chang-Won Lee , Byung-Hak Lee , Hee-Sook Park , Woong-Hee Sohn , Jong-Ryeol Yoo , Sun-Pil Yun , Jang-Hee Lee , Dong-Chan Lim
IPC分类号： H01L21/3205
CPC分类号： H01L21/76841 , H01L21/28061 , H01L21/76843 , H01L21/76846 , H01L21/76855 , H01L29/4933 , H01L29/4941
摘要： Embodiments of the present invention include semiconductor devices that can be made with relatively low resistance, and methods of forming the semiconductor devices. A resistance reducing layer is formed between a polysilicon layer and a metal layer. As a result, an interface resistance between the polysilicon layer and the metal layer is greatly reduced and a distribution of the interface resistance is very uniform. As a result, a conductive structure including the resistance reducing layer has a greatly reduced sheet resistance to improve electrical characteristics of a semiconductor device having the conductive structure.
摘要翻译：本发明的实施例包括可以制造成具有较低电阻的半导体器件，以及形成半导体器件的方法。在多晶硅层和金属层之间形成电阻降低层。结果，多晶硅层和金属层之间的界面电阻大大降低，并且界面电阻的分布非常均匀。结果，包括电阻降低层的导电结构具有大大降低的薄层电阻以改善具有导电结构的半导体器件的电特性。

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