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91. 发明授权

US08913445B2 Method and apparatus for adjusting drain bias of a memory cell with addressed and neighbor bits 有权
标题翻译：用于调整具有寻址和相邻位的存储单元的漏极偏置的方法和装置
公开(公告)号：US08913445B2
公开(公告)日：2014-12-16
申请号：US13372135
申请日：2012-02-13
申请人： Han-Sung Chen , Chung-Kuang Chen , Chun-Hsiung Hung
发明人： Han-Sung Chen , Chung-Kuang Chen , Chun-Hsiung Hung
IPC分类号： G11C7/00 , G11C7/22
CPC分类号： G11C7/00 , G11C11/5628 , G11C11/5642 , G11C11/5671 , G11C2211/5621
摘要： The storage layer such as a nitride layer of a nonvolatile memory cell has two storage parts storing separately addressable data, typically respectively proximate to the source terminal and the drain terminal. The applied drain voltage while sensing the data of one of the storage parts depends on the data stored at the other storage part. If the data stored at the other storage part is represented by a threshold voltage exceeding a minimum threshold voltage, then the applied drain voltage is raised. This technology is useful in read operations and program verify operations to widen the threshold voltage window.
摘要翻译：诸如非易失性存储单元的氮化物层的存储层具有存储单独可寻址数据的两个存储部分，通常分别靠近源极端子和漏极端子。在感测一个存储部件的数据时所施加的漏极电压取决于存储在另一个存储部分的数据。如果存储在另一个存储部分的数据由超过最小阈值电压的阈值电压表示，则所施加的漏极电压升高。该技术在读取操作和程序验证操作中有助于拓宽阈值电压窗口。

92. 发明授权

US08743641B2 Memory with temperature compensation 有权
标题翻译：带温度补偿的内存
公开(公告)号：US08743641B2
公开(公告)日：2014-06-03
申请号：US13227249
申请日：2011-09-07
申请人： Chung-Kuang Chen , Han-Sung Chen , Chun-Hsiung Hung
发明人： Chung-Kuang Chen , Han-Sung Chen , Chun-Hsiung Hung
IPC分类号： G11C7/04
CPC分类号： G11C7/04 , G11C7/14 , G11C11/5642 , G11C2211/5634
摘要： A memory element in which the temperature coefficient of a memory cell substantially matches the temperature coefficient of a reference cell and tuning either the temperature coefficient of a memory cell to substantially match the temperature coefficient of the reference cell provides for improved precision of sensing or reading memory element states, particularly so as to minimize the affect of temperature variations on reading and sensing states.
摘要翻译：一种存储元件，其中存储单元的温度系数基本上与参考单元的温度系数相匹配，并且调节存储单元的温度系数以与参考单元的温度系数基本一致，提供了读取或读取存储器的精度提高特别是为了最小化温度变化对读取和感测状态的影响。

93. 发明授权

US08589716B2 Clock integrated circuit 有权
标题翻译：时钟集成电路
公开(公告)号：US08589716B2
公开(公告)日：2013-11-19
申请号：US13596953
申请日：2012-08-28
申请人： Chung-Kuang Chen , Chun-Hsiung Hung , Han-Sung Chen
发明人： Chung-Kuang Chen , Chun-Hsiung Hung , Han-Sung Chen
IPC分类号： G06F1/12 , G06F1/00 , G06F1/04 , G05F3/02 , G05F3/16
CPC分类号： H03K19/018528 , G05F3/02 , G06F1/04 , G06F1/08 , G06F1/10 , G06F1/12 , H03K19/0175 , H03L5/00
摘要： The clock circuit of an integrated circuit operates with variations such as temperature, ground noise, and power noise. Various aspects of an improved clock integrated circuit address one or more of the variations in temperature, ground noise, and power noise.
摘要翻译：集成电路的时钟电路具有诸如温度，接地噪声和功率噪声的变化。改进的时钟集成电路的各个方面解决了温度，地面噪声和功率噪声中的一个或多个变化。

94. 发明申请

US20130208544A1 FLASH MEMORY WITH READ TRACKING CLOCK AND METHOD THEREOF 有权
标题翻译：具有读跟踪时钟的闪存及其方法
公开(公告)号：US20130208544A1
公开(公告)日：2013-08-15
申请号：US13370833
申请日：2012-02-10
申请人： Chung-Kuang Chen , Han-Sung Chen , Chun-Hsiung Hung
发明人： Chung-Kuang Chen , Han-Sung Chen , Chun-Hsiung Hung
IPC分类号： G11C16/06 , G11C16/04
CPC分类号： G11C16/28 , G11C16/06
摘要： The configurations of a flash memory having a read tracking clock and method thereof are provided. The proposed flash memory includes a first and a second storage capacitors, a first current source providing a first current flowing through the first storage capacitor, a second current source providing a second current flowing through the second storage capacitor, and a comparator electrically connected to the first and the second current sources, and sending out a signal indicating a developing time being accomplished when the second current is larger than the first current.
摘要翻译：提供具有读追踪时钟及其方法的闪速存储器的配置。所提出的闪速存储器包括第一和第二存储电容器，提供流过第一存储电容器的第一电流的第一电流源，提供流过第二存储电容器的第二电流的第二电流源，以及电连接到第一和第二电流源，并且当第二电流大于第一电流时发出指示正在完成的显影时间的信号。

95. 发明申请

US20130148445A1 LOCAL WORD LINE DRIVER 有权
标题翻译：本地字线驱动器
公开(公告)号：US20130148445A1
公开(公告)日：2013-06-13
申请号：US13713829
申请日：2012-12-13
申请人： Chung-Kuang Chen , Han-Sung Chen , Chun-Hsiung Hung
发明人： Chung-Kuang Chen , Han-Sung Chen , Chun-Hsiung Hung
IPC分类号： G11C8/08 , G11C7/12
CPC分类号： G11C8/08 , G11C7/12
摘要： A memory circuit with a word line driver and control circuitry is disclosed. The plurality of word line drivers are coupled to a plurality of word lines. Word line drivers include a CMOS inverter, which can have an input and an output, and a p-type transistor and an n-type transistor. The output of the CMOS inverter is coupled to one of the plurality of word lines. The control circuitry has multiple modes, including at least a first mode to discharge a particular word line of the plurality of word lines via a first discharge path such as at least a first transistor type of the CMOS inverter; and a second mode to discharge the particular word line of the plurality of word lines via a second discharge path such as at least the a second transistor type of the CMOS inverter.
摘要翻译：公开了具有字线驱动器和控制电路的存储器电路。多个字线驱动器耦合到多个字线。字线驱动器包括可以具有输入和输出的CMOS反相器，以及p型晶体管和n型晶体管。 CMOS反相器的输出耦合到多个字线之一。控制电路具有多种模式，包括至少第一模式，以经由诸如至少第一晶体管类型的CMOS反相器的第一放电路径放电多个字线的特定字线; 以及第二模式，用于经由诸如至少第二晶体管类型的CMOS反相器的第二放电路径放电多个字线的特定字线。

96. 发明申请

US20130076423A1 Integrated Circuit With Delay Circuitry 有权
标题翻译：具有延迟电路的集成电路
公开(公告)号：US20130076423A1
公开(公告)日：2013-03-28
申请号：US13240654
申请日：2011-09-22
申请人： Chung-Kuang Chen
发明人： Chung-Kuang Chen
IPC分类号： H03H11/26 , H03L5/00
CPC分类号： H03K5/131
摘要： The delay circuit, such as a clock circuit, of an integrated circuit operates with tolerance of variation in temperature. For example, the delay circuit has a temperature dependent current generator that has an adjustable temperature coefficient, such that a range of temperature coefficients is selectable at a particular current output. Also, the clock circuit of an integrated circuit operates with multiple versions of a current that controls a discharging rate and/or a charging rate between reference signals of timing circuitry.
摘要翻译：集成电路的延迟电路（例如时钟电路）具有温度变化的公差。例如，延迟电路具有温度依赖性电流发生器，其具有可调节的温度系数，使得温度系数的范围可在特定电流输出端选择。此外，集成电路的时钟电路以控制放电速率和/或定时电路的参考信号之间的充电速率的多种电流工作。

97. 发明授权

US08400203B1 Integrated circuit with delay circuitry 有权
标题翻译：具有延迟电路的集成电路
公开(公告)号：US08400203B1
公开(公告)日：2013-03-19
申请号：US13240654
申请日：2011-09-22
申请人： Chung-Kuang Chen
发明人： Chung-Kuang Chen
IPC分类号： H03K3/00
CPC分类号： H03K5/131
摘要： The delay circuit, such as a clock circuit, of an integrated circuit operates with tolerance of variation in temperature. For example, the delay circuit has a temperature dependent current generator that has an adjustable temperature coefficient, such that a range of temperature coefficients is selectable at a particular current output. Also, the clock circuit of an integrated circuit operates with multiple versions of a current that controls a discharging rate and/or a charging rate between reference signals of timing circuitry.
摘要翻译：集成电路的延迟电路（例如时钟电路）具有温度变化的公差。例如，延迟电路具有温度依赖性电流发生器，其具有可调节的温度系数，使得温度系数的范围可在特定电流输出端选择。此外，集成电路的时钟电路以控制放电速率和/或定时电路的参考信号之间的充电速率的多种电流工作。

98. 发明授权

US08295086B2 Memory array 有权
标题翻译：内存阵列
公开(公告)号：US08295086B2
公开(公告)日：2012-10-23
申请号：US13180854
申请日：2011-07-12
申请人： Chih-He Chiang , Chung-Kuang Chen , Han-Sung Chen
发明人： Chih-He Chiang , Chung-Kuang Chen , Han-Sung Chen
IPC分类号： G11C16/04
CPC分类号： G11C16/0491 , G11C16/26
摘要： A memory array is shown, including memory cells with source and drain doped regions, and global bit lines coupled to the doped regions via select transistors. The connections of the select transistors are configured such that the respective loading capacitances of two global bit lines respectively coupled to the source and the drain of a memory cell to be read do not vary with the memory cell to be read.
摘要翻译：示出了存储器阵列，包括具有源极和漏极掺杂区域的存储器单元，以及经由选择晶体管耦合到掺杂区域的全局位线。选择晶体管的连接被配置为使得分别耦合到要读取的存储器单元的源极和漏极的两个全局位线的相应负载电容不随着要读取的存储器单元而变化。

99. 发明申请

US20120262990A1 MEMORY DEVICE 有权
标题翻译：内存设备
公开(公告)号：US20120262990A1
公开(公告)日：2012-10-18
申请号：US13466915
申请日：2012-05-08
申请人： Chung-Kuang Chen
发明人： Chung-Kuang Chen
IPC分类号： G11C16/04
CPC分类号： G11C16/30 , G11C16/0483 , G11C16/10
摘要： A memory device comprises a main memory array having a plurality of bit lines, and a select array having a plurality of transistors coupled to the bit lines. Wherein one of the plurality of transistors is electrically programmed to a threshold voltage greater than a threshold voltage of another one of the plurality of transistors.
摘要翻译：存储器件包括具有多个位线的主存储器阵列和具有耦合到位线的多个晶体管的选择阵列。其中多个晶体管中的一个被电编程到大于多个晶体管中的另一晶体管的阈值电压的阈值电压。

100. 发明授权

US08275929B2 Memory and operating method thereof 有权
标题翻译：其记忆及操作方法
公开(公告)号：US08275929B2
公开(公告)日：2012-09-25
申请号：US12260258
申请日：2008-10-29
申请人： Chung-Kuang Chen , Han-Sung Chen , Chun-Hsiung Hung
发明人： Chung-Kuang Chen , Han-Sung Chen , Chun-Hsiung Hung
IPC分类号： G06F12/00 , G06F13/00 , G06F13/28 , G11C11/34 , G11C16/04
CPC分类号： G06F12/0238 , G06F2212/2142
摘要： A method of programming data stored in a memory, which comprises a number of user-defined blocks, a number of manufacture-defined blocks, and an information block, includes the following steps. A programming address pointing to a user-defined block in the memory and programming data is obtained. After that, it is determined whether there is an empty manufacture-defined block among a number of user-defined blocks in the memory. If so, an information block in the memory is programmed to store the programming address and a replacing address pointing to the empty manufacture-defined block. The empty manufacture-defined block is programmed to store the programming data.
摘要翻译：一种存储在存储器中的数据的方法，包括多个用户定义的块，多个制造定义的块和信息块，包括以下步骤。获得指向存储器中的用户定义块的编程地址和编程数据。之后，确定存储器中的多个用户定义的块中是否存在空的制造定义块。如果是这样，则存储器中的信息块被编程为存储编程地址和指向空制造定义块的替换地址。空的制造定义块被编程为存储编程数据。

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