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91. 发明申请

US20080224259A1 METHODS OF FABRICATING PASSIVE ELEMENT WITHOUT PLANARIZING AND RELATED SEMICONDUCTOR DEVICE 有权
公开(公告)号：US20080224259A1
公开(公告)日：2008-09-18
申请号：US12106374
申请日：2008-04-21
申请人： Anil K. Chinthakindi , Timothy J. Dalton , Ebenezer E. Eshun , Jeffrey P. Gambino , Anthony K. Stamper , Kunal Vaed
发明人： Anil K. Chinthakindi , Timothy J. Dalton , Ebenezer E. Eshun , Jeffrey P. Gambino , Anthony K. Stamper , Kunal Vaed
IPC分类号： H01L29/00 , H01L21/02
CPC分类号： H01L21/76819 , H01L23/522 , H01L28/40 , H01L2924/0002 , H01L2924/00
摘要： Methods of fabricating a passive element and a semiconductor device including the passive element are disclosed including the use of a dummy passive element. A dummy passive element is a passive element or wire which is added to the chip layout to aid in planarization but is not used in the active circuit. One embodiment of the method includes forming the passive element and a dummy passive element adjacent to the passive element; forming a dielectric layer over the passive element and the dummy passive element, wherein the dielectric layer is substantially planar between the passive element and the dummy passive element; and forming in the dielectric layer an interconnect to the passive element through the dielectric layer and a dummy interconnect portion overlapping at least a portion of the dummy passive element. The methods eliminate the need for planarizing.

92. 发明授权

US07394145B2 Methods of fabricating passive element without planarizing and related semiconductor device 有权
标题翻译：无平面化制造无源元件及相关半导体器件的方法
公开(公告)号：US07394145B2
公开(公告)日：2008-07-01
申请号：US11928798
申请日：2007-10-30
申请人： Anil K Chinthakindi , Timothy J. Dalton , Ebenezer E. Eshun , Jeffrey P. Gambino , Anthony K. Stamper , Kunal Vaed
发明人： Anil K Chinthakindi , Timothy J. Dalton , Ebenezer E. Eshun , Jeffrey P. Gambino , Anthony K. Stamper , Kunal Vaed
IPC分类号： H01L29/00 , H01L21/20
CPC分类号： H01L21/76819 , H01L23/522 , H01L28/40 , H01L2924/0002 , H01L2924/00
摘要： Methods of fabricating a passive element and a semiconductor device including the passive element are disclosed including the use of a dummy passive element. A dummy passive element is a passive element or wire which is added to the chip layout to aid in planarization but is not used in the active circuit. One embodiment of the method includes forming the passive element and a dummy passive element adjacent to the passive element; forming a dielectric layer over the passive element and the dummy passive element, wherein the dielectric layer is substantially planar between the passive element and the dummy passive element; and forming in the dielectric layer an interconnect to the passive element through the dielectric layer and a dummy interconnect portion overlapping at least a portion of the dummy passive element. The methods eliminate the need for planarizing.
摘要翻译：公开了制造无源元件的方法和包括无源元件的半导体器件，其包括使用虚拟无源元件。虚拟无源元件是被添加到芯片布局以帮助平坦化但在有源电路中不使用的无源元件或线。该方法的一个实施例包括形成无源元件和邻近无源元件的虚拟无源元件; 在无源元件和虚拟无源元件上形成电介质层，其中介电层在无源元件和虚拟无源元件之间基本上是平面的; 并且在所述电介质层中形成通过所述介电层与所述无源元件的互连以及与所述虚拟无源元件的至少一部分重叠的虚拟互连部分。该方法消除了平面化的需要。

93. 发明授权

US07375039B2 Local plasma processing 失效
标题翻译：局部等离子体处理
公开(公告)号：US07375039B2
公开(公告)日：2008-05-20
申请号：US10908709
申请日：2005-05-24
申请人： Jeffrey P. Gambino , Thomas L. McDevitt , Anthony K. Stamper
发明人： Jeffrey P. Gambino , Thomas L. McDevitt , Anthony K. Stamper
IPC分类号： H01L21/31 , H01L21/469
CPC分类号： C23C16/04 , C23C16/513 , H01J37/32366
摘要： A method and an apparatus for performing the method. The method includes: (a) providing an apparatus, wherein the apparatus comprises (i) a chamber, (ii) a plasma device being in and coupled to the chamber, (iii) a shower head being in and coupled to the chamber, and (iv) a chuck being in and coupled to the chamber; (b) placing the substrate on the chuck; (c) using the plasma device to receive a plasma device gas and generate a plasma; (d) directing the plasma at a pre-specified area on the substrate; and (e) using the shower head to receive and distribute a shower head gas in the chamber, wherein the plasma device gas and the shower head gas are selected such that the plasma and the shower head gas when mixed with each other result in a chemical reaction that forms a film at the pre-specified area on the substrate.
摘要翻译：一种用于执行该方法的方法和装置。该方法包括：（a）提供一种设备，其中所述设备包括（i）室，（ii）位于室中并耦合到所述室的等离子体设备，（iii）淋浴喷头位于并联接到所述室，以及（iv）卡盘位于并联接到所述腔室; （b）将基板放置在卡盘上; （c）使用等离子体装置接收等离子体装置气体并产生等离子体; （d）将等离子体引导到基板上的预定区域; 以及（e）使用所述淋浴头来接收和分配所述腔室中的淋浴头气体，其中所述等离子体装置气体和所述喷淋头气体被选择为使得当彼此混合时所述等离子体和所述淋浴头气体产生化学物质在基板上的预定区域形成膜的反应。

94. 发明授权

US07285474B2 Air-gap insulated interconnections 有权
标题翻译：气隙绝缘互连
公开(公告)号：US07285474B2
公开(公告)日：2007-10-23
申请号：US10711394
申请日：2004-09-16
申请人： Brent A. Anderson , Andres Bryant , Jeffrey P. Gambino , Anthony K. Stamper
发明人： Brent A. Anderson , Andres Bryant , Jeffrey P. Gambino , Anthony K. Stamper
IPC分类号： H01L21/76 , H01L21/4763
CPC分类号： H01L21/7682 , H01L21/76802 , H01L21/76807 , H01L21/76831 , H01L21/76835 , H01L23/5222 , H01L23/53238 , H01L23/5329 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： Air-gap insulated interconnection structures and methods of fabricating the structures, the methods including: forming a dielectric layer on a substrate; forming a capping layer on a top surface of the dielectric layer; forming a trench through the capping layer, the trench extending toward said substrate and into but not through, the dielectric layer; forming a sacrificial layer on opposing sidewalls of the trench; filling the trench with a electrical conductor; and removing a portion of the sacrificial layer from between the electrical conductor and the dielectric layer to form air-gaps.
摘要翻译：气隙绝缘互连结构及其制造方法，包括：在基板上形成电介质层; 在所述电介质层的顶表面上形成覆盖层; 通过所述覆盖层形成沟槽，所述沟槽朝向所述衬底延伸并且穿过所述电介质层; 在沟槽的相对侧壁上形成牺牲层; 用电导体填充沟槽; 以及从所述电导体和所述电介质层之间移除所述牺牲层的一部分以形成气隙。

95. 发明授权

US07037824B2 Copper to aluminum interlayer interconnect using stud and via liner 有权
公开(公告)号：US07037824B2
公开(公告)日：2006-05-02
申请号：US10844533
申请日：2004-05-13
申请人： Lloyd G. Burrell , Edward E. Cooney, III , Jeffrey P. Gambino , John E. Heidenreich, III , Hyun Koo Lee , Mark D. Levy , Baozhen Li , Stephen E. Luce , Thomas L. McDevitt , Anthony K. Stamper , Kwong Hon Wong , Sally J. Yankee
发明人： Lloyd G. Burrell , Edward E. Cooney, III , Jeffrey P. Gambino , John E. Heidenreich, III , Hyun Koo Lee , Mark D. Levy , Baozhen Li , Stephen E. Luce , Thomas L. McDevitt , Anthony K. Stamper , Kwong Hon Wong , Sally J. Yankee
IPC分类号： H01L21/4763
CPC分类号： H01L21/76843 , H01L21/76838 , H01L23/5226 , H01L23/53223 , H01L23/53228 , H01L2924/0002 , H01L2924/00
摘要： Tungsten studs of a size comparable to vias are provided to integrate and interface between copper and aluminum metallization layers in an integrated circuit and/or package therefor by lining a via opening, preferably with layers of tantalum nitride and PVD tungsten as a barrier against the corrosive effects of tungsten fluoride on copper. The reduced size of the tungsten studs relative to known interface structures allows wiring and connection pads to be formed in a single aluminum layer, improving performance and reducing process time and cost.

96. 发明授权

US06797610B1 Sublithographic patterning using microtrenching 有权
标题翻译：使用微切削的亚光刻图案
公开(公告)号：US06797610B1
公开(公告)日：2004-09-28
申请号：US10248019
申请日：2002-12-11
申请人： Jeffrey P. Gambino , Peter J. Lindgren , Anthony K. Stamper
发明人： Jeffrey P. Gambino , Peter J. Lindgren , Anthony K. Stamper
IPC分类号： H01L214763
CPC分类号： H01L21/76802
摘要： A sublitohgraphic trench is formed in a semiconductor substrate by first forming a microtrench which is subsequently used as a mask. Filled sublithographic trenches are formed with a width corresponding to the width of the microtrenches.
摘要翻译：通过首先形成随后用作掩模的微切口，在半导体衬底中形成子晶体学沟槽。填充的亚光刻沟槽形成为具有对应于微锥体宽度的宽度。

97. 发明授权

US06858889B2 Polysilicon capacitor having large capacitance and low resistance 失效
标题翻译：具有大电容和低电阻的多晶硅电容器
公开(公告)号：US06858889B2
公开(公告)日：2005-02-22
申请号：US09878117
申请日：2001-06-08
申请人： James W. Adkisson , John A. Bracchitta , Jed H. Rankin , Anthony K. Stamper
发明人： James W. Adkisson , John A. Bracchitta , Jed H. Rankin , Anthony K. Stamper
IPC分类号： H01L21/02 , H01L21/314 , H01L21/334 , H01L21/8242 , H01L29/78 , H01L33/00
CPC分类号： H01L28/75 , H01L21/3144 , H01L28/91
摘要： A process for forming capacitors in a semiconductor device. In one embodiment, a first insulating layer is deposited on the semiconductor device; a trench is formed in the insulating layer; a first low resistance metal layer is formed covering the interior surface of the trench; a first polysilicon layer is formed over the first low resistance metal layer; a first dielectric layer is formed over the first polysilicon layer; a second polysilicon layer is formed over the first dielectric layer; a second low resistance metal layer is formed over the second polysilicon layer; a third polysilicon layer is formed over the second low resistance metal layer; a second dielectric layer is formed over the third polysilicon layer; a fourth polysilicon layer is formed over the second dielectric layer; a third low resistance metal layer is formed over the fourth polysilicon layer until the trench is filled; the semiconductor device is planarized until the first, second and third low resistance metal layers are exposed above the trench; finally, capacitor leads are formed to the first, second, and third low resistance metal layers.
摘要翻译：一种用于在半导体器件中形成电容器的工艺。在一个实施例中，第一绝缘层沉积在半导体器件上; 在绝缘层中形成沟槽; 形成覆盖沟槽内表面的第一低电阻金属层; 在第一低电阻金属层上形成第一多晶硅层; 第一介电层形成在第一多晶硅层上; 在第一介电层上形成第二多晶硅层; 在第二多晶硅层上形成第二低电阻金属层; 在第二低电阻金属层上形成第三多晶硅层; 在所述第三多晶硅层上形成第二电介质层; 在第二介电层上形成第四多晶硅层; 第四低电阻金属层形成在第四多晶硅层上，直到沟槽被填充; 半导体器件被平坦化，直到第一，第二和第三低电阻金属层暴露在沟槽上方; 最后，对第一，第二和第三低电阻金属层形成电容器引线。

98. 发明授权

US06653710B2 Fuse structure with thermal and crack-stop protection 失效
公开(公告)号：US06653710B2
公开(公告)日：2003-11-25
申请号：US09788077
申请日：2001-02-16
申请人： James W. Adkisson , Edward Maciejewski , Peter Smeys , Anthony K. Stamper
发明人： James W. Adkisson , Edward Maciejewski , Peter Smeys , Anthony K. Stamper
IPC分类号： H01L2900
CPC分类号： H01L23/5329 , H01L23/3735 , H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： Thermal degradation of a low-k organic dielectric material is avoided or limited in the proximity of a heat source such as a fusible element by overlaying the low-k material with a thermally conductive material and providing a low thermal resistance path from the thermally conductive material, possibly having a low modulus of elasticity, to a heat sink. The thermally conductive material thus provides crack-stop protection for further layers of an integrated circuit or interconnect structure above the fusible element by mechanical, chemical and thermal encapsulation of the heat source and low-k material.

99. 发明授权

US06403393B1 Device having integrated optical and copper conductors and method of fabricating same 失效
标题翻译：具有集成光和铜导体的装置及其制造方法
公开(公告)号：US06403393B1
公开(公告)日：2002-06-11
申请号：US09388163
申请日：1999-09-01
申请人： James W. Adkisson , Paul W. Pastel , Anthony K. Stamper
发明人： James W. Adkisson , Paul W. Pastel , Anthony K. Stamper
IPC分类号： G02B600
CPC分类号： G02B6/132 , G02B6/122 , G02B6/13 , G02B2006/121
摘要： A method is provided for making optical waveguide structures in a semiconductor device wherein a rectangular cross-section low index of refraction material is encapsulated in a trench by a high index of refraction material. The waveguide structures may be made in a device containing copper conductors in trenches by forming new trenches to hold the optical waveguide. Copper conductor containing trenches may also be made in an electronic component containing waveguide structures and a further method is provided for forming an optical waveguide structure by replacing a copper containing trench with the waveguide structure in an electronic component having a plurality of copper containing trenches. All the methods use conventional techniques so that the fabrication of a semiconductor device containing both optical waveguide structures and copper conductor structures can be made both efficiently and economically.
摘要翻译：提供了一种用于在半导体器件中制造光波导结构的方法，其中通过高折射率材料将矩形横截面的低折射率材料折射率封装在沟槽中。波导结构可以通过形成新的沟槽来保持光波导，在包含沟槽中的铜导体的器件中制成。包含沟槽的铜导体也可以制成包含波导结构的电子部件，并且提供了另外的方法，用于通过在具有多个含铜沟槽的电子部件中用波导结构替换含铜沟槽来形成光波导结构。所有这些方法都使用常规技术，从而可以有效地和经济地制造含有光波导结构和铜导体结构的半导体器件。

100. 发明授权

US07494748B2 Method for correction of defects in lithography masks 失效
标题翻译：光刻掩模中缺陷校正方法
公开(公告)号：US07494748B2
公开(公告)日：2009-02-24
申请号：US10904308
申请日：2004-11-03
申请人： James W. Adkisson , Eric M. Coker , Christopher K. Magg , Jed H. Rankin , Anthony K. Stamper
发明人： James W. Adkisson , Eric M. Coker , Christopher K. Magg , Jed H. Rankin , Anthony K. Stamper
IPC分类号： G03F1/00
CPC分类号： G03F1/72 , G03F1/70
摘要： A method for correction of defects in lithography masks includes determining the existence of mask defects on an original mask, and identifying a stitchable zone around each of the mask defects found on the original mask. Each of the identified stitchable zones on the original mask is blocked out such that circuitry within the stitchable zones is not printed out during exposure of the original mask. A repair mask is formed, the repair mask including corrected circuit patterns from each of the identified stitchable zones.
摘要翻译：用于校正光刻掩模中的缺陷的方法包括确定原始掩模上的掩模缺陷的存在，以及识别在原始掩模上发现的每个掩模缺陷周围的可缝合区域。原始掩模上的每个识别的可缝合区域被阻挡，使得在原始掩模曝光期间不能打印出可缝合区域内的电路。形成修复掩模，修复掩模包括来自每个识别的可缝合区域的校正电路图案。

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