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91. 发明申请

US20120187418A1 SEMICONDUCTOR STRUCTURE AND METHOD FOR MANUFACTURING THE SAME 审中-公开
标题翻译：半导体结构及其制造方法
公开(公告)号：US20120187418A1
公开(公告)日：2012-07-26
申请号：US13380964
申请日：2011-03-04
申请人： Haizhou Yin , Zhijiong Luo , Huilong Zhu
发明人： Haizhou Yin , Zhijiong Luo , Huilong Zhu
IPC分类号： H01L29/04 , H01L21/20 , H01L29/36 , H01L29/24 , H01L29/20
CPC分类号： H01L29/785 , H01L29/045
摘要： The present application provides a semiconductor structure and a method for manufacturing the same. The semiconductor structure comprises a semiconductor substrate, a semiconductor fin located on the semiconductor substrate, and an etch stop layer located between the semiconductor substrate and the semiconductor fin, wherein a lateral sidewall of the semiconductor fin is substantially on the Si {111} crystal plane. Since the semiconductor fin exhibits better surface quality and less crystal defects, it is favorable for manufacturing FINFET.
摘要翻译：本申请提供了一种半导体结构及其制造方法。所述半导体结构包括半导体衬底，位于所述半导体衬底上的半导体鳍片，以及位于所述半导体衬底和所述半导体鳍片之间的蚀刻停止层，其中所述半导体鳍片的横向侧壁基本上位于所述Si {111}晶面上。由于半导体鳍具有更好的表面质量和更少的晶体缺陷，因此有利于制造FINFET。

92. 发明申请

US20120104466A1 METHOD FOR FABRICATING CONTACT ELECTRODE AND SEMICONDUCTOR DEVICE 有权
标题翻译：用于制造接触电极和半导体器件的方法
公开(公告)号：US20120104466A1
公开(公告)日：2012-05-03
申请号：US13129075
申请日：2011-02-24
申请人： Huilong Zhu , Haizhou Yin , Zhijiong Luo
发明人： Huilong Zhu , Haizhou Yin , Zhijiong Luo
IPC分类号： H01L29/772 , H01L21/768
CPC分类号： H01L23/485 , H01L29/41775 , H01L29/6659 , H01L29/66628 , H01L29/7834 , H01L29/7845 , H01L2924/0002 , H01L2924/00
摘要： The invention provides a semiconductor device comprising: a substrate; a gate, which is formed on the substrate; a source and a drain, which are located on opposite sides of the gate, respectively; a contact, which contacts with the source and/or the drain, wherein the contact has an enlarged end at an end which is in contact with the source and/or the drain. In the present invention, since the contact area of the contact is increased on the interface in contact with the source/the drain, the contact resistance can be reduced, and thus the performances of the semiconductor device can be guaranteed/improved. The present invention further provides a method of fabricating the semiconductor device (especially the contact therein) as previously described.
摘要翻译：本发明提供了一种半导体器件，包括：衬底; 形成在基板上的栅极; 源极和漏极分别位于栅极的相对侧上; 接触件，其与源极和/或漏极接触，其中接触件在与源极和/或漏极接触的端部处具有扩大的端部。在本发明中，由于在与源极/漏极接触的界面上接触面的接触面积增加，所以可以降低接触电阻，能够保证/提高半导体器件的性能。本发明还提供如前所述制造半导体器件（特别是其中的接触）的方法。

93. 发明申请

US20120080722A1 METHOD FOR FORMING STRAINED SEMICONDUCTOR CHANNEL AND SEMICONDUCTOR DEVICE 审中-公开
标题翻译：形成应变半导体通道和半导体器件的方法
公开(公告)号：US20120080722A1
公开(公告)日：2012-04-05
申请号：US13128931
申请日：2011-02-25
申请人： Haizhou Yin , Zhijiong Luo , Huilong Zhu
发明人： Haizhou Yin , Zhijiong Luo , Huilong Zhu
IPC分类号： H01L27/092 , H01L21/8238
CPC分类号： H01L21/823807 , H01L21/823842 , H01L29/1054 , H01L29/517 , H01L29/66545 , H01L29/66651
摘要： A semiconductor device includes: a semiconductor substrate; a SiGe relaxed layer on the semiconductor substrate; an NMOS transistor on the SiGe relaxed layer; and a PMOS transistor on the SiGe relaxed layer, in which the NMOS transistor includes a tensile strained epitaxial layer located on the SiGe relaxed layer or embedded in the SiGe relaxed layer; and the PMOS transistor includes a compressive strained epitaxial layer located on the SiGe relaxed layer or embedded in the SiGe relaxed layer. The loss of the strained semiconductor material can be avoided and meanwhile the stress in the channel can be better maintained.
摘要翻译：半导体器件包括：半导体衬底; 半导体衬底上的SiGe弛豫层; SiGe弛豫层上的NMOS晶体管; 以及SiGe弛豫层上的PMOS晶体管，其中NMOS晶体管包括位于SiGe弛豫层上或嵌入SiGe弛豫层中的拉伸应变外延层; 并且PMOS晶体管包括位于SiGe松弛层上或嵌入SiGe弛豫层中的压缩应变外延层。可以避免应变半导体材料的损失，同时可以更好地保持通道中的应力。

94. 发明申请

US20120037211A1 Thin Film of Solar Battery Structure, Thin Film of Solar Array and Manufacturing Method Thereof 审中-公开
标题翻译：太阳能电池结构薄膜，太阳能阵列薄膜及其制造方法
公开(公告)号：US20120037211A1
公开(公告)日：2012-02-16
申请号：US13264126
申请日：2010-04-14
申请人： Huilong Zhu , Zhijiong Luo , Haizhou Yin
发明人： Huilong Zhu , Zhijiong Luo , Haizhou Yin
IPC分类号： H01L31/0376 , H01L27/142 , H01L31/18
CPC分类号： H01L31/0392 , H01L31/035281 , Y02E10/50
摘要： The present invention proposes a thin-film solar cell structure, a method for manufacturing the same and a thin-film solar cell array. The method for manufacturing thin-film solar cell structures comprises: forming at least two first trenches through a first surface into said semiconductor substrate, forming at least one second trench through a second surface into said semiconductor substrate, said second trench located between two neighboring said first trenches; forming a first structure on sidewalls of each of said first trenches; to forming a second structure on sidewalls of each of said second trench; and cutting or stretching said semiconductor substrate to form thin-film solar cell structures. The distance between the electrodes can be effectively shortened through the present invention such that the recombination rate between the electrons and the holes can be reduced and the bulk recombination current and the surface recombination current can be reduced to achieve the objective of improving power generation efficiency. The thin-film solar cell structure and the method for manufacturing the same proposed in the present invention can also save semiconductor material and reduce production cost.
摘要翻译：本发明提出一种薄膜太阳能电池结构体及其制造方法以及薄膜太阳能电池阵列。制造薄膜太阳能电池结构的方法包括：通过第一表面形成至少两个第一沟槽到所述半导体衬底中，通过第二表面形成至少一个第二沟槽到所述半导体衬底中，所述第二沟槽位于两个相邻的所述第一壕沟在每个所述第一沟槽的侧壁上形成第一结构; 以在每个所述第二沟槽的侧壁上形成第二结构; 以及切割或拉伸所述半导体衬底以形成薄膜太阳能电池结构。通过本发明可以有效地缩短电极之间的距离，从而可以减小电子和空穴之间的复合速率，并且可以减小体积复合电流和表面复合电流，以达到提高发电效率的目的。本发明中提出的薄膜太阳能电池结构及其制造方法也可以节省半导体材料并降低生产成本。

95. 发明申请

US20120032230A1 METHOD OF FORMING STRAINED SEMICONDUCTOR CHANNEL AND SEMICONDUCTOR DEVICE 有权
标题翻译：形成应变半导体通道和半导体器件的方法
公开(公告)号：US20120032230A1
公开(公告)日：2012-02-09
申请号：US13059285
申请日：2010-09-19
申请人： Haizhou Yin , Huilong Zhu , Zhijiong Luo
发明人： Haizhou Yin , Huilong Zhu , Zhijiong Luo
IPC分类号： H01L29/78 , H01L21/20 , B82Y40/00 , B82Y99/00
CPC分类号： H01L29/66651 , H01L21/02381 , H01L21/02433 , H01L21/0245 , H01L21/02505 , H01L21/0251 , H01L21/02532 , H01L29/1054 , H01L29/517 , H01L29/66545
摘要： The present invention provides a method of forming a strained semiconductor channel, comprising: forming a relaxed SiGe layer on a semiconductor substrate; forming a dielectric layer on the relaxed SiGe layer and forming a sacrificial gate on the dielectric layer, wherein the dielectric layer and the sacrificial gate form a sacrificial gate structure; depositing an interlayer dielectric layer, which is planarized to expose the sacrificial gate; etching to remove the sacrificial gate and the dielectric layer to form an opening; forming a semiconductor epitaxial layer by selective semiconductor epitaxial growth in the opening; depositing a high-K dielectric layer and a metal layer; and removing the high-K dielectric layer and metal layer covering the interlayer dielectric layer by planarizing the deposited metal layer and high-K dielectric layer to form a metal gate. The present invention also provides a semiconductor device manufactured by this process.
摘要翻译：本发明提供一种形成应变半导体沟道的方法，包括：在半导体衬底上形成松弛的SiGe层; 在弛豫的SiGe层上形成电介质层，并在电介质层上形成牺牲栅极，其中电介质层和牺牲栅极形成牺牲栅极结构; 沉积层间电介质层，其被平坦化以暴露所述牺牲栅极; 蚀刻去除牺牲栅极和电介质层以形成开口; 通过开口中的选择性半导体外延生长形成半导体外延层; 沉积高K电介质层和金属层; 并且通过平坦化沉积的金属层和高K电介质层来去除覆盖层间电介质层的高K电介质层和金属层，以形成金属栅极。本发明还提供了通过该方法制造的半导体器件。

96. 发明申请

US20110260264A1 SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20110260264A1
公开(公告)日：2011-10-27
申请号：US12937321
申请日：2010-06-28
申请人： Zhijiong Luo , Haizhou Yin , Huilong Zhu
发明人： Zhijiong Luo , Haizhou Yin , Huilong Zhu
IPC分类号： H01L29/772 , H01L21/336
CPC分类号： H01L21/823835 , H01L21/823814 , H01L21/823871 , H01L29/4966 , H01L29/665 , H01L29/66545 , H01L29/6656
摘要： There is provided a semiconductor device and a method of fabricating the same. The method of fabricating a semiconductor device according to the present invention comprises: forming a transistor structure including a gate, and source and drain regions on a semiconductor substrate; carrying out a first silicidation to form a first metal silicide layer on the source and drain regions; depositing a first dielectric layer on the substrate, the top of the first dielectric layer being flush with the top of the gate region; forming contact holes at the portions corresponding to the source and drain regions in the first dielectric layer; and carrying out a second silicidation to form a second metal silicide at the gate region and in the contact holes, wherein the first metal silicide layer is formed to prevent silicidation from occurring at the source and drain regions during the second silicidation. According to the present invention, it is possible not only to reduce the gate resistance, but also to eliminate difficulties in forming contact holes by RIE at the gate and source/drain regions.
摘要翻译：提供了一种半导体器件及其制造方法。根据本发明的制造半导体器件的方法包括：在半导体衬底上形成包括栅极和源极和漏极区域的晶体管结构; 进行第一硅化，以在源区和漏区上形成第一金属硅化物层; 在所述衬底上沉积第一介电层，所述第一介电层的顶部与所述栅极区的顶部齐平; 在与第一电介质层中的源极和漏极区对应的部分处形成接触孔; 并且在所述栅极区和所述接触孔中进行第二硅化以形成第二金属硅化物，其中形成所述第一金属硅化物层以防止在所述第二硅化期间在所述源极和漏极区发生硅化。根据本发明，不仅可以降低栅极电阻，而且可以消除在栅极和源极/漏极区域通过RIE形成接触孔的困难。

97. 发明申请

US20110260262A1 SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20110260262A1
公开(公告)日：2011-10-27
申请号：US12999796
申请日：2010-09-17
申请人： Haizhou Yin , Zhijiong Luo , Huilong Zhu
发明人： Haizhou Yin , Zhijiong Luo , Huilong Zhu
IPC分类号： H01L27/088 , H01L21/8232
CPC分类号： H01L21/823468 , H01L21/76895 , H01L21/76897 , H01L21/823425 , H01L21/823475
摘要： A semiconductor device includes a semiconductor substrate; gates, spacers on both sides of the respective gates, and source and gain regions on both sides of the respective spacers, which are formed on the semiconductor substrate; lower contacts located on the respective source and gain regions and abutting outer-sidewalls of the spacers, with bottoms covering at least a portion of the respective source and gain regions; an inter-layer dielectric layer formed on the gates, the spacers, the source and gain regions, and the lower contacts, wherein the respective source and gain regions of each of the transistor structures are isolated from each other by the inter-layer dielectric layer; and upper contacts formed in the inter-layer dielectric layer and corresponding to the lower contacts. Methods for fabricating such a semiconductor device and for manufacturing contacts for semiconductor devices.
摘要翻译：半导体器件包括半导体衬底; 各个栅极的两侧的栅极，间隔物，以及形成在半导体衬底上的各个间隔物的两侧的源极和增益区域; 下部触点位于相应的源极和增益区域以及邻接的间隔物的外侧壁上，底部覆盖相应的源极和增益区域的至少一部分; 形成在栅极，间隔物，源极和增益区域以及下部触点上的层间电介质层，其中每个晶体管结构的各个源极和增益区域通过层间电介质层彼此隔离 ; 以及形成在层间电介质层中并对应于下触点的上触点。用于制造这种半导体器件和用于制造用于半导体器件的触点的方法。

98. 发明申请

US20110227144A1 HIGH-PERFORMANCE SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME 有权
标题翻译：高性能半导体器件及其制造方法
公开(公告)号：US20110227144A1
公开(公告)日：2011-09-22
申请号：US12999086
申请日：2010-06-25
申请人： Haizhou Yin , Huilong Zhu , Zhijiong Luo
发明人： Haizhou Yin , Huilong Zhu , Zhijiong Luo
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/495 , H01L21/26513 , H01L21/2652 , H01L21/2658 , H01L21/26586 , H01L21/823842 , H01L29/4966 , H01L29/517 , H01L29/66492 , H01L29/66545
摘要： The present invention relates to a method of manufacturing a semiconductor device, and the method uses the mode of thermal annealing the source/drain regions and performing Halo ion implantation to form a Halo ion-implanted region by: first removing the dummy gate to expose the gate dielectric layer to form an opening; then performing a tilted Halo ion implantation to the device from the opening to form a Halo ion-implanted region on both sides of the channel of the semiconductor device; and then annealing to activate the dopants in the Halo ion-implanted region; finally performing subsequent process to the device according to the requirement of the manufacture process. Through the present invention, the dopants in the Halo ion-implanted region improperly introduced to the source region and the drain region may be reduced, and then the overlap between the Halo ion-implantation region and the dopant region of the source/drain regions may be reduced, thus to reduce the band-band leakage current in the MOSFET, and hence improve the performance of the device.
摘要翻译：本发明涉及一种制造半导体器件的方法，该方法使用对源/漏区进行热退火的方式，并进行Halo离子注入以形成Halo离子注入区域，方法是首先去除伪栅极以暴露出栅介电层形成开口; 然后从所述开口对所述器件进行倾斜的Halo离子注入，以在所述半导体器件的沟道的两侧上形成Halo离子注入区域; 然后退火以激活卤素离子注入区域中的掺杂剂; 最后根据制造过程的要求对设备进行后续处理。通过本发明，可以减少不适当地引入源极区域和漏极区域的卤素离子注入区域中的掺杂剂，然后卤素离子注入区域和源极/漏极区域的掺杂剂区域之间的重叠可以减小，从而降低MOSFET中的带带漏电流，从而提高器件的性能。

99. 发明授权

US07897468B1 Device having self-aligned double gate formed by backside engineering, and device having super-steep retrograded island 有权
标题翻译：具有通过背面工程形成的自对准双门的装置，以及具有超陡峭退化岛的装置
公开(公告)号：US07897468B1
公开(公告)日：2011-03-01
申请号：US12556604
申请日：2009-09-10
申请人： Zhijiong Luo , Qingqing Liang , Haizhou Yin , Huilong Zhu
发明人： Zhijiong Luo , Qingqing Liang , Haizhou Yin , Huilong Zhu
IPC分类号： H01L21/336
CPC分类号： H01L29/7833 , H01L29/1083 , H01L29/165 , H01L29/66484 , H01L29/6659 , H01L29/66636 , H01L29/66742 , H01L29/7831 , H01L29/78648
摘要： A method of forming a dual gate semiconductor device is provided that includes providing a substrate having a first semiconductor layer and a second semiconductor layer, in which a first gate structure is formed on the second semiconductor layer. The second semiconductor layer and the first semiconductor layer are etched to expose the substrate using the first gate structure as an etch mask. A remaining portion of the first semiconductor layer is present underlying the first gate structure having edges aligned to the edges of the first gate structure. An epitaxial semiconductor material is formed on exposed portions of the substrate. The substrate and the remaining portion of the first semiconductor layer are removed to provide a recess having edges aligned to the edges of the first gate structure, and a second gate structure is formed in the recess. A method of forming a retrograded island is also provided.
摘要翻译：提供一种形成双栅极半导体器件的方法，其包括提供具有第一半导体层和第二半导体层的衬底，其中在第二半导体层上形成第一栅极结构。蚀刻第二半导体层和第一半导体层以使用第一栅极结构作为蚀刻掩模来露出衬底。第一半导体层的剩余部分位于具有与第一栅极结构的边缘对准的边缘的第一栅极结构下方。在衬底的暴露部分上形成外延半导体材料。去除衬底和第一半导体层的剩余部分以提供具有与第一栅极结构的边缘对准的边缘的凹部，并且在凹部中形成第二栅极结构。还提供了形成退火岛的方法。

100. 发明授权

US09373722B2 Semiconductor structure and method for manufacturing the same 有权
标题翻译：半导体结构及其制造方法
公开(公告)号：US09373722B2
公开(公告)日：2016-06-21
申请号：US14395076
申请日：2012-05-10
申请人： Haizhou Yin , Huilong Zhu , Zhijiong Luo
发明人： Haizhou Yin , Huilong Zhu , Zhijiong Luo
IPC分类号： H01L29/78 , H01L21/266 , H01L29/06 , H01L29/16 , H01L29/161 , H01L29/66 , H01L21/84 , H01L27/12 , H01L21/265 , H01L29/165
CPC分类号： H01L29/785 , H01L21/26586 , H01L21/266 , H01L21/84 , H01L27/1203 , H01L29/0649 , H01L29/16 , H01L29/161 , H01L29/165 , H01L29/6656 , H01L29/66795 , H01L29/7842 , H01L29/7843 , H01L29/7848 , H01L29/7849
摘要： The present invention provides a semiconductor structure comprising: a semiconductor base located on an insulating layer, wherein the insulating layer is located on a semiconductor substrate; source/drain regions, which are in contact with first sidewalls of the semiconductor base opposite to each other; gates located on second sidewalls of the semiconductor base opposite to each other; an insulating via located on the insulating layer and embedded into the semiconductor base; and an epitaxial layer sandwiched between the insulating via and the semiconductor base. The present invention further provides a method for manufacturing a semiconductor structure comprising: forming an insulating layer on a semiconductor substrate; forming a semiconductor base on the insulating layer; forming a void within the semiconductor base, wherein the void exposes the semiconductor substrate; forming an epitaxial layer in the void through selective epitaxy; and forming an insulating via within the void. Short-channel effects are significantly suppressed through forming super-steep retrograde well (SSRW).
摘要翻译：本发明提供一种半导体结构，包括：位于绝缘层上的半导体基底，其中所述绝缘层位于半导体衬底上; 源极/漏极区域，其与半导体基板的彼此相对的第一侧壁接触; 位于半导体基板的彼此相对的第二侧壁上的门; 位于绝缘层上并嵌入到半导体基底中的绝缘通孔; 以及夹在绝缘通孔和半导体基底之间的外延层。本发明还提供一种用于制造半导体结构的方法，包括：在半导体衬底上形成绝缘层; 在绝缘层上形成半导体基底; 在所述半导体基底内形成空隙，其中所述空隙暴露所述半导体衬底; 通过选择性外延在空隙中形成外延层; 并在空隙内形成绝缘通孔。通过形成超陡逆行井（SSRW），短通道效应被显着抑制。

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