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91. 发明授权

US08866301B2 Package systems having interposers with interconnection structures 有权
标题翻译：具有互连结构的插入器的封装系统
公开(公告)号：US08866301B2
公开(公告)日：2014-10-21
申请号：US12781960
申请日：2010-05-18
申请人： Yung-Chi Lin , Jing-Cheng Lin , Chen-Hua Yu
发明人： Yung-Chi Lin , Jing-Cheng Lin , Chen-Hua Yu
IPC分类号： H01L23/48 , H01L23/52 , H01L29/40 , H01L23/02 , H01L23/498 , H01L23/538 , H01L23/00 , H01L23/31 , H01L21/56 , H01L23/29 , H01L21/48
CPC分类号： H01L21/4857 , H01L21/4846 , H01L21/4853 , H01L21/486 , H01L21/56 , H01L21/563 , H01L21/565 , H01L21/6835 , H01L21/768 , H01L23/295 , H01L23/3128 , H01L23/49816 , H01L23/49822 , H01L23/49827 , H01L23/5389 , H01L24/03 , H01L24/11 , H01L24/19 , H01L24/24 , H01L25/0657 , H01L25/50 , H01L2221/68359 , H01L2224/02331 , H01L2224/02372 , H01L2224/0239 , H01L2224/0401 , H01L2224/12105 , H01L2224/16225 , H01L2224/24227 , H01L2224/32225 , H01L2224/73203 , H01L2224/73204 , H01L2225/06517 , H01L2225/06548 , H01L2225/06572 , H01L2924/01006 , H01L2924/01013 , H01L2924/01019 , H01L2924/0102 , H01L2924/01023 , H01L2924/01024 , H01L2924/01029 , H01L2924/01032 , H01L2924/01033 , H01L2924/01047 , H01L2924/01049 , H01L2924/01059 , H01L2924/01073 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01327 , H01L2924/10253 , H01L2924/10329 , H01L2924/12042 , H01L2924/1305 , H01L2924/13091 , H01L2924/14 , H01L2924/15192 , H01L2924/15311 , H01L2924/15788 , H01L2924/181 , H01L2924/00012 , H01L2924/00
摘要： A package system includes a first integrated circuit disposed over an interposer. The interposer includes at least one molding compound layer including a plurality of electrical connection structures through the at least one molding compound layer. A first interconnect structure is disposed over a first surface of the at least one molding compound layer and electrically coupled with the plurality of electrical connection structures. The first integrated circuit is electrically coupled with the first interconnect structure.
摘要翻译：封装系统包括设置在插入器上的第一集成电路。所述插入器包括至少一个包含穿过所述至少一个模塑复合层的多个电连接结构的模塑复合层。第一互连结构设置在至少一个模塑复合层的第一表面上并与多个电连接结构电耦合。第一集成电路与第一互连结构电耦合。

92. 发明授权

US08455995B2 TSVs with different sizes in interposers for bonding dies 有权
标题翻译：用于焊接模具的插入件中具有不同尺寸的TSV
公开(公告)号：US08455995B2
公开(公告)日：2013-06-04
申请号：US12762085
申请日：2010-04-16
申请人： Po-Hao Tsai , Jing-Cheng Lin , Chen-Hua Yu
发明人： Po-Hao Tsai , Jing-Cheng Lin , Chen-Hua Yu
IPC分类号： H01L23/04
CPC分类号： H01L23/3121 , H01L21/486 , H01L21/568 , H01L21/6835 , H01L21/6836 , H01L21/76898 , H01L23/13 , H01L23/147 , H01L23/481 , H01L23/49822 , H01L23/49827 , H01L24/13 , H01L24/16 , H01L24/73 , H01L24/81 , H01L25/0652 , H01L25/0655 , H01L25/0657 , H01L25/50 , H01L2221/68327 , H01L2221/68381 , H01L2224/13124 , H01L2224/13139 , H01L2224/13144 , H01L2224/13147 , H01L2224/13155 , H01L2224/13184 , H01L2224/16225 , H01L2224/16227 , H01L2224/16235 , H01L2224/73204 , H01L2224/81411 , H01L2224/81444 , H01L2224/81455 , H01L2224/81464 , H01L2225/06517 , H01L2225/06548 , H01L2924/00011 , H01L2924/01322 , H01L2924/14 , H01L2924/15153 , H01L2924/15192 , H01L2924/15311 , H01L2924/15321 , H01L2924/00 , H01L2224/81805
摘要： A device includes an interposer including a substrate having a top surface and a bottom surface. A plurality of through-substrate vias (TSVs) penetrates through the substrate. The plurality of TSVs includes a first TSV having a first length and a first horizontal dimension, and a second TSV having a second length different from the first length, and a second horizontal dimension different from the first horizontal dimension. An interconnect structure is formed overlying the top surface of the substrate and electrically coupled to the plurality of TSVs.
摘要翻译：一种器件包括具有顶表面和底表面的衬底的插入器。多个穿通基板通孔（TSV）穿过基板。多个TSV包括具有第一长度和第一水平尺寸的第一TSV和具有不同于第一长度的第二长度的第二TSV和与第一水平尺寸不同的第二水平尺寸。互连结构形成在衬底的顶表面上并电耦合到多个TSV。

93. 发明授权

US08361895B2 Ultra-shallow junctions using atomic-layer doping 有权
标题翻译：使用原子层掺杂的超浅结
公开(公告)号：US08361895B2
公开(公告)日：2013-01-29
申请号：US12211464
申请日：2008-09-16
申请人： Jing-Cheng Lin , Chen-Hua Yu
发明人： Jing-Cheng Lin , Chen-Hua Yu
IPC分类号： H01L21/22 , H01L21/38
CPC分类号： H01L29/66636 , H01L21/2254 , H01L21/324 , H01L21/823814 , H01L29/165 , H01L29/49 , H01L29/517 , H01L29/6653 , H01L29/6659 , H01L29/7833 , H01L29/7843 , H01L29/7848
摘要： A semiconductor device and a method of manufacturing are provided. A substrate has a gate stack formed thereon. Ultra-shallow junctions are formed by depositing an atomic layer of a dopant and performing an anneal to diffuse the dopant into the substrate on opposing sides of the gate stack. The substrate may be recessed prior to forming the atomic layer and the recess may be filled by an epitaxial process. The depositing, annealing, and, if used, epitaxial growth may be repeated a plurality of times to achieve the desired junctions. Source/drain regions are also provided on opposing sides of the gate stack.
摘要翻译：提供半导体器件和制造方法。基板上形成有栅叠层。通过沉积掺杂剂的原子层并执行退火来形成超浅结，以将掺杂剂扩散到栅叠层的相对侧上的衬底中。衬底可以在形成原子层之前被凹入，并且凹槽可以通过外延工艺填充。可以重复沉积，退火和（如果使用）外延生长以实现所需的结。源极/漏极区域也设置在栅极堆叠的相对侧上。

94. 发明申请

US20110018069A1 Depletion-Free MOS using Atomic-Layer Doping 有权
标题翻译：消耗MOS的原子层掺杂
公开(公告)号：US20110018069A1
公开(公告)日：2011-01-27
申请号：US12854638
申请日：2010-08-11
申请人： Jing-Cheng Lin , Chen-Hua Yu
发明人： Jing-Cheng Lin , Chen-Hua Yu
IPC分类号： H01L27/092
CPC分类号： H01L21/823842 , H01L21/2254 , H01L21/28035 , H01L29/4925 , H01L29/6659
摘要： A semiconductor device and a method of manufacturing are provided. A dielectric layer is formed over a substrate, and a first silicon-containing layer, undoped, is formed over the dielectric layer. Atomic-layer doping is used to dope the undoped silicon-containing layer. A second silicon-containing layer is formed over first silicon-containing layer. The process may be expanded to include forming a PMOS and NMOS device on the same wafer. For example, the first silicon-containing layer may be thinned in the PMOS region prior to the atomic-layer doping. In the NMOS region, the doped portion of the first silicon-containing layer is removed such that the remaining portion of the first silicon-containing layer in the NMOS is undoped. Thereafter, another atomic-layer doping process may be used to dope the first silicon-containing layer in the NMOS region to a different conductivity type. A third silicon-containing layer may be formed doped to the respective conductivity type.
摘要翻译：提供半导体器件和制造方法。介电层形成在衬底上，并且在介电层上形成未掺杂的第一含硅层。原子层掺杂用于掺杂未掺杂的含硅层。在第一含硅层上形成第二含硅层。该过程可以扩展到包括在同一晶片上形成PMOS和NMOS器件。例如，在原子层掺杂之前，第一含硅层可以在PMOS区中减薄。在NMOS区域中，去除第一含硅层的掺杂部分，使得NMOS中的第一含硅层的剩余部分未掺杂。此后，可以使用另一种原子层掺杂工艺将NMOS区域中的第一含硅层掺杂到不同的导电类型。可以形成掺杂到相应导电类型的第三含硅层。

95. 发明申请

US20100289116A1 Selective Epitaxial Growth of Semiconductor Materials with Reduced Defects 有权
标题翻译：具有减少缺陷的半导体材料的选择性外延生长
公开(公告)号：US20100289116A1
公开(公告)日：2010-11-18
申请号：US12708711
申请日：2010-02-19
申请人： Jing-Cheng Lin , Chen-Hua Yu
发明人： Jing-Cheng Lin , Chen-Hua Yu
IPC分类号： H01L29/06
CPC分类号： H01L21/02494 , H01L21/02381 , H01L21/0245 , H01L21/02455 , H01L21/02532 , H01L21/02538 , H01L21/02587 , H01L21/02639 , H01L21/76224 , H01L29/165 , H01L29/267
摘要： A semiconductor device includes a substrate formed of a first semiconductor material; two insulators on the substrate; and a semiconductor region having a portion between the two insulators and over the substrate. The semiconductor region has a bottom surface contacting the substrate and having sloped sidewalls. The semiconductor region is formed of a second semiconductor material different from the first semiconductor material.
摘要翻译：半导体器件包括由第一半导体材料形成的衬底; 基板上有两个绝缘子; 以及半导体区域，其具有在所述两个绝缘体之间并且在所述衬底上的部分。半导体区域具有与衬底接触并具有倾斜侧壁的底表面。半导体区域由与第一半导体材料不同的第二半导体材料形成。

96. 发明申请

US20140011301A1 System and Method for Through Silicon Via Yield 有权
标题翻译：通过产量的硅的系统和方法
公开(公告)号：US20140011301A1
公开(公告)日：2014-01-09
申请号：US13542896
申请日：2012-07-06
申请人： Chien Rhone Wang , Kewei Zuo , Chen-Hua Yu , Jing-Cheng Lin , Yen-Hsin Liu
发明人： Chien Rhone Wang , Kewei Zuo , Chen-Hua Yu , Jing-Cheng Lin , Yen-Hsin Liu
IPC分类号： H01L21/66 , G06F19/00
CPC分类号： H01L22/20 , H01L21/76898 , H01L22/12
摘要： The present disclosure provides one embodiment of an integrated circuit (IC) fabrication method to form an IC structure having one or more through silicon via (TSV) features. The IC fabrication method includes performing a plurality of processing steps; collecting physical metrology data from the plurality of processing steps; collecting virtual metrology data from the plurality of processing steps based on the physical metrology data; generating a yield prediction to the IC structure based on the physical metrology data and the virtual metrology data; and identifying an action at an earlier processing step based on the yield prediction.
摘要翻译：本公开提供了用于形成具有一个或多个贯穿硅通孔（TSV）特征的IC结构的集成电路（IC）制造方法的一个实施例。 IC制作方法包括执行多个处理步骤; 从多个处理步骤收集物理计量数据; 基于所述物理测量数据从所述多个处理步骤收集虚拟测量数据; 基于物理测量数据和虚拟测量数据，为IC结构生成产量预测; 以及基于所述产量预测在较早的处理步骤识别动作。

97. 发明授权

US08411459B2 Interposer-on-glass package structures 有权
标题翻译：内置玻璃封装结构
公开(公告)号：US08411459B2
公开(公告)日：2013-04-02
申请号：US12834943
申请日：2010-07-13
申请人： Chen-Hua Yu , Jing-Cheng Lin
发明人： Chen-Hua Yu , Jing-Cheng Lin
IPC分类号： H05K7/00 , H05K1/16
CPC分类号： H01L21/76898 , H01L23/13 , H01L23/147 , H01L23/15 , H01L23/49816 , H01L23/49827 , H01L23/5384 , H01L23/5385 , H01L23/5389 , H01L25/03 , H01L25/0657 , H01L2224/16225 , H01L2224/16227 , H01L2225/06517 , H01L2225/06548 , H01L2225/06572 , H01L2924/00014 , H01L2924/15311 , H01L2924/15321 , Y10T29/49124 , Y10T29/49165 , H01L2224/0401
摘要： A device includes an interposer including a substrate, and a first through-substrate via (TSV) penetrating through the substrate. A glass substrate is bonded to the interposer through a fusion bonding. The glass substrate includes a second TSV therein and electrically coupled to the first TSV.
摘要翻译：一种器件包括内插器，其包括衬底和穿透衬底的第一穿透衬底通孔（TSV）。玻璃基板通过熔接结合到插入件上。玻璃基板在其中包括第二TSV并且电耦合到第一TSV。

98. 发明申请

US20120098123A1 Molded Chip Interposer Structure and Methods 有权
标题翻译：成型芯片内插器结构与方法
公开(公告)号：US20120098123A1
公开(公告)日：2012-04-26
申请号：US12953130
申请日：2010-11-23
申请人： Chen-Hua Yu , Chun Hui Yu , Jing-Cheng Lin
发明人： Chen-Hua Yu , Chun Hui Yu , Jing-Cheng Lin
IPC分类号： H01L23/498
CPC分类号： H01L25/0655 , H01L21/563 , H01L21/568 , H01L23/3157 , H01L23/36 , H01L23/42 , H01L23/49822 , H01L23/49827 , H01L24/81 , H01L24/96 , H01L24/97 , H01L2224/04105 , H01L2224/12105 , H01L2224/16225 , H01L2224/16237 , H01L2224/32225 , H01L2224/73204 , H01L2224/97 , H01L2924/00011 , H01L2924/01029 , H01L2924/01322 , H01L2924/09701 , H01L2924/14 , H01L2924/181 , H01L2924/351 , H01L2924/00 , H01L2224/81 , H01L2224/83 , H01L2224/81805
摘要： Apparatus and methods for providing a molded chip interposer structure and assembly. A molded chip structure having at least two integrated circuit dies disposed within a mold compound is provided having the die bond pads on the bottom surface; and solder bumps are formed in the openings of a dielectric layer on the bottom surface, the solder bumps forming connections to the bond pads. An interposer having a die side surface and a board side surface is provided having bump lands receiving the solder bumps of the molded chip structure on the die side of the interposer. An underfill layer is formed between the die side of the interposer and the bottom surface of the molded chip structure surrounding the solder bumps. Methods for forming the molded chip interposer structure are disclosed.
摘要翻译：用于提供模制芯片插入件结构和组装的装置和方法。提供具有设置在模具化合物内的至少两个集成电路管芯的模制芯片结构，其具有底表面上的管芯接合焊盘; 并且在底表面上的电介质层的开口中形成焊料凸块，焊料凸块形成与焊盘的连接。具有裸片侧表面和电路板侧表面的插入件设置有凸起焊盘，其在插入件的裸片侧接收模制芯片结构的焊料凸块。在插入件的裸片侧和围绕焊料凸块的模制芯片结构的底表面之间形成底部填充层。公开了用于形成模制芯片内插器结构的方法。

99. 发明申请

US20100155790A1 N-FET with a Highly Doped Source/Drain and Strain Booster 有权
标题翻译：具有高掺杂源/漏极和应变增强器的N-FET
公开(公告)号：US20100155790A1
公开(公告)日：2010-06-24
申请号：US12341674
申请日：2008-12-22
申请人： Jing-Cheng Lin , Chen-Hua Yu
发明人： Jing-Cheng Lin , Chen-Hua Yu
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/7848 , H01L21/26586 , H01L21/28255 , H01L29/51 , H01L29/66477 , H01L29/7833
摘要： A structure and method of making an N-FET with a highly doped source/drain and strain booster are presented. The method provides a substrate with a Ge channel region. A gate dielectric is formed over the Ge channel and a gate electrode is formed over the gate dielectric. Sacrificial gate spacers are disposed on the sidewalls of the gate dielectric and gate electrode. Cavities are etched into the substrate extending under the sacrificial gate spacers. Si1−xGex source/drain regions are doped in-situ during formation, x
摘要翻译：提出了制造具有高掺杂源/漏和应变增强器的N-FET的结构和方法。该方法提供具有Ge沟道区的衬底。在Ge沟道上方形成栅极电介质，在栅极电介质上形成栅电极。牺牲栅间隔件设置在栅极电介质和栅电极的侧壁上。凹坑被蚀刻到在牺牲栅极间隔物下面延伸的衬底中。 Si1-xGex源/漏区在形成期间原位掺杂，x <0.85。

100. 发明授权

US07250683B2 Method to solve via poisoning for porous low-k dielectric 有权
标题翻译：解决多孔低介电常数中毒的方法
公开(公告)号：US07250683B2
公开(公告)日：2007-07-31
申请号：US11056758
申请日：2005-02-11
申请人： Ming-Hsing Tsai , Jing-Cheng Lin , Shau-Lin Shue , Chen-Hua Yu
发明人： Ming-Hsing Tsai , Jing-Cheng Lin , Shau-Lin Shue , Chen-Hua Yu
IPC分类号： H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L21/76844 , H01L21/76807 , H01L21/76831 , H01L2221/1063
摘要： A method of forming a via in a low-k dielectric material and without the attendant via poisoning problem, or a dual damascene structure formed in the same dielectric and without the same problem are disclosed. The vertical walls of the via opening are first lined with a low-k protection layer and then covered with a barrier layer in order to prevent outgassing from the low-k dielectric material when copper is deposited into the via opening. In the case of a dual damascene structure, it is sufficient that the hole opening underlying the trench opening is first lined with the low-k protection layer. The resulting via or dual damascene structure is free of poisoned metal and, therefore, more reliable.
摘要翻译：公开了一种在低k电介质材料中形成通孔并且不伴随通过中毒问题的方法，或者形成在相同电介质中并且没有相同问题的双镶嵌结构。通孔开口的垂直壁首先衬有低k保护层，然后被阻挡层覆盖，以便当铜沉积到通孔中时，防止从低k电介质材料脱气。在双镶嵌结构的情况下，沟槽开口下方的开孔首先衬有低k保护层就足够了。所得到的通孔或双镶嵌结构没有中毒金属，因此更可靠。

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