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91. 发明授权

US08384601B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US08384601B2
公开(公告)日：2013-02-26
申请号：US13361988
申请日：2012-01-31
申请人： Kazuya Hanaoka , Hideto Ohnuma , Teruyuki Fujii
发明人： Kazuya Hanaoka , Hideto Ohnuma , Teruyuki Fujii
IPC分类号： H01Q1/38
CPC分类号： H01Q1/2208 , H01Q9/0407 , H01Q23/00
摘要： An object of the present invention is to prevent electrical characteristics of circuit elements from being adversely affected by copper diffusion in a semiconductor device having an integrated circuit and an antenna formed over one substrate, which uses copper plating for the antenna. Another object is to prevent a defect of a semiconductor device due to poor connection between an antenna and an integrated circuit in a semiconductor device having the integrated circuit and the antenna formed over one substrate. In a semiconductor device having an integrated circuit 100 and an antenna 101 formed over one substrate 102, when a copper plating layer 108 is used for a conductor of the antenna 101, it is possible to decrease an adverse effect on electrical characteristics of circuit elements due to copper diffusion because a base layer 107 of the antenna 101 uses a nitride film of a predetermined metal.
摘要翻译：本发明的目的是为了防止在具有集成电路的半导体器件中的电路元件的电气特性受到不利影响，并且在一个衬底上形成天线，该衬底使用用于天线的铜电镀。另一个目的是防止在具有集成电路的半导体器件中的天线与集成电路之间的不良连接导致半导体器件的缺陷，并且形成在一个衬底上的天线。在具有集成电路100和在一个基板102上形成的天线101的半导体器件中，当将铜镀层108用于天线101的导体时，可以减少对电路元件的电特性的不利影响，由于天线101的基极层107使用预定金属的氮化物膜而导致铜扩散。

92. 发明授权

US08293626B2 Method for manufacturing semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US08293626B2
公开(公告)日：2012-10-23
申请号：US12552493
申请日：2009-09-02
申请人： Hideto Ohnuma , Naoki Okuno
发明人： Hideto Ohnuma , Naoki Okuno
IPC分类号： H01L21/00
CPC分类号： H01L27/1274 , H01L21/02422 , H01L21/02532 , H01L21/67115 , H01L27/1214 , H01L27/1218 , H01L29/04 , H01L29/42384 , H01L29/4908
摘要： It is an object to provide a homogeneous semiconductor film in which variation in the size of crystal grains is reduced. Alternatively, it is an object to provide a homogeneous semiconductor film and to achieve cost reduction. By introducing a glass substrate over which an amorphous semiconductor film is formed into a treatment atmosphere set at more than or equal to a temperature that is needed for crystallization, rapid heating due to heat conduction from the treatment atmosphere is performed so that the amorphous semiconductor film is crystallized. More specifically, for example, after the temperature of the treatment atmosphere is increased in advance to a temperature that is needed for crystallization, the substrate over which the semiconductor film is formed is put into the treatment atmosphere.
摘要翻译：本发明的目的是提供一种均匀的半导体膜，其中晶粒尺寸的变化减小。或者，目的是提供均匀的半导体膜并实现成本降低。通过将形成非晶半导体膜的玻璃基板导入设定为结晶所需温度以上的处理气氛，进行由于来自处理气氛的热传导而引起的快速加热，使得非晶半导体膜结晶。更具体地，例如，在将处理气氛的温度预先提高到结晶所需的温度之后，将形成有半导体膜的基板投入处理气氛。

93. 发明授权

US08283669B2 Semiconductor device and method of manufacturing same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US08283669B2
公开(公告)日：2012-10-09
申请号：US12963883
申请日：2010-12-09
申请人： Hideto Ohnuma
发明人： Hideto Ohnuma
IPC分类号： H01L29/04
CPC分类号： H01L27/1266 , H01L27/1214 , H01L27/13 , H01L29/0657 , H01L29/66757 , H01L29/78609 , H01L29/78621 , H01L29/78675
摘要： An object is to reduce the adverse influence which a portion of a gate insulating layer where the thickness has decreased, that is, a step portion, has on semiconductor element characteristics so that the reliability of the semiconductor element is improved. A semiconductor layer is formed over an insulating surface; a side surface of the semiconductor layer is oxidized using wet oxidation to form a first insulating layer; a second insulating layer is formed over the semiconductor layer and the first insulating layer; and a gate electrode is formed over the semiconductor layer and the first insulating layer with the second insulating layer interposed therebetween.
摘要翻译：本发明的目的是减少栅极绝缘层的厚度减小的部分（即阶梯部分）对半导体元件特性的不良影响，从而提高半导体元件的可靠性。在绝缘表面上形成半导体层; 半导体层的侧表面被湿氧化氧化以形成第一绝缘层; 在半导体层和第一绝缘层上形成第二绝缘层; 并且在所述半导体层和所述第一绝缘层之间形成有栅电极，其间插入有所述第二绝缘层。

94. 发明授权

US08263476B2 Manufacturing method of SOI substrate 有权
标题翻译： SOI衬底的制造方法
公开(公告)号：US08263476B2
公开(公告)日：2012-09-11
申请号：US12176617
申请日：2008-07-21
申请人： Hideto Ohnuma
发明人： Hideto Ohnuma
IPC分类号： H01L21/30
CPC分类号： H01L29/78603 , H01L21/76254 , H01L27/1266 , H01L29/42384 , H01L29/78621
摘要： A manufacturing method of an SOI substrate with high throughput. A semiconductor layer separated from a semiconductor substrate is transferred to a supporting substrate, thereby manufacturing an SOI substrate. First, the semiconductor substrate serving as a base of the semiconductor layer is prepared. An embrittlement layer is formed in a region at a predetermined depth of the semiconductor substrate, and an insulating layer is formed on a surface of the semiconductor substrate. After bonding the semiconductor substrate and a supporting substrate with the insulating layer interposed therebetween, the semiconductor substrate is selectively irradiated with a laser beam; accordingly, embrittlement of the embrittlement layer progresses. Then, using a physical method or heat treatment, the semiconductor substrate is separated; at that time, the region where the embrittlement has progressed in the embrittlement layer serves as a starting point.
摘要翻译：具有高通量的SOI衬底的制造方法。将从半导体衬底分离的半导体层转移到支撑衬底，从而制造SOI衬底。首先，制备用作半导体层的基底的半导体衬底。在半导体衬底的预定深度的区域中形成脆化层，并且在半导体衬底的表面上形成绝缘层。在将半导体衬底和支撑衬底与绝缘层接合之后，用激光束选择性地照射半导体衬底; 因此，脆化层的脆化进行。然后，使用物理方法或热处理，分离半导体衬底; 此时，在脆化层中脆化进行的区域作为起点。

95. 发明申请

US20120202331A1 MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件的制造方法
公开(公告)号：US20120202331A1
公开(公告)日：2012-08-09
申请号：US13449383
申请日：2012-04-18
申请人： Hideto Ohnuma , Masayuki Sakakura
发明人： Hideto Ohnuma , Masayuki Sakakura
IPC分类号： H01L21/336
CPC分类号： H01L27/127 , H01L21/0273 , H01L27/1214 , H01L27/124 , H01L27/1255 , H01L27/1288 , H01L27/3244 , H01L27/3276 , H01L51/5237 , H01L51/5246 , H01L51/5259
摘要： The invention provides a technique to manufacture a highly reliable semiconductor device and a display device at high yield. As an exposure mask, an exposure mask provided with a diffraction grating pattern or an auxiliary pattern formed of a semi-transmissive film with a light intensity reducing function is used. With such an exposure mask, various light exposures can be more accurately controlled, which enables a resist to be processed into a more accurate shape. Therefore, when such a mask layer is used, the conductive film and the insulating film can be processed in the same step into different shapes in accordance with desired performances. As a result, thin film transistors with different characteristics, wires in different sizes and shapes, and the like can be manufactured without increasing the number of steps.
摘要翻译：本发明提供了以高产率制造高度可靠的半导体器件和显示器件的技术。作为曝光掩模，使用设置有衍射光栅图案的曝光掩模或由具有光强度降低功能的半透射膜形成的辅助图案。通过这种曝光掩模，可以更精确地控制各种光照射，这使得抗蚀剂能够被加工成更准确的形状。因此，当使用这种掩模层时，导电膜和绝缘膜可以根据期望的性能在同一步骤中被加工成不同的形状。结果，可以在不增加步数的情况下制造具有不同特性的薄膜晶体管，不同尺寸和形状的导线等。

96. 发明授权

US08233203B2 Exposure method and method of manufacturing semiconductor device 有权
标题翻译：半导体器件的制造方法及制造方法
公开(公告)号：US08233203B2
公开(公告)日：2012-07-31
申请号：US11705049
申请日：2007-02-12
申请人： Hideto Ohnuma
发明人： Hideto Ohnuma
IPC分类号： G03H1/20 , G03H1/22 , G02B5/32 , G02B27/54
CPC分类号： G03F7/70375 , G03H1/0408 , G03H2001/0094 , G03H2001/2289 , G03H2222/56
摘要： The exposure method includes the steps of: illuminating a hologram recording medium, in which a hologram with a first pattern has been recorded by illumination with a laser beam emitted from a first laser oscillator, with a laser beam emitted from a second laser oscillator; and delivering the laser beam emitted from the second laser oscillator, which has passed through the hologram recording medium, onto a resist, thereby forming a second pattern in the resist. The wavelength of the laser beam used for illuminating the resist through the hologram recording medium in which the hologram is recorded is shorter than the wavelength of the laser beam used for recording the hologram in the hologram recording medium. Further, the wavelength of the laser beam used for illuminating the resist is 1/(0.5×n) (where n is an integer not less than 3) that of the laser beam used for recording the hologram.
摘要翻译：曝光方法包括以下步骤：利用从第二激光振荡器发射的激光束照射已经通过用从第一激光振荡器发射的激光照明的第一图案的全息图照射的全息图记录介质; 以及将已经通过全息图记录介质的第二激光振荡器发射的激光束传送到抗蚀剂上，从而在抗蚀剂中形成第二图案。用于通过其中记录全息图的全息图记录介质照射抗蚀剂的激光束的波长短于用于在全息图记录介质中记录全息图的激光束的波长。此外，用于照射抗蚀剂的激光束的波长为用于记录全息图的激光束的波长为1 /（0.5×n）（其中n为不小于3的整数）。

97. 发明授权

US08198173B2 Method for manufacturing SOI substrate 有权
标题翻译：制造SOI衬底的方法
公开(公告)号：US08198173B2
公开(公告)日：2012-06-12
申请号：US12910320
申请日：2010-10-22
申请人： Hideto Ohnuma , Kenichiro Makino , Yoichi Iikubo , Masaharu Nagai , Aiko Shiga
发明人： Hideto Ohnuma , Kenichiro Makino , Yoichi Iikubo , Masaharu Nagai , Aiko Shiga
IPC分类号： H01L21/46
CPC分类号： H01L21/84 , H01L21/76254 , H01L29/66772 , H01L29/78621
摘要： To improve bonding strength and improve reliability of an SOI substrate in bonding a semiconductor substrate and a base substrate to each other even when an insulating film containing nitrogen is used as a bonding layer, an oxide film is provided on the semiconductor substrate side, a nitrogen-containing layer is provided on the base substrate side, and the oxide film formed on the semiconductor substrate and the nitrogen-containing layer formed over the base substrate are bonded to each other. Further, plasma treatment is performed on at least one of the oxide film and the nitrogen-containing layer before bonding the oxide film formed on the semiconductor substrate and the nitrogen-containing layer formed over the base substrate to each other. Plasma treatment can be performed in a state in which a bias voltage is applied.
摘要翻译：即使使用含有氮的绝缘膜作为接合层，为了提高接合强度并提高SOI基板的接合半导体基板和基板的可靠性，在半导体基板侧设置氧化膜，氮在基底基板侧设置含氧层，并且形成在半导体基板上的氧化膜和形成在基底基板上的含氮层彼此结合。此外，在将形成在半导体衬底上的氧化膜和形成在基底衬底上的含氮层彼此粘合之前，对氧化物膜和含氮层中的至少一种进行等离子体处理。可以在施加偏置电压的状态下进行等离子体处理。

98. 发明授权

US08173496B2 Method for manufacturing semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US08173496B2
公开(公告)日：2012-05-08
申请号：US13024360
申请日：2011-02-10
申请人： Sho Kato , Satoshi Toriumi , Fumito Isaka , Hideto Ohnuma
发明人： Sho Kato , Satoshi Toriumi , Fumito Isaka , Hideto Ohnuma
IPC分类号： H01L21/00 , H01L21/336 , H01L21/30
CPC分类号： H01L21/84 , H01L21/76251
摘要： A stack including at least an insulating layer, a first electrode, and a first impurity semiconductor layer is provided over a supporting substrate; a first semiconductor layer to which an impurity element imparting one conductivity type is added is formed over the first impurity semiconductor layer; a second semiconductor layer to which an impurity element imparting the one conductivity type is added is formed over the first semiconductor layer under a condition different from that of the first semiconductor layer; crystallinity of the first semiconductor layer and crystallinity of the second semiconductor layer are improved by a solid-phase growth method to form a second impurity semiconductor layer; an impurity element imparting the one conductivity type and an impurity element imparting a conductivity type different from the one conductivity type are added to the second impurity semiconductor layer; and a gate electrode layer is formed via a gate insulating layer.
摘要翻译：至少包括绝缘层，第一电极和第一杂质半导体层的叠层设置在支撑基板上; 在所述第一杂质半导体层上形成添加有赋予一种导电类型的杂质元素的第一半导体层; 在与第一半导体层不同的条件下，在第一半导体层上形成添加有赋予一种导电型的杂质元素的第二半导体层; 通过固相生长法提高第一半导体层的结晶度和第二半导体层的结晶度，形成第二杂质半导体层; 赋予一种导电类型的杂质元素和赋予不同于一种导电类型的导电类型的杂质元素添加到第二杂质半导体层; 并且经由栅极绝缘层形成栅极电极层。

99. 发明申请

US20110260165A1 Semiconductor Device and Method for Manufacturing Semiconductor Device 有权
标题翻译：半导体器件及半导体器件制造方法
公开(公告)号：US20110260165A1
公开(公告)日：2011-10-27
申请号：US13174952
申请日：2011-07-01
申请人： Hideto Ohnuma
发明人： Hideto Ohnuma
IPC分类号： H01L29/786 , H01L21/58
CPC分类号： H01L23/66 , H01L23/3121 , H01L23/3135 , H01L23/562 , H01L2223/6677 , H01L2924/0002 , H01L2924/00
摘要： An object is to provide a semiconductor device which is not easily broken even if stressed externally and a method for manufacturing such a semiconductor device. A semiconductor device includes an element layer including a transistor in which a channel is formed in a semiconductor layer and insulating layers which are formed as an upper layer and a lower layer of the transistor respectively, and a plurality of projecting members provided at intervals of from 2 to 200 μm on a surface of the element layer. The longitudinal elastic modulus of the material for forming the plurality of projecting members is lower than that of the materials of the insulating layers.
摘要翻译：目的在于提供即使在外部受到压力也不容易破碎的半导体装置及其制造方法。一种半导体器件包括：元件层，包括其中在半导体层中形成沟道的晶体管和分别形成为晶体管的上层和下层的绝缘层;以及多个突出构件，在元件层的表面上为2〜200μm。用于形成多个突出构件的材料的纵向弹性模量低于绝缘层材料的纵向弹性模量。

100. 发明授权

US08043902B2 Semiconductor device and manufacturing method thereof 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US08043902B2
公开(公告)日：2011-10-25
申请号：US12512075
申请日：2009-07-30
申请人： Hideto Ohnuma , Shigeharu Monoe , Shunpei Yamazaki
发明人： Hideto Ohnuma , Shigeharu Monoe , Shunpei Yamazaki
IPC分类号： H01L21/00
CPC分类号： H01L27/1214 , H01L27/124 , H01L27/1288 , H01L29/66757 , H01L29/78624
摘要： The present invention provides a TFT including at least one LDD region in a self-alignment manner without forming a sidewall spacer and increasing the number of manufacturing steps. A photomask or a reticle provided with an assist pattern that is formed of a diffraction grating pattern or a semi-transmitting film and has a function of reducing light intensity is employed in a photolithography step of forming a gate electrode, an asymmetrical resist pattern having a region with a thick thickness and a region with a thickness thinner than that of the above region on one side is formed, a gate electrode having a stepped portion is formed, and an LDD region is formed in a self-alignment manner by injecting an impurity element to the semiconductor layer through the region with a thin thickness of the gate electrode.
摘要翻译：本发明提供一种TFT，其以自对准方式提供至少一个LDD区域，而不形成侧壁间隔物并增加制造步骤的数量。在形成栅电极的光刻步骤中使用具有由衍射光栅图案或半透射膜形成的辅助图案并具有降低光强度的功能的光掩模或掩模版，具有形成厚度厚的区域和具有比一面上述区域的厚度薄的区域，形成具有台阶部分的栅电极，并且通过注入杂质以自对准方式形成LDD区域元件通过具有薄的栅电极厚度的区域到半导体层。

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