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91. 发明授权

US09213389B2 Non-volatile semiconductor memory device with power-saving feature 有权
标题翻译：具有省电功能的非易失性半导体存储器件
公开(公告)号：US09213389B2
公开(公告)日：2015-12-15
申请号：US13617908
申请日：2012-09-14
申请人： HakJune Oh
发明人： HakJune Oh
IPC分类号： G06F1/26 , G06F1/32 , G06F1/12 , G11C16/16 , G11C16/32
CPC分类号： G06F1/3203 , G06F1/12 , G06F1/3275 , G11C16/16 , G11C16/32 , Y02D10/14
摘要： A non-volatile semiconductor memory device, comprising: an interface for receiving commands issued by a controller, the commands including an erase command; a functional entity with circuit components and having a terminal; a node; switchable circuitry capable of controllably switching between a first operational state in which the terminal is electrically connected to the node and a second operational state in which the terminal is electrically decoupled from the node, the node being configured to have a signal for the functional entity communicated through it when the switchable circuitry is in the first operational state; and a command processing unit configured to recognize the commands issued by the controller and, in response to recognizing the erase command, to cause the switchable circuitry to switch from the first operational state to the second operational state.
摘要翻译：一种非易失性半导体存储器件，包括：用于接收由控制器发出的命令的接口，所述命令包括擦除命令; 具有电路组件并具有终端的功能实体; 一个节点能够在端子与节点电连接的第一操作状态和端子与节点电分离的第二操作状态之间可控地切换的可切换电路，该节点被配置为具有用于功能实体通信的信号当可切换电路处于第一操作状态时; 以及命令处理单元，其被配置为识别由所述控制器发出的命令，并且响应于识别所述擦除命令，使所述可切换电路从所述第一操作状态切换到所述第二操作状态。

92. 发明授权

US08825939B2 Semiconductor memory device suitable for interconnection in a ring topology 有权
标题翻译：适用于环形拓扑互连的半导体存储器件
公开(公告)号：US08825939B2
公开(公告)日：2014-09-02
申请号：US12141384
申请日：2008-06-18
申请人： HakJune Oh , Jin-Ki Kim
发明人： HakJune Oh , Jin-Ki Kim
IPC分类号： G06F12/00 , G11C8/00
CPC分类号： G11C16/10 , G06F13/4239 , G11C7/10 , G11C7/1003
摘要： A semiconductor memory device, which comprises: memory; a plurality of inputs for receiving a command latch enable signal, an address latch enable signal, an information signal and a select signal indicative of whether the memory device has been selected by a controller; a plurality of outputs for releasing a set of output signals towards a next device; control circuitry; and bypass circuitry. When the select signal is indicative of the memory device having been selected by the controller, the control circuitry is configured to interpret the information signal based on the command latch enable signal and the address latch enable signal. When the select signal is indicative of the memory device not having been selected by the controller, the bypass circuitry is configured to transfer the command latch enable signal, the address latch enable signal and the information signal to the outputs of the memory device.
摘要翻译：一种半导体存储器件，包括：存储器; 用于接收命令锁存使能信号，地址锁存使能信号，信息信号和指示存储器件是否被控制器选择的选择信号的多个输入; 多个输出，用于向下一个装置释放一组输出信号; 控制电路; 和旁路电路。当选择信号指示由控制器选择的存储器件时，控制电路被配置为基于命令锁存使能信号和地址锁存使能信号来解释信息信号。当选择信号指示存储器件未被控制器选择时，旁路电路被配置为将命令锁存使能信号，地址锁存使能信号和信息信号传送到存储器件的输出。

93. 发明申请

US20140198587A1 PRE-CHARGE VOLTAGE GENERATION AND POWER SAVING MODES 有权
标题翻译：预充电电压和节电模式
公开(公告)号：US20140198587A1
公开(公告)日：2014-07-17
申请号：US14216024
申请日：2014-03-17
申请人： Valerie Lines , HakJune Oh
发明人： Valerie Lines , HakJune Oh
IPC分类号： G11C5/14
CPC分类号： G11C5/148 , G11C5/147 , G11C7/1048 , G11C7/1078 , G11C7/1096 , G11C8/08 , G11C2207/2227
摘要： A system includes a voltage generator to produce a pre-charge voltage signal for pre-charging one or more signals in a memory circuit. The one or more signals can be data bus lines used to access memory. The voltage generator can include an input indicating whether the memory circuit is set to a power-saving mode. According to one embodiment, the input adjusts a magnitude of the pre-charge voltage signal produced by the voltage generator. Such an embodiment is useful over conventional methods because adjusting the pre-charge voltage can result in power savings. As an example, when in the power-saving mode, the voltage generator circuit can adjust the pre-charge voltage to a value that reduces an amount of leakage current associated with a pre-charge voltage. Reducing the leakage with respect to the pre-charge voltage means that the saved power can be used for other useful purposes.
摘要翻译：系统包括电压发生器，以产生用于对存储器电路中的一个或多个信号进行预充电的预充电电压信号。一个或多个信号可以是用于访问存储器的数据总线。电压发生器可以包括指示存储器电路是否被设置为省电模式的输入。根据一个实施例，输入调节由电压发生器产生的预充电电压信号的幅度。这种实施例对于常规方法是有用的，因为调节预充电电压可导致功率节省。例如，在省电模式下，电压发生器电路可以将预充电电压调整为减小与预充电电压相关联的漏电流量的值。减少相对于预充电电压的泄漏意味着所节省的功率可以用于其他有用的目的。

94. 发明授权

US08699288B2 Pre-charge voltage generation and power saving modes 有权
标题翻译：预充电电压和省电模式
公开(公告)号：US08699288B2
公开(公告)日：2014-04-15
申请号：US13599836
申请日：2012-08-30
申请人： Valerie Lines , HakJune Oh
发明人： Valerie Lines , HakJune Oh
IPC分类号： G11C7/00
CPC分类号： G11C5/148 , G11C5/147 , G11C7/1048 , G11C7/1078 , G11C7/1096 , G11C8/08 , G11C2207/2227
摘要： A system includes a voltage generator to produce a pre-charge voltage signal for pre-charging one or more signals in a memory circuit. The one or more signals can be data bus lines used to access memory. The voltage generator can include an input indicating whether the memory circuit is set to a power-saving mode. According to one embodiment, the input adjusts a magnitude of the pre-charge voltage signal produced by the voltage generator. Such an embodiment is useful over conventional methods because adjusting the pre-charge voltage can result in power savings. As an example, when in the power-saving mode, the voltage generator circuit can adjust the pre-charge voltage to a value that reduces an amount of leakage current associated with a pre-charge voltage. Reducing the leakage with respect to the pre-charge voltage means that the saved power can be used for other useful purposes.
摘要翻译：系统包括电压发生器，以产生用于对存储器电路中的一个或多个信号进行预充电的预充电电压信号。一个或多个信号可以是用于访问存储器的数据总线。电压发生器可以包括指示存储器电路是否被设置为省电模式的输入。根据一个实施例，输入调节由电压发生器产生的预充电电压信号的幅度。这种实施例对于常规方法是有用的，因为调节预充电电压可导致功率节省。例如，在省电模式下，电压发生器电路可以将预充电电压调整为减小与预充电电压相关联的漏电流量的值。减少相对于预充电电压的泄漏意味着所节省的功率可以用于其他有用的目的。

95. 发明授权

US08582382B2 Memory system having a plurality of serially connected devices 有权
标题翻译：存储器系统具有多个串行连接的设备
公开(公告)号：US08582382B2
公开(公告)日：2013-11-12
申请号：US12782911
申请日：2010-05-19
申请人： HakJune Oh
发明人： HakJune Oh
IPC分类号： G11C7/00
CPC分类号： G11C16/06 , G11C7/10 , G11C7/22 , G11C8/12 , G11C16/08 , G11C16/32
摘要： A semiconductor memory device and system are disclosed. The memory device includes a memory, a plurality of inputs, and a device identification register for storing register bits that distinguish the memory device from other possible memory devices. Circuitry for comparing identification bits in the information signal with the register bits provides positive or negative indication as to whether the identification bits match the register bits. If the indication is positive, then the memory device is configured to respond as having been selected by a controller. If the indication is negative, then the memory device is configured to respond as having not been selected by the controller. A plurality of outputs release a set of output signals towards a next device.
摘要翻译：公开了一种半导体存储器件和系统。存储器件包括存储器，多个输入端和用于存储将存储器件与其它可能存储器件区分开的寄存器位的器件识别寄存器。用于将信息信号中的标识位与寄存器位进行比较的电路提供关于标识位是否匹配寄存器位的正或负指示。如果指示为正，则存储器设备被配置为响应为由控制器选择。如果指示为负，则存储器设备被配置为响应为未被控制器选择。多个输出向一个下一个设备释放一组输出信号。

96. 发明授权

US08291248B2 Non-volatile semiconductor memory device with power saving feature 有权
标题翻译：具有省电功能的非易失性半导体存储器件
公开(公告)号：US08291248B2
公开(公告)日：2012-10-16
申请号：US12488278
申请日：2009-06-19
申请人： HakJune Oh
发明人： HakJune Oh
IPC分类号： G06F1/00
CPC分类号： G06F1/3203 , G06F1/12 , G06F1/3275 , G11C16/16 , G11C16/32 , Y02D10/14
摘要： A non-volatile semiconductor memory device, comprising: an interface for receiving commands issued by a controller, the commands including an erase command; a functional entity with circuit components and having a terminal; a node; switchable circuitry capable of controllably switching between a first operational state in which the terminal is electrically connected to the node and a second operational state in which the terminal is electrically decoupled from the node, the node being configured to have a signal for the functional entity communicated through it when the switchable circuitry is in the first operational state; and a command processing unit configured to recognize the commands issued by the controller and, in response to recognizing the erase command, to cause the switchable circuitry to switch from the first operational state to the second operational state.
摘要翻译：一种非易失性半导体存储器件，包括：用于接收由控制器发出的命令的接口，所述命令包括擦除命令; 具有电路组件并具有终端的功能实体; 一个节点能够在端子与节点电连接的第一操作状态和端子与节点电分离的第二操作状态之间可控地切换的可切换电路，该节点被配置为具有用于功能实体通信的信号当可切换电路处于第一操作状态时; 以及命令处理单元，其被配置为识别由所述控制器发出的命令，并且响应于识别所述擦除命令，使所述可切换电路从所述第一操作状态切换到所述第二操作状态。

97. 发明授权

US08200925B2 Data mirroring in serial-connected memory system 有权
标题翻译：串行存储系统中的数据镜像
公开(公告)号：US08200925B2
公开(公告)日：2012-06-12
申请号：US12399315
申请日：2009-03-06
申请人： HakJune Oh , William Petrie
发明人： HakJune Oh , William Petrie
IPC分类号： G06F12/00 , G06F3/00 , G06F13/00 , G11C29/00
CPC分类号： G11C7/1006 , G06F11/1044 , G11C29/74
摘要： A method of data mirroring in a serial-connected memory system between a first and a second memory device. A bypass command is issued to the first memory device, then a write data packet is provided to the first and second memory devices, and then a write data packet command is provided to the first and second memory devices by wherein the write data packet is passed to the second memory device through the first memory device. Mirroring of the write data packet into the first and second memory devices is thereby achieved. ECC (error correction codes) within spare fields provide means for recovering data after failure. The serial-connected memory system is especially useful for implementing SSD (solid-state disk) memory systems.
摘要翻译：一种在第一和第二存储器件之间的串联存储器系统中的数据镜像方法。向第一存储器件发出旁路命令，然后向第一和第二存储器件提供写入数据包，然后通过写入数据包被传递到第一和第二存储器装置来写入数据包命令通过第一存储器件到达第二存储器件。从而实现将写入数据包镜像到第一和第二存储器件中。备用字段内的ECC（纠错码）提供了在故障后恢复数据的方法。串行连接的存储器系统对于实现SSD（固态盘）存储器系统特别有用。

98. 发明授权

US08181056B2 Serial-connected memory system with output delay adjustment 有权
标题翻译：串行连接存储器系统，具有输出延迟调整功能
公开(公告)号：US08181056B2
公开(公告)日：2012-05-15
申请号：US12241832
申请日：2008-09-30
申请人： HakJune Oh
发明人： HakJune Oh
IPC分类号： G06F1/04 , H04L7/00
CPC分类号： G06F13/1689
摘要： Systems and methods for performing output delay adjustment are provided for application in serial-connected devices operating as slave devices. A master device provides a clock to the first slave device, and each slave device passes the clock to the next slave device in turn, and the last slave device returns the clock to the master device. The master device compares the outgoing clock to the returned clock and determines if an output delay adjustment is needed. If so, the master device generates and outputs commands for the slave devices to perform output delay adjustment. The slave devices apply the output delay to the clock signal, but may also apply the delay to other output signals. Each of the slave devices has a circuit for performing output delay adjustment. In some implementations, each slave device is a memory device, and the master device is a memory controller.
摘要翻译：提供用于执行输出延迟调整的系统和方法用于在作为从设备操作的串行连接设备中的应用。主设备向第一从设备提供时钟，并且每个从设备依次将时钟传递到下一个从设备，最后一个从设备将时钟返回给主设备。主设备将输出时钟与返回的时钟进行比较，并确定是否需要输出延迟调整。如果是，则主设备生成并输出从设备的命令以执行输出延迟调整。从器件将输出延迟施加到时钟信号，但也可以将延迟应用于其他输出信号。每个从设备具有用于执行输出延迟调整的电路。在一些实现中，每个从设备是存储设备，并且主设备是存储器控制器。

99. 发明授权

US08144528B2 Memory with data control 有权
标题翻译：带数据控制的内存
公开(公告)号：US08144528B2
公开(公告)日：2012-03-27
申请号：US12699627
申请日：2010-02-03
申请人： HakJune Oh
发明人： HakJune Oh
IPC分类号： G11C7/00
CPC分类号： G11C7/1078 , G11C7/109 , G11C7/22 , G11C16/102 , G11C2207/107 , G11C2216/30
摘要： In an embodiment, a memory device comprises memory, a first data link, a first input, a second input, a second data link, a first output and a second output. The first data link is configured to input one or more packets into the memory device. The first input is configured to input command strobe signals into the memory device that delineate command packets that are input into the memory device via the first data link. The second input is configured to input data strobe signals into the memory device that delineate data packets that are input into the memory device via the first data link. The first and second outputs are configured to output the command strobe signal and data strobe signal, respectively. The second data link is configured to output packets from the memory device.
摘要翻译：在一个实施例中，存储器件包括存储器，第一数据链路，第一输入，第二输入，第二数据链路，第一输出和第二输出。第一数据链路被配置为将一个或多个分组输入到存储器设备中。第一输入被配置为将命令选通信号输入到描绘经由第一数据链路输入存储器件的命令分组的存储器件中。第二输入被配置为将数据选通信号输入到通过第一数据链路描绘输入存储器件的数据分组的存储器件中。第一和第二输出分别被配置为输出命令选通信号和数据选通信号。第二数据链路被配置为从存储设备输出分组。

100. 发明授权

US07701753B2 Apparatus and method for self-refreshing dynamic random access memory cells 失效
标题翻译：用于自动刷新动态随机存取存储器单元的装置和方法
公开(公告)号：US07701753B2
公开(公告)日：2010-04-20
申请号：US12341316
申请日：2008-12-22
申请人： HakJune Oh
发明人： HakJune Oh
IPC分类号： G11C11/24
CPC分类号： G11C11/406 , G11C2211/4061
摘要： A dynamic random access memory (DRAM) having DRAM cells coupled to wordlines and bitlines. In a self-refresh mode, the cells coupled with the even numbered rows retain main data previously stored therein and the assistant data, which is logically opposite to the main data, is overwritten into the cells coupled with the wordlines of the odd numbered rows. When the DRAM enters the self-refresh mode, a starting refresh address for the self-refresh mode is detected. If the detected starting refresh address does not match with a predetermined correct address set for the self-refresh operation mode, a dummy refresh cycle will be established in an entry-burst self-refresh period. During the dummy refresh cycle, a dummy refresh command is added to increment an internal row address counter that provides row addresses for self-refreshing the cells of the selected wordlines within the cell array.
摘要翻译：具有耦合到字线和位线的DRAM单元的动态随机存取存储器（DRAM）。在自刷新模式中，与偶数行耦合的单元保留先前存储在其中的主数据，并且与主数据逻辑上相反的辅助数据被覆盖到与奇数行的字线耦合的单元中。当DRAM进入自刷新模式时，检测到用于自刷新模式的起始刷新地址。如果检测到的起始刷新地址与为自刷新操作模式设置的预定正确地址不匹配，则将在入口突发自刷新周期中建立虚拟刷新周期。在虚拟刷新周期期间，添加虚拟刷新命令以增加内部行地址计数器，该内部行地址计数器提供行地址以便自动刷新单元阵列内所选字线的单元。

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