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    • 93. 发明授权
    • EEPROM with bit lines below word lines
    • EEPROM位于字线下方的EEPROM
    • US5900661A
    • 1999-05-04
    • US931517
    • 1997-09-16
    • Yasuo Sato
    • Yasuo Sato
    • H01L21/8247H01L27/115H01L29/788G11C11/34
    • H01L27/11521H01L27/115
    • In a semiconductor device and a manufacturing method therefor, in a nonvolatile semiconductor memory such as an EEPROM having a floating gate, bit lines are formed under word lines to easily and properly realize bit contact, and a memory cell portion and a peripheral circuit portion are manufactured with good uniformity. In the memory cell portion of this nonvolatile semiconductor memory, a polysilicon film is patterned to form a gate counterelectrode and the bit lines substantially at the same level. The gate counterelectrode opposes a floating gate and is capacitively coupled to the floating gate with a dielectric film intervened therebetween on a field oxide film which is an element isolation structure. The word lines extend on an insulating film formed on the bit lines to cross the bit lines and are electrically connected to lower counterelectrodes. Therefore, the bit lines substantially exist under the word lines. The floating gate of the memory cell portion and the gate of the peripheral circuit portion, or the gate counterelectrode and the bit lines of the memory cell portion and the wiring layer of the peripheral circuit portion are simultaneously formed.
    • 在半导体装置及其制造方法中,在诸如具有浮动栅极的EEPROM的非易失性半导体存储器中,在字线下方形成位线以容易且适当地实现位接触,并且存储单元部分和外围电路部分 制造均匀性好。 在该非易失性半导体存储器的存储单元部分中,对多晶硅膜进行构图以形成栅极对电极,并且位线基本上处于相同的水平。 栅极对电极与浮动栅极相对,并且在作为元件隔离结构的场氧化物膜上介于其间的电介质膜电容耦合到浮动栅极。 字线在形成在位线上的绝缘膜上延伸以跨越位线并且电连接到下反相电极。 因此,位线基本上存在于字线下面。 同时形成存储单元部分的浮置栅极,外围电路部分的栅极,栅极反电极以及存储单元部分的位线和外围电路部分的布线层。
    • 96. 发明授权
    • Nonvolatile semiconductor memory device and method of producing the same
    • 非易失性半导体存储器件及其制造方法
    • US5594688A
    • 1997-01-14
    • US499379
    • 1995-07-07
    • Yasuo Sato
    • Yasuo Sato
    • H01L21/8247H01L27/115H01L29/423H01L29/788H01L29/792
    • H01L27/11521H01L27/115H01L29/42324
    • A nonvolatile semiconductor memory device has a semiconductor substrate of a first conductivity type, at least a pair of element isolation insulating films and a pair of spaced source/drawn regions of a second conductivity type different from the first conductivity type and formed in a surface of the semiconductor substrate. A floating gate electrode is formed above a channel region disposed between the pair of source/drain regions in the surface of the semiconductor substrate in an insulated relationship with the channel region. The floating gate electrode overlaps each of the element isolation insulating films and a gap is formed between an underside of the floating gate electrode and each of the element isolation insulating films at each of portions thereof where the floating gate electrode overlaps the pair of element isolation insulating films, respectively. A control gate electrode is formed above the floating gate electrode in an insulated relationship with the floating gate electrode. A part of the control gate electrode extends beyond a side of the floating gate electrode to an underside of the floating gate electrode facing each of the gaps.
    • 非易失性半导体存储器件具有第一导电类型的半导体衬底,至少一对元件隔离绝缘膜和与第一导电类型不同的第二导电类型的一对隔开的源极/引出区域,并且形成在 半导体衬底。 在与沟道区域绝缘的关系中,在设置在半导体衬底的表面中的一对源极/漏极区域之间的沟道区域上方形成浮栅电极。 浮栅电极与每个元件隔离绝缘膜重叠,并且在浮置栅电极与一对元件隔离绝缘层重叠的部分的每个部分处,在浮置栅电极的下侧和每个元件隔离绝缘膜之间形成间隙 电影。 控制栅电极以与浮置栅电极绝缘的关系形成在浮置栅电极的上方。 控制栅电极的一部分延伸超过浮栅电极的一侧,面向每个间隙的浮栅电极的下侧。