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91. 发明授权

US08154928B2 Integrated flash memory systems and methods for load compensation 有权
标题翻译：集成闪存系统和负载补偿方法
公开(公告)号：US08154928B2
公开(公告)日：2012-04-10
申请号：US12947719
申请日：2010-11-16
申请人： Hieu Van Tran
发明人： Hieu Van Tran
IPC分类号： G11C16/06
CPC分类号： G11C16/26
摘要： Systems and methods are disclosed including features that compensate for variations in the magnitude of supply voltages used in memory arrays. According to some aspects, compensation circuits may provide a tunable current-limiting load for data columns, where the load can be tuned to dynamically compensate for variations in supply voltage. In certain aspects, a compensation circuit may employ an operational amplifier configured as a voltage follower. The voltage follower compensates for any variations in supply voltage, forcing a constant voltage drop across the load element(s), thus maintaining a constant load. Other circuits may also be included, such as precharge circuits, clamp circuits, buffer circuits, trimming circuit, and sense amplifier circuits with sensed body effect. System-On-Chip integrated system aspects may include a microcontroller, a mixed IP, and a flash memory system having functionality and blocks that interface and interoperate with each other for load compensation.
摘要翻译：公开了系统和方法，其包括补偿存储器阵列中使用的电源电压的幅度变化的特征。根据一些方面，补偿电路可以为数据列提供可调谐的限流负载，其中可以调整负载来动态补偿电源电压的变化。在某些方面，补偿电路可以采用配置为电压跟随器的运算放大器。电压跟随器补偿电源电压的任何变化，迫使负载元件上的恒定电压降，从而保持恒定的负载。还可以包括其他电路，例如预充电电路，钳位电路，缓冲电路，微调电路，以及感测体效应的读出放大器电路。片上系统集成系统方面可以包括微控制器，混合IP和闪存系统，其具有彼此接口和互操作以进行负载补偿的功能和块。

92. 发明授权

US08049535B2 Sense amplifier for low voltage high speed sensing 有权
标题翻译：用于低电压高速感应的感应放大器
公开(公告)号：US08049535B2
公开(公告)日：2011-11-01
申请号：US12972974
申请日：2010-12-20
申请人： Hieu Van Tran , Sang Thanh Nguyen , Hung Quoc Nguyen
发明人： Hieu Van Tran , Sang Thanh Nguyen , Hung Quoc Nguyen
IPC分类号： G01R19/00
CPC分类号： G11C11/5642 , G11C7/06 , G11C7/062
摘要： A memory system includes a sense amplifier for detecting content of data memory cells by comparison with a voltage stored in a reference cell. The sense amplifier may comprise a comparator, first and second load circuits, and a low impedance circuit. A first input of the comparator is coupled to the low impedance circuit and a reference voltage node. A second input of the comparator is coupled to a data voltage node. The first load circuit loads a reference cell coupled to the reference voltage node. The second load circuit loads a data cell coupled to the data voltage node.
摘要翻译：存储器系统包括用于通过与存储在参考单元中的电压进行比较来检测数据存储单元的内容的读出放大器。读出放大器可以包括比较器，第一和第二负载电路以及低阻抗电路。比较器的第一输入耦合到低阻抗电路和参考电压节点。比较器的第二输入耦合到数据电压节点。第一负载电路加载耦合到参考电压节点的参考电池。第二负载电路加载耦合到数据电压节点的数据单元。

93. 发明申请

US20110110170A1 Non-volatile memory systems and methods including page read and/or configuration features 有权
标题翻译：非易失性存储器系统和方法，包括页面读取和/或配置特征
公开(公告)号：US20110110170A1
公开(公告)日：2011-05-12
申请号：US12961458
申请日：2010-12-06
申请人： Hieu Van Tran , Sakhawat M. Khan
发明人： Hieu Van Tran , Sakhawat M. Khan
IPC分类号： G11C7/00
CPC分类号： G11C16/10 , G11C11/5621 , G11C11/5628 , G11C11/5635 , G11C11/5642 , G11C11/5678 , G11C13/0004 , G11C16/08 , G11C16/24 , G11C16/28 , G11C27/005 , G11C2211/5634
摘要： A high speed voltage mode sensing is provided for a digital multibit non-volatile memory integrated system. An embodiment has a local source follower stage followed by a high speed common source stage. Another embodiment has a local source follower stage followed by a high speed source follower stage. Another embodiment has a common source stage followed by a source follower. An auto zeroing scheme is used. A capacitor sensing scheme is used. Multilevel parallel operation is described.
摘要翻译：为数字多位非易失性存储器集成系统提供高速电压模式感测。一个实施例具有本地源跟随器阶段，之后是高速公共源级。另一个实施例具有本地源极跟随器级，之后是高速源极跟随器级。另一个实施例具有公共源级，之后是源跟随器。使用自动归零方案。使用电容感测方案。描述多级并行操作。

94. 发明申请

US20110058425A1 Integrated Flash Memory Systems And Methods For Load Compensation 有权
标题翻译：集成闪存系统和负载补偿方法
公开(公告)号：US20110058425A1
公开(公告)日：2011-03-10
申请号：US12947719
申请日：2010-11-16
申请人： Hieu Van Tran
发明人： Hieu Van Tran
IPC分类号： G11C16/06 , G11C16/04
CPC分类号： G11C16/26
摘要： Systems and methods are disclosed including features that compensate for variations in the magnitude of supply voltages used in memory arrays. According to some aspects, compensation circuits may provide a tunable current-limiting load for data columns, where the load can be tuned to dynamically compensate for variations in supply voltage. In certain aspects, a compensation circuit may employ an operational amplifier configured as a voltage follower. The voltage follower compensates for any variations in supply voltage, forcing a constant voltage drop across the load element(s), thus maintaining a constant load. Other circuits may also be included, such as precharge circuits, clamp circuits, buffer circuits, trimming circuit, and sense amplifier circuits with sensed body effect. System-On-Chip integrated system aspects may include a microcontroller, a mixed IP, and a flash memory system having functionality and blocks that interface and interoperate with each other for load compensation.
摘要翻译：公开了系统和方法，其包括补偿存储器阵列中使用的电源电压的幅度变化的特征。根据一些方面，补偿电路可以为数据列提供可调谐的限流负载，其中可以调整负载来动态补偿电源电压的变化。在某些方面，补偿电路可以采用配置为电压跟随器的运算放大器。电压跟随器补偿电源电压的任何变化，迫使负载元件上的恒定电压降，从而保持恒定的负载。还可以包括其他电路，例如预充电电路，钳位电路，缓冲电路，微调电路，以及感测体效应的读出放大器电路。片上系统集成系统方面可以包括微控制器，混合IP和闪存系统，其具有彼此接口和互操作以进行负载补偿的功能和块。

95. 发明申请

US20100202200A1 Power Line Compensation for Flash Memory Sense Amplifiers 有权
标题翻译：闪存读数放大器的电源线补偿
公开(公告)号：US20100202200A1
公开(公告)日：2010-08-12
申请号：US12766682
申请日：2010-04-23
申请人： Hieu Van Tran
发明人： Hieu Van Tran
IPC分类号： G11C16/02 , G11C16/28 , G11C16/04
CPC分类号： G11C7/062 , G11C5/147 , G11C7/02 , G11C7/06 , G11C7/065 , G11C7/067 , G11C11/4091 , G11C11/5642 , G11C16/28 , G11C16/30 , G11C2207/063 , G11C2211/5645
摘要： In one aspect, the invention concerns a memory system that compensates for power level variations in sense amplifiers for multilevel memory. For example, a compensation circuit can be employed to compensate for current or voltage variations in the power supplied to multilevel memory sense amplifiers. As another example, compensation can be accomplished by application of a bias voltage to the power supply. Another example is a sense amplifier configured with improved input common mode voltage range. Such sense amplifiers can be two-pair and three-pair sense amplifiers. Further examples of the invention include more simplified sense amplifier configurations, and sense amplifiers having reduced leakage current.
摘要翻译：一方面，本发明涉及一种用于补偿多电平存储器的读出放大器中的功率电平变化的存储器系统。例如，可以采用补偿电路来补偿提供给多电平存储器读出放大器的功率的电流或电压变化。作为另一示例，可以通过向电源施加偏置电压来实现补偿。另一个例子是配置有改进的输入共模电压范围的读出放大器。这样的读出放大器可以是两对和三对读出放大器。本发明的其它示例包括更简化的读出放大器配置和具有减小的漏电流的读出放大器。

96. 发明授权

US07631231B2 Method and apparatus for testing the connectivity of a flash memory chip 有权
标题翻译：用于测试闪存芯片连接性的方法和装置
公开(公告)号：US07631231B2
公开(公告)日：2009-12-08
申请号：US11407602
申请日：2006-04-19
申请人： Sang Thanh Nguyen , Hieu Van Tran , Hung O. Nguyen , Phil Klotzkin
发明人： Sang Thanh Nguyen , Hieu Van Tran , Hung O. Nguyen , Phil Klotzkin
IPC分类号： G11C29/00 , G01R31/28 , G11C7/00
CPC分类号： G11C29/02 , G11C29/022 , G11C2029/3202
摘要： In one embodiment of the invention, circuitry and hardware for connectivity testing are fabricated on an IC, and in particular an IC containing a flash memory array. This testing circuitry is electrically connected to the bond pads of the IC. In some embodiments, the testing circuitry includes a boundary scan cell connected to each bond pad, allowing for rapid connectivity testing of flash memory chips in accordance with testing standards such as the JTAG standard. The invention further includes methods in which the pins and/or memory cells of a flash memory chip are sequentially sent a series of data so as to test the connectivity of portions of the IC. The sequentially-sent data is then retrieved and compared to the original data. Discrepancies between these sets of data thus highlight connectivity problems in the IC.
摘要翻译：在本发明的一个实施例中，用于连接测试的电路和硬件被制造在IC上，特别是包含闪存阵列的IC。该测试电路电连接到IC的接合焊盘。在一些实施例中，测试电路包括连接到每个接合焊盘的边界扫描单元，允许根据诸如JTAG标准的测试标准对闪存芯片进行快速连接测试。本发明还包括其中闪存芯片的引脚和/或存储单元被顺序地发送一系列数据以便测试IC的部分连通性的方法。然后检索顺序发送的数据并将其与原始数据进行比较。因此，这些数据集之间的差异突出了IC中的连接问题。

97. 发明申请

US20090096507A1 Integrated Semiconductor Metal-Insulator-Semiconductor Capacitor 审中-公开
标题翻译：集成半导体金属绝缘体 - 半导体电容器
公开(公告)号：US20090096507A1
公开(公告)日：2009-04-16
申请号：US12270604
申请日：2008-11-13
申请人： Feng Gao , Changyuan Chen , Vishal Sarin , William John Saiki , Hieu Van Tran , Dana Lee
发明人： Feng Gao , Changyuan Chen , Vishal Sarin , William John Saiki , Hieu Van Tran , Dana Lee
IPC分类号： H03K3/01
CPC分类号： H01L27/0805 , H01L27/0811 , H01L29/94
摘要： An integrated MIS capacitor has two substantially identical MIS capacitors. A first capacitor comprises a first region of a first conductivity type adjacent to a channel region of the first conductivity type in a semiconductor substrate. The semiconductor substrate has a second conductivity type. A gate electrode is insulated and spaced apart from the channel region of the first capacitor. The second capacitor is substantially identical to the first capacitor and is formed in the same semiconductor substrate. The gate electrode of the first capacitor is electrically connected to the first region of the second capacitor and the gate electrode of the second capacitor is electrically connected to the first region of the first capacitor. In this manner, the capacitors are connected in an anti-parallel configuration. A capacitor which has high capacitance densities, low process complexity, ambipolar operation, low voltage and temperature coefficient, low external parasitic resistance and capacitance and good matching characteristics for use in analog designs that can be integrated with existing semiconductor processes results.
摘要翻译：集成的MIS电容器具有两个基本相同的MIS电容器。第一电容器包括在半导体衬底中与第一导电类型的沟道区相邻的第一导电类型的第一区域。半导体衬底具有第二导电类型。栅电极与第一电容器的沟道区隔离并隔开。第二电容器基本上与第一电容器相同，并且形成在相同的半导体衬底中。第一电容器的栅电极电连接到第二电容器的第一区域，并且第二电容器的栅极电连接到第一电容器的第一区域。以这种方式，电容器以反并联配置连接。具有高电容密度，低工艺复杂性，双极性操作，低电压和温度系数，低外部寄生电阻和电容以及用于可与现有半导体工艺结合的模拟设计的良好匹配特性的电容器。

98. 发明申请

US20080239834A1 SENSE AMPLIFIER FOR LOW VOLTAGE HIGH SPEED SENSING 有权
标题翻译：用于低电压高速感应的感应放大器
公开(公告)号：US20080239834A1
公开(公告)日：2008-10-02
申请号：US11942665
申请日：2007-11-19
申请人： Hieu Van Tran , Sang Thanh Nguyen , Hung Quoc Nguyen
发明人： Hieu Van Tran , Sang Thanh Nguyen , Hung Quoc Nguyen
IPC分类号： G01R19/00 , G11C7/00
CPC分类号： G11C11/5642 , G11C7/06 , G11C7/062
摘要： A memory system includes a sense amplifier for detecting content of data memory cells by comparison with a voltage stored in a reference cell. The sense amplifier may comprise a comparator, first and second load circuits, and a low impedance circuit. A first input of the comparator is coupled to the low impedance circuit and a reference voltage node. A second input of the comparator is coupled to a data voltage node. The first load circuit loads a reference cell coupled to the reference voltage node. The second load circuit loads a data cell coupled to the data voltage node.
摘要翻译：存储器系统包括用于通过与存储在参考单元中的电压进行比较来检测数据存储单元的内容的读出放大器。读出放大器可以包括比较器，第一和第二负载电路以及低阻抗电路。比较器的第一输入耦合到低阻抗电路和参考电压节点。比较器的第二输入耦合到数据电压节点。第一负载电路加载耦合到参考电压节点的参考电池。第二负载电路加载耦合到数据电压节点的数据单元。

99. 发明授权

US07227217B2 Nonvolatile memory cell having floating gate, control gate and separate erase gate, an array of such memory cells, and method of manufacturing 有权
标题翻译：具有浮动栅极，控制栅极和单独的擦除栅极的非易失性存储单元，这种存储单元的阵列以及制造方法
公开(公告)号：US07227217B2
公开(公告)日：2007-06-05
申请号：US11078562
申请日：2005-02-28
申请人： Amitay Levi , Pavel Klinger , Bomy Chen , Hieu Van Tran , Dana Lee , Jack E. Frayer
发明人： Amitay Levi , Pavel Klinger , Bomy Chen , Hieu Van Tran , Dana Lee , Jack E. Frayer
IPC分类号： H01L29/788 , H01L29/76
CPC分类号： H01L27/11521 , H01L27/115 , H01L29/42328 , H01L29/7885
摘要： A nonvolatile memory cell having a floating gate for the storage of charges thereon has a control gate and a separate erase gate. The cell is programmed by hot channel electron injection and is erased by poly to poly Fowler-Nordheim tunneling. A method for making an array of unidirectional cells in a planar substrate, as well as an array of bidirectional cells in a substrate having a trench, is disclosed. An array of such cells and a method of making such an array is also disclosed.
摘要翻译：具有用于存储电荷的浮动栅极的非易失性存储单元具有控制栅极和单独的擦除栅极。该电池通过热通道电子注入进行编程，并被poly-poly Fowler-Nordheim隧道擦除。公开了一种用于在平面基板中制造单向单元阵列的方法，以及在具有沟槽的基板中的双向单元阵列。还公开了这样的单元阵列和制造这种阵列的方法。

100. 发明授权

US07196927B2 Wide dynamic range and high speed voltage mode sensing for a multilevel digital non-volatile memory 有权
公开(公告)号：US07196927B2
公开(公告)日：2007-03-27
申请号：US10764381
申请日：2004-01-22
申请人： Hieu Van Tran , Sakhawat M. Khan
发明人： Hieu Van Tran , Sakhawat M. Khan
IPC分类号： G11C11/34 , G11C7/00
CPC分类号： G11C11/5621 , G11C11/5628 , G11C11/5635 , G11C11/5642 , G11C11/5678 , G11C13/0004 , G11C16/08 , G11C16/10 , G11C16/24 , G11C16/28 , G11C27/005 , G11C2211/5634
摘要： A high speed voltage mode sensing is provided for a digital multibit non-volatile memory integrated system. An embodiment has a local source follower stage followed by a high speed common source stage. Another embodiment has a local source follower stage followed by a high speed source follower stage. Another embodiment has a common source stage followed by a source follower. An auto zeroing scheme is used. A capacitor sensing scheme is used. Multilevel parallel operation is described.

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